From: Alexei Filippov <alexei.filippov@syntacore.com>
To: <dbarboza@ventanamicro.com>
Cc: <alexei.filippov@syntacore.com>, <alistair.francis@wdc.com>,
<bin.meng@windriver.com>, <liwei1518@gmail.com>,
<palmer@dabbelt.com>, <qemu-devel@nongnu.org>,
<qemu-riscv@nongnu.org>, <zhiwei_liu@linux.alibaba.com>
Subject: [PATCH v2 2/2] target/riscv: do not set mtval2 for non guest-page faults
Date: Fri, 3 May 2024 13:30:52 +0300 [thread overview]
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com> (raw)
In-Reply-To: <ca275792-36c9-4ccd-b7b2-24d9fd837b24@ventanamicro.com>
Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
translation part, mtval2 will be set in case of successes 2 stage translation but
failed pmp check.
In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
page-fault is taken into M-mode, mtval2 is written with either zero or guest
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
is set to zero...*
Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
Changes since v1:
-Added Reviewed-by tag.
target/riscv/cpu_helper.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e3a7797d00..484edad900 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1375,17 +1375,17 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
__func__, pa, ret, prot_pmp, tlb_size);
prot &= prot_pmp;
- }
-
- if (ret != TRANSLATE_SUCCESS) {
+ } else {
/*
* Guest physical address translation failed, this is a HS
* level exception
*/
first_stage_error = false;
- env->guest_phys_fault_addr = (im_address |
- (address &
- (TARGET_PAGE_SIZE - 1))) >> 2;
+ if (ret != TRANSLATE_PMP_FAIL) {
+ env->guest_phys_fault_addr = (im_address |
+ (address &
+ (TARGET_PAGE_SIZE - 1))) >> 2;
+ }
}
}
} else {
--
2.34.1
next prev parent reply other threads:[~2024-05-03 10:32 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-13 10:59 [PATCH 1/2] target/riscv: prioritize pmp errors in raise_mmu_exception() Alexei Filippov
2024-04-13 10:59 ` [PATCH 2/2] target/riscv: do not set mtval2 for non guest-page faults Alexei Filippov
2024-04-29 9:43 ` Daniel Henrique Barboza
2024-05-03 10:30 ` Alexei Filippov [this message]
2024-05-14 5:59 ` [PATCH v2 " Alistair Francis
2024-05-14 6:16 ` Alistair Francis
2024-04-15 18:50 ` [PATCH 1/2] target/riscv: prioritize pmp errors in raise_mmu_exception() Joseph Chan
2024-04-16 3:14 ` Joseph Chan
2024-05-14 5:48 ` Alistair Francis
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