From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>
Subject: [PATCH 1/5] target/mips: Make globalnumber a CPU property
Date: Mon, 06 May 2024 16:31:35 +0100 [thread overview]
Message-ID: <20240506-mips-smp-v1-1-3cc234786910@flygoat.com> (raw)
In-Reply-To: <20240506-mips-smp-v1-0-3cc234786910@flygoat.com>
GlobalNumber marks topology information of a CPU instance.
Make it a CPU property to allow CPS to override topology information.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
target/mips/cpu.c | 16 +++++++++++++++-
target/mips/cpu.h | 10 +++++++++-
target/mips/sysemu/machine.c | 5 ++---
3 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index bbe01d07dd..762000d09b 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -296,7 +296,6 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)
env->CP0_Random = env->tlb->nb_tlb - 1;
env->tlb->tlb_in_use = env->tlb->nb_tlb;
env->CP0_Wired = 0;
- env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId;
env->CP0_EBase = KSEG0_BASE | (cs->cpu_index & 0x3FF);
if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
@@ -484,6 +483,12 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
env->exception_base = (int32_t)0xBFC00000;
+#if !defined(CONFIG_USER_ONLY)
+ if (env->CP0_GlobalNumber == -1) {
+ env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId;
+ }
+#endif
+
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
mmu_init(env, env->cpu_model);
#endif
@@ -563,6 +568,13 @@ static const TCGCPUOps mips_tcg_ops = {
};
#endif /* CONFIG_TCG */
+static Property mips_cpu_properties[] = {
+#if !defined(CONFIG_USER_ONLY)
+ DEFINE_PROP_INT32("globalnumber", MIPSCPU, env.CP0_GlobalNumber, -1),
+#endif
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void mips_cpu_class_init(ObjectClass *c, void *data)
{
MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
@@ -592,6 +604,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
#ifdef CONFIG_TCG
cc->tcg_ops = &mips_tcg_ops;
#endif /* CONFIG_TCG */
+
+ device_class_set_props(dc, mips_cpu_properties);
}
static const TypeInfo mips_cpu_type_info = {
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 3e906a175a..7499608678 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -612,8 +612,13 @@ typedef struct CPUArchState {
# define CP0EnLo_RI 31
# define CP0EnLo_XI 30
#endif
- int32_t CP0_GlobalNumber;
+ /* CP0_GlobalNumber is preserved across CPU reset. */
#define CP0GN_VPId 0
+#define CP0GN_VPId_MASK (0xFFUL << CP0GN_VPId)
+#define CP0GN_CoreNum 8
+#define CP0GN_CoreNum_MASK (0xFUL << CP0GN_CoreNum)
+#define CP0GN_ClusterNum 16
+#define CP0GN_ClusterNum_MASK (0xFUL << CP0GN_ClusterNum)
/*
* CP0 Register 4
*/
@@ -1175,6 +1180,9 @@ typedef struct CPUArchState {
struct {} end_reset_fields;
/* Fields from here on are preserved across CPU reset. */
+#if !defined(CONFIG_USER_ONLY)
+ int32_t CP0_GlobalNumber;
+#endif
CPUMIPSMVPContext *mvp;
#if !defined(CONFIG_USER_ONLY)
CPUMIPSTLBContext *tlb;
diff --git a/target/mips/sysemu/machine.c b/target/mips/sysemu/machine.c
index 213fd637fc..235d640862 100644
--- a/target/mips/sysemu/machine.c
+++ b/target/mips/sysemu/machine.c
@@ -218,8 +218,8 @@ static const VMStateDescription vmstate_tlb = {
const VMStateDescription vmstate_mips_cpu = {
.name = "cpu",
- .version_id = 21,
- .minimum_version_id = 21,
+ .version_id = 22,
+ .minimum_version_id = 22,
.post_load = cpu_post_load,
.fields = (const VMStateField[]) {
/* Active TC */
@@ -257,7 +257,6 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
- VMSTATE_INT32(env.CP0_GlobalNumber, MIPSCPU),
VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU),
VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
--
2.34.1
next prev parent reply other threads:[~2024-05-06 15:32 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-06 15:31 [PATCH 0/5] hw/mips: Proper multi core support Jiaxun Yang
2024-05-06 15:31 ` Jiaxun Yang [this message]
2024-05-06 15:31 ` [PATCH 2/5] hw/msic/mips_cmgcr: Implement multicore functions Jiaxun Yang
2024-05-06 15:31 ` [PATCH 3/5] hw/msic/mips_cpc: Implement multi core support Jiaxun Yang
2024-05-06 15:31 ` [PATCH 4/5] hw/mips/cps: " Jiaxun Yang
2024-05-06 15:31 ` [PATCH 5/5] hw/mips/boston: " Jiaxun Yang
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