From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, zhao1.liu@intel.com
Subject: [PATCH v2 19/25] target/i386: move remaining conditional operations to new decoder
Date: Mon, 6 May 2024 10:09:51 +0200 [thread overview]
Message-ID: <20240506080957.10005-20-pbonzini@redhat.com> (raw)
In-Reply-To: <20240506080957.10005-1-pbonzini@redhat.com>
Move long-displacement Jcc, SETcc and CMOVcc to the new decoder.
While filling in the tables makes the code seem longer, the new
emitters are all just one line of code.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.h | 1 +
target/i386/tcg/translate.c | 2 +-
target/i386/tcg/decode-new.c.inc | 56 ++++++++++++++++++++++++++++++++
target/i386/tcg/emit.c.inc | 10 ++++++
4 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h
index 77bb31eb143..cd7ceca21e8 100644
--- a/target/i386/tcg/decode-new.h
+++ b/target/i386/tcg/decode-new.h
@@ -106,6 +106,7 @@ typedef enum X86CPUIDFeature {
X86_FEAT_AVX2,
X86_FEAT_BMI1,
X86_FEAT_BMI2,
+ X86_FEAT_CMOV,
X86_FEAT_CMPCCXADD,
X86_FEAT_F16C,
X86_FEAT_FMA,
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index b94d9504090..a80021930bf 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -3206,7 +3206,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
#ifndef CONFIG_USER_ONLY
use_new &= b <= limit;
#endif
- if (use_new && 0) {
+ if (use_new && (b >= 0x138 && b <= 0x19f)) {
disas_insn_new(s, cpu, b);
return true;
}
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index a47ecab6dd4..7528e9e4f07 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -993,6 +993,15 @@ static const X86OpEntry opcodes_0F[256] = {
/* Incorrectly listed as Mq,Vq in the manual */
[0x17] = X86_OP_ENTRY3(VMOVHPx_st, M,q, None,None, V,dq, vex5 p_00_66),
+ [0x40] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x41] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x42] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x43] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x44] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x45] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x46] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x47] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+
[0x50] = X86_OP_ENTRY3(MOVMSK, G,y, None,None, U,x, vex7 p_00_66),
[0x51] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), /* sqrtps */
[0x52] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3), /* rsqrtps */
@@ -1020,6 +1029,24 @@ static const X86OpEntry opcodes_0F[256] = {
[0x76] = X86_OP_ENTRY3(PCMPEQD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
[0x77] = X86_OP_GROUP0(0F77),
+ [0x80] = X86_OP_ENTRYr(Jcc, J,z_f64),
+ [0x81] = X86_OP_ENTRYr(Jcc, J,z_f64),
+ [0x82] = X86_OP_ENTRYr(Jcc, J,z_f64),
+ [0x83] = X86_OP_ENTRYr(Jcc, J,z_f64),
+ [0x84] = X86_OP_ENTRYr(Jcc, J,z_f64),
+ [0x85] = X86_OP_ENTRYr(Jcc, J,z_f64),
+ [0x86] = X86_OP_ENTRYr(Jcc, J,z_f64),
+ [0x87] = X86_OP_ENTRYr(Jcc, J,z_f64),
+
+ [0x90] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x91] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x92] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x93] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x94] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x95] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x96] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x97] = X86_OP_ENTRYw(SETcc, E,b),
+
[0x28] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1 p_00_66), /* MOVAPS */
[0x29] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 p_00_66), /* MOVAPS */
[0x2A] = X86_OP_GROUP0(0F2A),
@@ -1032,6 +1059,15 @@ static const X86OpEntry opcodes_0F[256] = {
[0x38] = X86_OP_GROUP0(0F38),
[0x3a] = X86_OP_GROUP0(0F3A),
+ [0x48] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x49] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x4a] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x4b] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x4c] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x4d] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x4e] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x4f] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+
[0x58] = X86_OP_ENTRY3(VADD, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
[0x59] = X86_OP_ENTRY3(VMUL, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
[0x5a] = X86_OP_GROUP0(0F5A),
@@ -1057,6 +1093,24 @@ static const X86OpEntry opcodes_0F[256] = {
[0x7e] = X86_OP_GROUP0(0F7E),
[0x7f] = X86_OP_GROUP0(0F7F),
+ [0x88] = X86_OP_ENTRYr(Jcc, J,z_f64),
+ [0x89] = X86_OP_ENTRYr(Jcc, J,z_f64),
+ [0x8a] = X86_OP_ENTRYr(Jcc, J,z_f64),
+ [0x8b] = X86_OP_ENTRYr(Jcc, J,z_f64),
+ [0x8c] = X86_OP_ENTRYr(Jcc, J,z_f64),
+ [0x8d] = X86_OP_ENTRYr(Jcc, J,z_f64),
+ [0x8e] = X86_OP_ENTRYr(Jcc, J,z_f64),
+ [0x8f] = X86_OP_ENTRYr(Jcc, J,z_f64),
+
+ [0x98] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x99] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x9a] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x9b] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x9c] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x9d] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x9e] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x9f] = X86_OP_ENTRYw(SETcc, E,b),
+
[0xae] = X86_OP_GROUP0(group15),
[0xc2] = X86_OP_ENTRY4(VCMP, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
@@ -1918,6 +1972,8 @@ static bool has_cpuid_feature(DisasContext *s, X86CPUIDFeature cpuid)
switch (cpuid) {
case X86_FEAT_None:
return true;
+ case X86_FEAT_CMOV:
+ return (s->cpuid_features & CPUID_CMOV);
case X86_FEAT_F16C:
return (s->cpuid_ext_features & CPUID_EXT_F16C);
case X86_FEAT_FMA:
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index ffe458b80f9..a48ff1536a4 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -1386,6 +1386,11 @@ static void gen_CMC(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
}
+static void gen_CMOVcc(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_cmovcc1(s, decode->b & 0xf, s->T0, s->T1);
+}
+
static void gen_CMPccXADD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
TCGLabel *label_top = gen_new_label();
@@ -3298,6 +3303,11 @@ static void gen_SCAS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
}
}
+static void gen_SETcc(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ gen_setcc1(s, decode->b & 0xf, s->T0);
+}
+
static void gen_SHA1NEXTE(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
gen_helper_sha1nexte(OP_PTR0, OP_PTR1, OP_PTR2);
--
2.45.0
next prev parent reply other threads:[~2024-05-06 8:13 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-06 8:09 [PATCH v2 00/25] target/i386: convert 1-byte opcodes to new decoder Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 01/25] target/i386: use TSTEQ/TSTNE to test low bits Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 02/25] target/i386: use TSTEQ/TSTNE to check flags Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 03/25] target/i386: remove mask from CCPrepare Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 04/25] target/i386: cc_op is not dynamic in gen_jcc1 Paolo Bonzini
2024-05-06 15:53 ` Richard Henderson
2024-05-06 8:09 ` [PATCH v2 05/25] target/i386: cleanup cc_op changes for REP/REPZ/REPNZ Paolo Bonzini
2024-05-06 16:07 ` Richard Henderson
2024-05-06 16:31 ` Paolo Bonzini
2024-05-06 16:39 ` Richard Henderson
2024-05-06 8:09 ` [PATCH v2 06/25] target/i386: pull cc_op update to callers of gen_jmp_rel{, _csize} Paolo Bonzini
2024-05-06 16:12 ` [PATCH v2 06/25] target/i386: pull cc_op update to callers of gen_jmp_rel{,_csize} Richard Henderson
2024-05-06 8:09 ` [PATCH v2 07/25] target/i386: extend cc_* when using them to compute flags Paolo Bonzini
2024-05-06 16:16 ` Richard Henderson
2024-05-06 8:09 ` [PATCH v2 08/25] target/i386: do not use s->T0 and s->T1 as scratch registers for CCPrepare Paolo Bonzini
2024-05-06 16:18 ` Richard Henderson
2024-05-06 8:09 ` [PATCH v2 09/25] target/i386: clarify the "reg" argument of functions returning CCPrepare Paolo Bonzini
2024-05-06 16:19 ` Richard Henderson
2024-05-06 8:09 ` [PATCH v2 10/25] target/i386: cleanup *gen_eob* Paolo Bonzini
2024-05-06 16:21 ` Richard Henderson
2024-05-06 8:09 ` [PATCH v2 11/25] target/i386: reintroduce debugging mechanism Paolo Bonzini
2024-05-06 16:23 ` Richard Henderson
2024-05-06 8:09 ` [PATCH v2 12/25] target/i386: move 00-5F opcodes to new decoder Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 13/25] target/i386: extract gen_far_call/jmp, reordering temporaries Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 14/25] target/i386: allow instructions with more than one immediate Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 15/25] target/i386: move 60-BF opcodes to new decoder Paolo Bonzini
2024-05-06 16:44 ` Richard Henderson
2024-05-06 8:09 ` [PATCH v2 16/25] target/i386: generalize gen_movl_seg_T0 Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 17/25] target/i386: move C0-FF opcodes to new decoder (except for x87) Paolo Bonzini
2024-05-06 16:56 ` Richard Henderson
2024-05-06 8:09 ` [PATCH v2 18/25] target/i386: merge and enlarge a few ranges for call to disas_insn_new Paolo Bonzini
2024-05-06 8:09 ` Paolo Bonzini [this message]
2024-05-06 8:09 ` [PATCH v2 20/25] target/i386: move BSWAP to new decoder Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 21/25] target/i386: port extensions of one-byte opcodes " Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 22/25] target/i386: remove now-converted opcodes from old decoder Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 23/25] target/i386: decode x87 instructions in a separate function Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 24/25] target/i386: split legacy decoder into " Paolo Bonzini
2024-05-06 8:09 ` [PATCH v2 25/25] target/i386: remove duplicate prefix decoding Paolo Bonzini
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240506080957.10005-20-pbonzini@redhat.com \
--to=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=zhao1.liu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).