From: Zhao Liu <zhao1.liu@intel.com>
To: "Tejus GK" <tejus.gk@nutanix.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Daniel P . Berrangé" <berrange@redhat.com>
Cc: Babu Moger <babu.moger@amd.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
Zhenyu Wang <zhenyu.z.wang@intel.com>,
Zhuocheng Ding <zhuocheng.ding@intel.com>,
Xiaoyao Li <xiaoyao.li@intel.com>,
Dapeng Mi <dapeng1.mi@intel.com>,
Yongwei Ma <yongwei.ma@intel.com>, Zhao Liu <zhao1.liu@intel.com>
Subject: Re: [PATCH v11 19/21] i386: Add cache topology info in CPUCacheInfo
Date: Mon, 6 May 2024 15:32:21 +0800 [thread overview]
Message-ID: <ZjiHhVSEjyxitWvg@intel.com> (raw)
In-Reply-To: <6766AC1F-96D1-41F0-AAEB-CE4158662A51@nutanix.com>
Hi Tejus,
(Also +Paolo/Daniel)
On Tue, Apr 30, 2024 at 06:14:52AM +0000, Tejus GK wrote:
> Date: Tue, 30 Apr 2024 06:14:52 +0000
> From: Tejus GK <tejus.gk@nutanix.com>
> Subject: Re: [PATCH v11 19/21] i386: Add cache topology info in CPUCacheInfo
>
>
>
> On 24 Apr 2024, at 9:19 PM, Zhao Liu <zhao1.liu@intel.com> wrote:
>
> @@ -2140,6 +2164,7 @@ static const CPUCaches epyc_milan_cache_info = {
> .lines_per_tag = 1,
> .self_init = 1,
> .no_invd_sharing = true,
> + .share_level = CPU_TOPO_LEVEL_CORE,
> },
> .l1i_cache = &(CPUCacheInfo) {
> .type = INSTRUCTION_CACHE,
> @@ -2152,6 +2177,7 @@ static const CPUCaches epyc_milan_cache_info = {
> .lines_per_tag = 1,
> .self_init = 1,
> .no_invd_sharing = true,
> + .share_level = CPU_TOPO_LEVEL_CORE,
> },
> .l2_cache = &(CPUCacheInfo) {
> .type = UNIFIED_CACHE,
> @@ -2162,6 +2188,7 @@ static const CPUCaches epyc_milan_cache_info = {
> .partitions = 1,
> .sets = 1024,
> .lines_per_tag = 1,
> + .share_level = CPU_TOPO_LEVEL_CORE,
> },
> .l3_cache = &(CPUCacheInfo) {
> .type = UNIFIED_CACHE,
> @@ -2175,6 +2202,7 @@ static const CPUCaches epyc_milan_cache_info = {
> .self_init = true,
> .inclusive = true,
> .complex_indexing = true,
> + .share_level = CPU_TOPO_LEVEL_DIE,
> },
> };
>
>
> Hi Zhao and Babu, thank you for this patch. I have a slightly
> off-topic question about this patch. Firstly, many AMD CPU models
> have pre-defined cache sizes for the various cache levels; how are
> these values decided? I couldn't figure that out from the patches that
> introduced those changes.
I understand the AMD pre-defined cache idea started from this
discussion:
https://lore.kernel.org/qemu-devel/20180320175427.GU3417@localhost.localdomain/
From the discussion, it appears that AMD's cache information is encoded
according to the spec/datasheet for each generation of EPYC.
> Secondly, there isn't any pre-defined cache size for Intel, and the
> legacy cache values are used. This value can be vastly different from
> what actual available caches might be. Is there any reason why
> something like that for Intel has yet to be introduced?
Previously, there should be a lack of reason to introduce on Intel side,
or haven't met the relevant need/issue before.
I understand that AMD's reason is to make the cache information in the
Guest with a specific CPU model look more correct and to be able to
better emulate the Host environment.
Hi @Paolo and @Daniel, do you think Intel should also add correct cache
info for each CPU model?
Thanks,
Zhao
next prev parent reply other threads:[~2024-05-06 7:19 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-24 15:49 [PATCH v11 00/21] i386: Introduce smp.modules and clean up cache topology Zhao Liu
2024-04-24 15:49 ` [PATCH v11 01/21] hw/core/machine: Introduce the module as a CPU topology level Zhao Liu
2024-04-24 15:49 ` [PATCH v11 02/21] hw/core/machine: Support modules in -smp Zhao Liu
2024-04-24 15:49 ` [PATCH v11 03/21] hw/core: Introduce module-id as the topology subindex Zhao Liu
2024-04-24 15:49 ` [PATCH v11 04/21] hw/core: Support module-id in numa configuration Zhao Liu
2024-04-24 15:49 ` [PATCH v11 05/21] i386/cpu: Fix i/d-cache topology to core level for Intel CPU Zhao Liu
2024-04-24 15:49 ` [PATCH v11 06/21] i386/cpu: Use APIC ID info to encode cache topo in CPUID[4] Zhao Liu
2024-04-24 15:49 ` [PATCH v11 07/21] i386/cpu: Use APIC ID info get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Zhao Liu
2024-04-24 15:49 ` [PATCH v11 08/21] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() Zhao Liu
2024-04-24 15:49 ` [PATCH v11 09/21] i386/cpu: Introduce bitmap to cache available CPU topology levels Zhao Liu
2024-04-24 15:49 ` [PATCH v11 10/21] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] Zhao Liu
2024-04-24 15:49 ` [PATCH v11 11/21] i386/cpu: Decouple CPUID[0x1F] subleaf with specific topology level Zhao Liu
2024-04-24 15:49 ` [PATCH v11 12/21] i386: Introduce module level cpu topology to CPUX86State Zhao Liu
2024-04-24 15:49 ` [PATCH v11 13/21] i386: Support modules_per_die in X86CPUTopoInfo Zhao Liu
2024-04-24 15:49 ` [PATCH v11 14/21] i386: Expose module level in CPUID[0x1F] Zhao Liu
2024-04-24 15:49 ` [PATCH v11 15/21] i386: Support module_id in X86CPUTopoIDs Zhao Liu
2024-04-24 15:49 ` [PATCH v11 16/21] i386/cpu: Introduce module-id to X86CPU Zhao Liu
2024-04-24 15:49 ` [PATCH v11 17/21] tests: Add test case of APIC ID for module level parsing Zhao Liu
2024-04-24 15:49 ` [PATCH v11 18/21] hw/i386/pc: Support smp.modules for x86 PC machine Zhao Liu
2024-04-24 15:49 ` [PATCH v11 19/21] i386: Add cache topology info in CPUCacheInfo Zhao Liu
2024-04-30 6:14 ` Tejus GK
2024-05-06 7:32 ` Zhao Liu [this message]
2024-04-24 15:49 ` [PATCH v11 20/21] i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[4] Zhao Liu
2024-04-24 15:49 ` [PATCH v11 21/21] i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14] Zhao Liu
2024-04-25 8:06 ` [PATCH v11 00/21] i386: Introduce smp.modules and clean up cache topology Philippe Mathieu-Daudé
2024-04-25 13:30 ` Zhao Liu
2024-05-15 14:48 ` Zhao Liu
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