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[RFC PATCH v4 0/5] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions
 2024-06-20  7:50 UTC  (12+ messages)
` [RFC PATCH v4 1/5] accel/tcg: Avoid unnecessary call overhead from qemu_plugin_vcpu_mem_cb
` [RFC PATCH v4 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store
` [RFC PATCH v4 3/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride whole register load/store
` [RFC PATCH v4 4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions
` [RFC PATCH v4 5/5] target/riscv: Inline unit-stride ld/st and corresponding functions for performance

[PATCH] hw/riscv/virt.c: Make block devices default to virtio
 2024-06-20  6:47 UTC 

[PATCH v7 0/2] Support RISC-V IOPMP
 2024-06-20  2:30 UTC  (10+ messages)
` [PATCH v7 1/2] hw/misc/riscv_iopmp: Add RISC-V IOPMP device
` [PATCH v7 2/2] hw/riscv/virt: Add IOPMP support

[PATCH v2] target/riscv: fix instructions count handling in icount mode
 2024-06-19 19:56 UTC  (2+ messages)

Is there a way to check values of registers before and after running a program on qemu-system-risc64v?
 2024-06-19 18:20 UTC  (6+ messages)

[PATCH v2 00/12] Add support for RISC-V ACPI tests
 2024-06-19 18:05 UTC  (24+ messages)
` [PATCH v2 04/12] qtest: bios-tables-test: Rename aarch64 tests with aarch64 in them
` [PATCH v2 05/12] tests/qtest/bios-tables-test.c: Add support for arch in path
` [PATCH v2 06/12] tests/data/acpi/virt: Move ACPI tables under aarch64
` [PATCH v2 07/12] meson.build: Add RISC-V to the edk2-target list
` [PATCH v2 08/12] pc-bios/meson.build: Add support for RISC-V in unpack_edk2_blobs
` [PATCH v2 09/12] tests/data/acpi/rebuild-expected-aml.sh: Add RISC-V
` [PATCH v2 10/12] tests/qtest/bios-tables-test: Add empty ACPI data files for RISC-V
` [PATCH v2 11/12] tests/qtest/bios-tables-test.c: Enable basic testing "
` [PATCH v2 12/12] tests/qtest/bios-tables-test: Add expected ACPI data files "

[PATCH v2 0/6] target/riscv: Add support for Control Transfer Records Ext
 2024-06-19 15:27 UTC  (7+ messages)
` [PATCH v2 1/6] target/riscv: Remove obsolete sfence.vm instruction
` [PATCH v2 2/6] target/riscv: Add Control Transfer Records CSR definitions
` [PATCH v2 3/6] target/riscv: Add support for Control Transfer Records extension CSRs
` [PATCH v2 4/6] target/riscv: Add support to record CTR entries
` [PATCH v2 5/6] target/riscv: Add CTR sctrclr instruction
` [PATCH v2 6/6] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs

[PATCH v3 00/13] riscv: QEMU RISC-V IOMMU Support
 2024-06-18 15:15 UTC  (31+ messages)
` [PATCH v3 02/13] hw/riscv: add riscv-iommu-bits.h
` [PATCH v3 03/13] hw/riscv: add RISC-V IOMMU base emulation
` [PATCH v3 05/13] hw/riscv: add riscv-iommu-pci reference device
` [PATCH v3 08/13] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
` [PATCH v3 09/13] hw/riscv/riscv-iommu: add s-stage and g-stage support
` [PATCH v3 10/13] hw/riscv/riscv-iommu: add ATS support
` [PATCH v3 11/13] hw/riscv/riscv-iommu: add DBG support

[PATCH v3 0/3] hw/dma: Add error handling for loading descriptions failing
 2024-06-18 10:54 UTC  (5+ messages)
` [PATCH v3 1/3] hw/dma: Enhance error handling in loading description
` [PATCH v3 2/3] hw/dma: Add a trace log for a description loading failure
` [PATCH v3 3/3] hw/net: Fix the transmission return size

[RFC PATCH v2 0/2] Support RISC-V CSR read/write in Qtest environment
 2024-06-18  7:47 UTC  (4+ messages)
` [RFC PATCH v2 1/2] Add RISC-V CSR qtest support
` [RFC PATCH v2 2/2] QTest example for RISC-V CSR register

[PATCH v3] hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs
 2024-06-17  9:36 UTC  (6+ messages)

Can I utilize the RISC-V vector extension with QEMU?
 2024-06-17 13:12 UTC  (2+ messages)

[PATCH v2 0/6] Introduce extension implied rules
 2024-06-16  2:46 UTC  (7+ messages)
` [PATCH v2 1/6] target/riscv: Introduce extension implied rules definition
` [PATCH v2 2/6] target/riscv: Introduce extension implied rule helpers
` [PATCH v2 3/6] target/riscv: Add MISA implied rules
` [PATCH v2 4/6] target/riscv: Add standard extension "
` [PATCH v2 5/6] target/riscv: Add Zc extension implied rule
` [PATCH v2 6/6] target/riscv: Remove extension auto-update check statements

[RFC PATCH 00/16] Implements RISC-V WorldGuard extension v0.4
 2024-06-14 13:28 UTC  (22+ messages)
` [RFC PATCH 01/16] accel/tcg: Store section pointer in CPUTLBEntryFull
` [RFC PATCH 02/16] accel/tcg: memory access from CPU will pass access_type to IOMMU
` [RFC PATCH 03/16] exec: Add RISC-V WorldGuard WID to MemTxAttrs
` [RFC PATCH 04/16] hw/misc: riscv_worldguard: Add RISC-V WorldGuard global config
` [RFC PATCH 05/16] target/riscv: Add CPU options of WorldGuard CPU extension
` [RFC PATCH 06/16] target/riscv: Add hard-coded CPU state of WG extension
` [RFC PATCH 07/16] target/riscv: Add defines for WorldGuard CSRs
` [RFC PATCH 08/16] target/riscv: Allow global WG config to set WG CPU callbacks
` [RFC PATCH 09/16] target/riscv: Implement WorldGuard CSRs
` [RFC PATCH 10/16] target/riscv: Add WID to MemTxAttrs of CPU memory transactions
` [RFC PATCH 11/16] hw/misc: riscv_worldguard: Add API to enable WG extension of CPU
` [RFC PATCH 12/16] hw/misc: riscv_wgchecker: Implement RISC-V WorldGuard Checker
` [RFC PATCH 13/16] hw/misc: riscv_wgchecker: Implement wgchecker slot registers
` [RFC PATCH 14/16] hw/misc: riscv_wgchecker: Implement correct block-access behavior
` [RFC PATCH 15/16] hw/misc: riscv_wgchecker: Check the slot settings in translate
` [RFC PATCH 16/16] hw/riscv: virt: Add WorldGuard support

[RFC PATCH v3 0/5] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions
 2024-06-13 15:42 UTC  (7+ messages)
` [RFC PATCH v3 1/5] accel/tcg: Avoid unnecessary call overhead from qemu_plugin_vcpu_mem_cb
` [RFC PATCH v3 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store
` [RFC PATCH v3 3/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride whole register load/store
` [RFC PATCH v3 4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions
` [RFC PATCH v3 5/5] target/riscv: Inline unit-stride ld/st and corresponding functions for performance

[RFC PATCH 0/2] Support RISC-V CSR read/write in Qtest environment
 2024-06-13 10:14 UTC  (4+ messages)
` [PATCH 1/2] Add RISC-V CSR qtest support
` [PATCH 2/2] QTest example for RISC-V CSR register

[PATCH 0/6] target/riscv: Add support for Control Transfer Records Ext
 2024-06-12  3:13 UTC  (17+ messages)
` [PATCH 1/6] target/riscv: Remove obsolete sfence.vm instruction
` [PATCH 3/6] target/riscv: Add support for Control Transfer Records extension CSRs
` [PATCH 5/6] target/riscv: Add CTR sctrclr instruction

qemu-riscv32 usermode still broken?
 2024-06-12  1:26 UTC  (7+ messages)

[PATCH RESEND 0/6] Introduce extension implied rules
 2024-06-12  1:21 UTC  (13+ messages)
` [PATCH RESEND 1/6] target/riscv: Introduce extension implied rules definition
` [PATCH RESEND 2/6] target/riscv: Introduce extension implied rule helpers
` [PATCH RESEND 3/6] target/riscv: Add MISA implied rules
` [PATCH RESEND 4/6] target/riscv: Add standard extension "
` [PATCH RESEND 5/6] target/riscv: Add Zc extension implied rule
` [PATCH RESEND 6/6] target/riscv: Remove extension auto-update check statements

[PATCH v3 0/5] semihosting: Restrict to TCG
 2024-06-11 10:07 UTC  (9+ messages)
` [PATCH v3 1/5] target/m68k: Restrict semihosting "
` [PATCH v3 2/5] target/xtensa: "
` [PATCH v3 3/5] target/mips: "
` [PATCH v3 4/5] target/riscv: "
` [PATCH v3 5/5] semihosting: Restrict "

[PATCH] target/riscv: Fix froundnx.h nanbox check
 2024-06-08 21:45 UTC 

[PATCH] target/riscv: support atomic instruction fetch (Ziccif)
 2024-06-07 13:39 UTC  (2+ messages)

[PATCH v4 0/6] target/riscv: Support RISC-V privilege 1.13 spec
 2024-06-07  5:04 UTC  (9+ messages)
` [PATCH v4 1/6] target/riscv: Reuse the conversion function of priv_spec
` [PATCH v4 2/6] target/riscv: Define macros and variables for ss1p13
` [PATCH v4 3/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0
` [PATCH v4 4/6] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
` [PATCH v4 5/6] target/riscv: Reserve exception codes for sw-check and hw-err
` [PATCH v4 6/6] target/riscv: Support the version for ss1p13

[PATCH v3 0/6] target/riscv: Support RISC-V privilege 1.13 spec
 2024-06-06 13:43 UTC  (8+ messages)
` [PATCH v3 2/6] target/riscv: Define macros and variables for ss1p13
` [PATCH v3 3/6] target/riscv: Support the version "
` [PATCH v3 4/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0

[PATCH 0/3] RISC-V: ACPI: Namespace updates
 2024-06-06  9:49 UTC  (7+ messages)
` [PATCH 1/3] gpex-acpi: Support PCI link devices outside the host bridge
` [PATCH 3/3] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART

[PATCH v4 0/3] target/riscv/kvm: QEMU support for KVM Guest Debug on RISC-V
 2024-06-06  1:56 UTC  (5+ messages)
` [PATCH v4 1/3] target/riscv/kvm: add software breakpoints support
` [PATCH v4 2/3] target/riscv/kvm: handle the exit with debug reason
` [PATCH v4 3/3] target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG

[PATCH v3 0/3] target/riscv/kvm: QEMU support for KVM Guest Debug on RISC-V
 2024-06-05 23:51 UTC  (5+ messages)
` [PATCH v3 1/3] target/riscv/kvm: add software breakpoints support
` [PATCH v3 2/3] target/riscv/kvm: handle the exit with debug reason
` [PATCH v3 3/3] target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG

[PATCH RFC 0/8] Add Counter delegation ISA extension support
 2024-06-05 11:49 UTC  (5+ messages)
` [PATCH RFC 2/8] target/riscv: Decouple AIA processing from xiselect and xireg
` [PATCH RFC 4/8] target/riscv: Support generic CSR indirect access

[PATCH 0/6] Introduce extension implied rules
 2024-06-05  6:54 UTC  (4+ messages)
` [PATCH 2/6] target/riscv: Introduce extension implied rule helpers

[PATCH v2 0/8] hw/riscv/virt.c: aplic/imsic DT fixes
 2024-06-05  0:43 UTC  (10+ messages)
` [PATCH v2 5/8] hw/riscv/virt.c: aplic DT: rename prop to 'riscv, delegation'
` [PATCH v2 6/8] hw/riscv/virt.c: change imsic nodename to 'interrupt-controller'
` [PATCH v2 7/8] hw/riscv/virt.c: imsics DT: add 'qemu, imsics' to 'compatible'
` [PATCH v2 8/8] hw/riscv/virt.c: imsics DT: add '#msi-cells'


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