[PATCH 0/7] riscv: implement Ssqosid extension and CBQRI controllers
2025-11-25 11:55 UTC (27+ messages)
` [PATCH 1/7] riscv: implement Ssqosid extension and srmcfg CSR
` [PATCH 2/7] hw/riscv: define capabilities of CBQRI controllers
` [PATCH 3/7] hw/riscv: implement CBQRI capacity controller
` [PATCH 4/7] hw/riscv: implement CBQRI bandwidth controller
` [PATCH 5/7] hw/riscv: Kconfig: add CBQRI options
` [PATCH 6/7] hw/riscv: meson: add CBQRI controllers to the build
` [PATCH 7/7] hw/riscv: add CBQRI controllers to virt machine
[PATCH v4 0/5] hw/riscv: Experimental Server Platform Reference Board
2025-11-25 11:24 UTC (10+ messages)
` [PATCH v4 2/5] target/riscv: Add server platform reference cpu
` [PATCH v4 3/5] hw/riscv: experimental server platform reference machine
[PATCH-for-11.0 00/12] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data()
2025-11-25 11:06 UTC (18+ messages)
` [PATCH-for-11.0 01/12] target/hexagon: Use little-endian variant of cpu_ld/st_data*()
` [PATCH-for-11.0 02/12] target/tricore: "
` [PATCH-for-11.0 03/12] target/rx: "
` [PATCH-for-11.0 04/12] target/m68k: "
` [PATCH-for-11.0 05/12] target/s390x: "
` [PATCH-for-11.0 06/12] target/sparc: "
` [PATCH-for-11.0 07/12] target/i386: "
` [PATCH-for-11.0 08/12] target/hppa: "
` [PATCH-for-11.0 09/12] target/riscv: Use little-endian variant of cpu_ld/st_data*() for vector
` [PATCH-for-11.0 10/12] target/sh4: Replace cpu_stl_data() by explicit endianness variants
` [PATCH-for-11.0 11/12] target/mips: Use big-endian variant of cpu_ld/st_data*() for MSA
` [PATCH-for-11.0 12/12] accel/tcg: Remove non-explicit endian cpu_ld/st*_data*() helpers
[PATCH v2 00/15] Error message improvements
2025-11-25 10:28 UTC (32+ messages)
` [PATCH v2 01/15] error: Strip trailing '\n' from error string arguments (again)
` [PATCH v2 02/15] hw/usb: Convert to qemu_create() for a better error message
` [PATCH v2 03/15] ui: Convert to qemu_create() for simplicity and consistency
` [PATCH v2 04/15] tap-solaris: Use error_setg_file_open() for better error messages
` [PATCH v2 05/15] qga: "
` [PATCH v2 06/15] hw/scsi: Use error_setg_file_open() for a better error message
` [PATCH v2 07/15] hw/virtio: "
` [PATCH v2 08/15] net/tap: "
` [PATCH v2 09/15] blkdebug: "
` [PATCH v2 10/15] error: Use error_setg_file_open() for simplicity and consistency
` [PATCH v2 11/15] net/slirp: Improve file open error message
` [PATCH v2 12/15] error: Use error_setg_errno() to improve error messages
` [PATCH v2 13/15] error: Use error_setg_errno() for simplicity and consistency
` [PATCH v2 14/15] qga/commands-win32: Use error_setg_win32() for better error messages
` [PATCH v2 15/15] block/file-win32: Improve an error message
[PATCH v4 5/5] docs: add rvsp-ref.rst
2025-11-24 2:06 UTC (2+ messages)
[PATCH v4 1/5] target/riscv/cpu.c: remove 'bare' condition for .profile
2025-11-24 2:02 UTC (2+ messages)
[PATCH v3 00/18] Implements RISC-V WorldGuard extension v0.4
2025-11-23 17:52 UTC (5+ messages)
` [PATCH v3 05/18] hw/misc: riscv_worldguard: Add RISC-V WorldGuard global config
` [PATCH v3 14/18] hw/misc: riscv_wgchecker: Implement RISC-V WorldGuard Checker
[PATCH 00/14] Error message improvements
2025-11-22 13:58 UTC (34+ messages)
` [PATCH 01/14] error: Strip trailing '\n' from error string arguments (again)
` [PATCH 02/14] hw/usb: Use error_setg_file_open() for a better error message
` [PATCH 03/14] tap-solaris: Use error_setg_file_open() for better error messages
` [PATCH 04/14] qga: "
` [PATCH 05/14] hw/scsi: Use error_setg_file_open() for a better error message
` [PATCH 06/14] hw/virtio: "
` [PATCH 07/14] net/tap: "
` [PATCH 08/14] blkdebug: "
` [PATCH 09/14] error: Use error_setg_file_open() for simplicity and consistency
` [PATCH 10/14] net/slirp: Improve file open error message
` [PATCH 11/14] error: Use error_setg_errno() to improve error messages
` [PATCH 12/14] error: Use error_setg_errno() for simplicity and consistency
` [PATCH 13/14] qga/commands-win32: Use error_setg_win32() for better error messages
` [PATCH 14/14] block/file-win32: Improve an error message
[PATCH v1] target/riscv:Add support for RV64 Sifive U74 CPU
2025-11-21 9:08 UTC
[PATCH 0/9] RISC-V CPU time source interface
2025-11-21 8:24 UTC (8+ messages)
` [PATCH 8/9] target/riscv: RISCVCPUTimeSrcIf: add register_time_change_notifier
` [PATCH 9/9] hw/intc/riscv_aclint: implement the register_time_change_notifier method
[PATCH v2] Add RISCV Zilsd extension
2025-11-21 7:41 UTC (4+ messages)
[PATCH 0/3] Fix Zjpm implementation
2025-11-21 5:07 UTC (9+ messages)
` [PATCH 1/3] target/riscv: fix address masking
` [PATCH 2/3] target/riscv: Fix pointer masking PMM field selection logic
` [PATCH 3/3] target/riscv: Rename riscv_pm_get_virt_pmm() to riscv_pm_get_vm_ldst_pmm()
[PATCH v2 0/6] Fix Zjpm implementation
2025-11-21 5:04 UTC (7+ messages)
` [PATCH v2 1/6] target/riscv: fix address masking
` [PATCH v2 2/6] target/riscv: Add a helper to return the current effective priv mode
` [PATCH v2 3/6] target/riscv: Fix pointer masking PMM field selection logic
` [PATCH v2 4/6] target/riscv: Fix pointer masking for virtual-machine load/store insns
` [PATCH v2 5/6] target/riscv: Rename riscv_pm_get_virt_pmm() to riscv_pm_get_vm_ldst_pmm()
` [PATCH v2 6/6] target/riscv: Fix pointer masking translation mode check bug
[PATCH 0/5] A bit of cleanup around Error
2025-11-20 19:12 UTC (29+ messages)
` [PATCH 1/5] hw/core/loader: Make load_elf_hdr() return bool, simplify caller
` [PATCH 2/5] hw/nvram/xlnx-bbram: More idiomatic and simpler error reporting
` [PATCH 3/5] nbd/client-connection: Replace error_propagate() by assignment
` [PATCH 4/5] error: error_free(NULL) is safe, drop unnecessary conditionals
` [PATCH 5/5] error: Consistently name Error * objects err, and not errp
[PATCH v2 00/17] hw/riscv, target/riscv: initial e-trace support
2025-11-20 18:03 UTC (6+ messages)
` [PATCH v2 01/17] hw/riscv: Trace Encoder initial impl
` [PATCH v2 02/17] hw/riscv: Trace RAM Sink "
[PATCH v1] target/riscv: add support for RV64 THEAD C910 CPU
2025-11-20 12:21 UTC (2+ messages)
[PATCH v5] Add RISCV ZALASR extension
2025-11-19 1:04 UTC (2+ messages)
[PATCH 00/13] target/riscv: Centralize MO_TE uses in a pair of helpers
2025-11-18 20:17 UTC (4+ messages)
` [PATCH 01/13] target/riscv: Really use little endianness for 128-bit loads/stores
[PATCH v14 00/14] riscv: Add support for MIPS P8700 CPU
2025-11-18 11:19 UTC (16+ messages)
` [PATCH v14 01/14] hw/intc: Allow gaps in hartids for aclint and aplic
` [PATCH v14 03/14] target/riscv: Add MIPS P8700 CPU
` [PATCH v14 02/14] target/riscv: Add cpu_set_exception_base
` [PATCH v14 06/14] target/riscv: Add mips.pref instruction
` [PATCH v14 04/14] target/riscv: Add MIPS P8700 CSRs
` [PATCH v14 05/14] target/riscv: Add mips.ccmov instruction
` [PATCH v14 08/14] hw/misc: Add RISC-V CMGCR device implementation
` [PATCH v14 07/14] target/riscv: Add Xmipslsp instructions
` [PATCH v14 09/14] hw/misc: Add RISC-V CPC device implementation
` [PATCH v14 10/14] hw/riscv: Add support for RISCV CPS
` [PATCH v14 11/14] hw/riscv: Add support for MIPS Boston-aia board mode
` [PATCH v14 12/14] riscv/boston-aia: Add an e1000e NIC in slot 0 func 1
` [PATCH v14 13/14] test/functional: Add test for boston-aia board
` [PATCH v14 14/14] scripts/checkpatch: Check DEVICE_NATIVE_ENDIAN
[PATCH 0/2] Set MISA.[C|X] based on the selected extensions
2025-11-17 13:53 UTC (5+ messages)
` [PATCH 1/2] target/riscv: Update MISA.C for Zc* extensions
` [PATCH 2/2] target/riscv: Update MISA.X for non-standard extensions
[PATCH v4 RESEND 2/2] tests/acpi: Add acpi ged and power button in DSDT for RISC-V
2025-11-17 12:54 UTC (2+ messages)
[PATCH v4 RESEND 1/2] hw/riscv/virt: Add acpi ged and powerdown support
2025-11-17 10:01 UTC (2+ messages)
[PATCH v2 0/5] RISC-V: NEORV32 CPU, devices, and machine
2025-11-14 13:24 UTC (7+ messages)
` [PATCH v2 4/5] hw/ssi: add NEORV32 SPI controller (SSI master, CS command)
` [PATCH v2 5/5] hw/riscv: introduce 'neorv32' board, docs, and riscv32 device config
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