[PATCH 00/20] testing/next: functional tests and qtest timers
2024-12-10 20:43 UTC (21+ messages)
` [PATCH 01/20] tests/functional: update the arm tuxrun tests
` [PATCH 02/20] tests/functional: update the i386 "
` [PATCH 03/20] tests/functional: add a m68k "
` [PATCH 04/20] tests/functional: update the mips32 "
` [PATCH 05/20] tests/functional: update the mips32el "
` [PATCH 06/20] tests/functional: update the mips64 "
` [PATCH 07/20] tests/functional: update the mips64el "
` [PATCH 08/20] tests/functional: update the ppc32 "
` [PATCH 09/20] tests/functional: update the ppc64 "
` [PATCH 10/20] tests/functional: update the riscv32 "
` [PATCH 11/20] tests/functional: update the riscv64 "
` [PATCH 12/20] tests/functional: update the s390x "
` [PATCH 13/20] tests/functional: update the sparc64 "
` [PATCH 14/20] tests/functional: update the x86_64 "
` [PATCH 15/20] tests/functional/aarch64: add tests for FEAT_RME
` [PATCH 16/20] util/qemu-timer: fix indentation
` [PATCH 17/20] tests/qtest: move clock_steps to after checks
` [PATCH 18/20] system/qtest: properly feedback results of clock_[step|set]
` [PATCH 19/20] tests/functional: remove hacky sleep from the tests
` [PATCH 20/20] tests/functional: extend test_aarch64_virt with vulkan test
[PATCH 00/20] target: Implement CPUClass::datapath_is_big_endian() handlers
2024-12-09 20:21 UTC (26+ messages)
` [PATCH 01/20] exec/tswap: Rename target_words_bigendian -> qemu_binary_is_bigendian
` [PATCH 02/20] hw/core/cpu: Introduce CPUClass::datapath_is_big_endian() handler
` [PATCH 03/20] target/arm: Implement CPUClass::datapath_is_big_endian
` [PATCH 04/20] target/ppc: Register CPUClass::datapath_is_big_endian
` [PATCH 05/20] target/rx: Implement CPUClass::datapath_is_big_endian
` [PATCH 06/20] target/sparc: "
` [PATCH 07/20] target/riscv: "
` [PATCH 08/20] target/sh4: Expose CPUSH4State::little_endian property
` [PATCH 09/20] target/sh4: Implement CPUClass::datapath_is_big_endian
` [PATCH 10/20] target/microblaze: "
` [PATCH 11/20] target/mips: "
` [PATCH 12/20] target/xtensa: Implement xtensa_isa_is_big_endian()
` [PATCH 13/20] target/xtensa: Implement CPUClass::datapath_is_big_endian
` [PATCH 14/20] target: Implement CPUClass::datapath_is_big_endian (little-endian)
` [PATCH 15/20] target: Implement CPUClass::datapath_is_big_endian (big-endian)
` [PATCH 16/20] hw/core/cpu: Expose cpu_datapath_is_big_endian() method
` [PATCH 17/20] disas: Use cpu_datapath_is_big_endian()
` [PATCH 18/20] hw/core/generic-loader: "
` [RFC PATCH 19/20] hw/virtio: "
` [PATCH 20/20] hw/core/cpu: Remove cpu_virtio_is_big_endian()
[RFC v2 0/2] Add RISC-V Server Platform Reference Board
2024-12-09 20:20 UTC (2+ messages)
[PATCH v6 0/9] target/riscv: Add support for Smdbltrp and Ssdbltrp extensions
2024-12-09 19:36 UTC (5+ messages)
` [PATCH v6 1/9] target/riscv: fix henvcfg potentially containing stale bits
` [PATCH v6 2/9] target/riscv: Add Ssdbltrp CSRs handling
[PATCH v13 00/15] macOS PV Graphics and new vmapple machine type
2024-12-08 20:22 UTC (16+ messages)
` [PATCH v13 01/15] ui & main loop: Redesign of system-specific main thread event handling
` [PATCH v13 02/15] hw/display/apple-gfx: Introduce ParavirtualizedGraphics.Framework support
` [PATCH v13 03/15] hw/display/apple-gfx: Adds PCI implementation
` [PATCH v13 04/15] hw/display/apple-gfx: Adds configurable mode list
` [PATCH v13 05/15] MAINTAINERS: Add myself as maintainer for apple-gfx, reviewer for HVF
` [PATCH v13 06/15] hw: Add vmapple subdir
` [PATCH v13 07/15] hw/misc/pvpanic: Add MMIO interface
` [PATCH v13 08/15] hvf: arm: Ignore writes to CNTP_CTL_EL0
` [PATCH v13 09/15] gpex: Allow more than 4 legacy IRQs
` [PATCH v13 10/15] hw/vmapple/aes: Introduce aes engine
` [PATCH v13 11/15] hw/vmapple/bdif: Introduce vmapple backdoor interface
` [PATCH v13 12/15] hw/vmapple/cfg: Introduce vmapple cfg region
` [PATCH v13 13/15] hw/vmapple/virtio-blk: Add support for apple virtio-blk
` [PATCH v13 14/15] hw/block/virtio-blk: Replaces request free function with g_free
` [PATCH v13 15/15] hw/vmapple/vmapple: Add vmapple machine type
[PATCH v12 0/7] Pointer Masking update for Zjpm v1.0
2024-12-07 7:20 UTC (11+ messages)
` [PATCH v12 1/7] target/riscv: Remove obsolete pointer masking extension code
` [PATCH v12 2/7] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0
` [PATCH v12 3/7] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking
` [PATCH v12 4/7] target/riscv: Add pointer masking tb flags
` [PATCH v12 5/7] target/riscv: Update address modify functions to take into account pointer masking
` [PATCH v12 6/7] target/riscv: Apply pointer masking for virtualized memory accesses
` [PATCH v12 7/7] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension
[PATCH 1/1] disas/riscv: Guard dec->cfg dereference for host disassemble
2024-12-07 1:27 UTC (5+ messages)
Host riscv disas is broken
2024-12-06 3:39 UTC (6+ messages)
[PATCH v3] riscv/gdb: add V bit to priv register
2024-12-06 0:12 UTC
[PATCH-for-10.0 v2 00/13] hw/boards: Remove legacy MachineClass::pci_allow_0_address flag
2024-12-05 21:25 UTC (10+ messages)
` [PATCH-for-10.0 v2 01/13] hw/pci: Do not declare PCIBus::flags mask as enum
` [PATCH-for-10.0 v2 05/13] hw/pci: Propagate bar_at_addr_0_refused to pci_root_bus_internal_init()
` [PATCH-for-10.0 v2 10/13] hw/pci-host/gpex: Expose 'refuse-bar-at-addr-0' property
[PATCH] binfmt: Don't consider riscv{32,64} part of the same family
2024-12-05 17:15 UTC (7+ messages)
` [PATCH] binfmt: Don't consider riscv{32, 64} "
[PATCH for-10.0 00/11] riscv: IOMMU HPM support
2024-12-05 13:30 UTC (12+ messages)
` [PATCH for-10.0 01/11] hw/riscv/riscv-iommu.h: add missing headers
` [PATCH for-10.0 02/11] hw/riscv/riscv-iommu-bits.h: HPM bits
` [PATCH for-10.0 03/11] hw/riscv/riscv-iommu: add riscv-iommu-hpm file
` [PATCH for-10.0 04/11] hw/riscv/riscv-iommu: add riscv_iommu_hpm_incr_ctr()
` [PATCH for-10.0 05/11] hw/riscv/riscv-iommu: instantiate hpm_timer
` [PATCH for-10.0 06/11] hw/riscv/riscv-iommu: add IOCOUNTINH mmio writes
` [PATCH for-10.0 07/11] hw/riscv/riscv-iommu: add IOHPMCYCLES mmio write
` [PATCH for-10.0 08/11] hw/riscv/riscv-iommu: add hpm events "
` [PATCH for-10.0 09/11] hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM cap
` [PATCH for-10.0 10/11] hw/riscv: add IOMMU HPM trace events
` [PATCH for-10.0 11/11] docs/specs/riscv-iommu.rst: add HPM support info
[PATCH v1] target/riscv: add support for RV64 Xiangshan Nanhu CPU
2024-12-05 12:14 UTC (2+ messages)
[PATCH v4 0/7] target/riscv: Add support for Control Transfer Records Ext
2024-12-05 11:36 UTC (10+ messages)
` [PATCH v4 1/7] target/riscv: Remove obsolete sfence.vm instruction
` [PATCH v4 2/7] target/riscv: Add Control Transfer Records CSR definitions
` [PATCH v4 3/7] target/riscv: Add support for Control Transfer Records extension CSRs
` [PATCH v4 4/7] target/riscv: Add support to record CTR entries
` [PATCH v4 5/7] target/riscv: Add CTR sctrclr instruction
` [PATCH v4 6/7] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs
` [PATCH v4 7/7] target/riscv: machine: Add Control Transfer Record state description
[PATCH v5 0/7] target/riscv: Add support for Control Transfer Records Ext
2024-12-05 11:34 UTC (8+ messages)
` [PATCH v5 1/7] target/riscv: Remove obsolete sfence.vm instruction
` [PATCH v5 2/7] target/riscv: Add Control Transfer Records CSR definitions
` [PATCH v5 3/7] target/riscv: Add support for Control Transfer Records extension CSRs
` [PATCH v5 4/7] target/riscv: Add support to record CTR entries
` [PATCH v5 5/7] target/riscv: Add CTR sctrclr instruction
` [PATCH v5 6/7] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs
` [PATCH v5 7/7] target/riscv: machine: Add Control Transfer Record state description
[PATCH v2] riscv/gdb: add virt mode debug interface
2024-12-05 9:15 UTC (9+ messages)
[PATCH v6 0/1] target/riscv: rvv: reduce the overhead for simple RISC-V vector unit-stride loads and stores
2024-12-04 13:44 UTC (3+ messages)
` [PATCH v6 1/1] "
[PATCH v3 0/6] target/riscv: Add support for Control Transfer Records Ext
2024-12-04 12:59 UTC (3+ messages)
[PATCH RESEND v1] target/riscv: add support for RV64 Xiangshan Nanhu CPU
2024-12-04 12:58 UTC (2+ messages)
[PATCH v4 00/11] Add RISC-V Counter delegation ISA extension support
2024-12-04 12:51 UTC (14+ messages)
` [PATCH v4 01/11] target/riscv: Add properties for Indirect CSR Access extension
` [PATCH v4 02/11] target/riscv: Decouple AIA processing from xiselect and xireg
` [PATCH v4 03/11] target/riscv: Enable S*stateen bits for AIA
` [PATCH v4 04/11] target/riscv: Support generic CSR indirect access
` [PATCH v4 05/11] target/riscv: Add properties for counter delegation ISA extensions
` [PATCH v4 06/11] target/riscv: Add counter delegation definitions
` [PATCH v4 07/11] target/riscv: Add select value range check for counter delegation
` [PATCH v4 08/11] target/riscv: Add counter delegation/configuration support
` [PATCH v4 09/11] target/riscv: Invoke pmu init after feature enable
` [PATCH v4 10/11] target/riscv: Add implied rule for counter delegation extensions
` [PATCH v4 11/11] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg
[PATCH for-10.0 0/9] target/riscv: add 'sha' support
2024-12-04 4:42 UTC (19+ messages)
` [PATCH for-10.0 2/9] target/riscv: add ssstateen
` [PATCH for-10.0 3/9] target/riscv: add shcounterenw
` [PATCH for-10.0 4/9] target/riscv: add shvstvala
` [PATCH for-10.0 5/9] target/riscv: add shtvala
` [PATCH for-10.0 6/9] target/riscv: add shvstvecd
` [PATCH for-10.0 7/9] target/riscv: add shvsatpa
` [PATCH for-10.0 8/9] target/riscv: add shgatpa
` [PATCH for-10.0 9/9] target/riscv/tcg: add sha
[PATCH v1] Add a CPU entry for the RV64 XiangShan NANHU CPU which supports single-core and dual-core configurations. More details can be found at https://docs.xiangshan.cc/zh-cn/latest/integration/overview
2024-12-04 2:53 UTC
[PATCH 0/2] target/riscv: Include missing headers in '*internals.h'
2024-12-04 2:41 UTC (8+ messages)
` [PATCH 1/2] target/riscv: Include missing headers in 'vector_internals.h'
` [PATCH 2/2] target/riscv: Include missing headers in 'internals.h'
[PATCH v5 0/6] Introduce svukte ISA extension
2024-12-04 2:36 UTC (9+ messages)
` [PATCH v5 1/6] target/riscv: Add svukte extension capability variable
` [PATCH v5 2/6] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled
` [PATCH v5 3/6] target/riscv: Support hstatus[HUKTE] "
` [PATCH v5 4/6] target/riscv: Check memory access to meet svukte rule
` [PATCH v5 5/6] target/riscv: Expose svukte ISA extension
` [PATCH v5 6/6] target/riscv: Check svukte is not enabled in RV32
[PATCH for-9.2] target/riscv: Avoid bad shift in riscv_cpu_do_interrupt()
2024-12-03 8:40 UTC (4+ messages)
[PATCH v4 0/3] Support 64-bit address of initrd
2024-12-03 6:47 UTC (8+ messages)
` [PATCH v4 1/3] hw/riscv: Support to load DTB after 3GB memory on 64-bit system
` [PATCH v4 2/3] hw/riscv: Add a new struct RISCVBootInfo
` [PATCH v4 3/3] hw/riscv: Add the checking if DTB overlaps to kernel or initrd
[PATCH-for-10.0 0/3] hw/char/riscv_htif: Remove tswap64() calls
2024-12-03 6:35 UTC (8+ messages)
` [PATCH-for-10.0 1/3] MAINTAINERS: Cover RISC-V HTIF interface
` [PATCH-for-10.0 2/3] hw/char/riscv_htif: Explicit little-endian implementation
` [PATCH-for-10.0 3/3] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses
[PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format
2024-12-03 6:34 UTC (3+ messages)
[RFC PATCH v3 09/11] target/riscv: call plugin trap callbacks
2024-12-03 4:39 UTC (2+ messages)
[PATCH v3 00/11] Add RISC-V Counter delegation ISA extension support
2024-12-02 23:47 UTC (9+ messages)
` [PATCH v3 04/11] target/riscv: Support generic CSR indirect access
` [PATCH v3 08/11] target/riscv: Add counter delegation/configuration support
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