From: Gia <giacomo.gio@gmail.com>
To: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: "Benjamin Böhmke" <benjamin@boehmke.net>,
"Mario Limonciello" <mario.limonciello@amd.com>,
"Christian Heusel" <christian@heusel.eu>,
"Linux regressions mailing list" <regressions@lists.linux.dev>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"stable@vger.kernel.org" <stable@vger.kernel.org>,
"kernel@micha.zone" <kernel@micha.zone>,
"Andreas Noever" <andreas.noever@gmail.com>,
"Michael Jamet" <michael.jamet@intel.com>,
"Yehezkel Bernat" <YehezkelShB@gmail.com>,
"linux-usb@vger.kernel.org" <linux-usb@vger.kernel.org>,
"S, Sanath" <Sanath.S@amd.com>
Subject: Re: [REGRESSION][BISECTED] "xHCI host controller not responding, assume dead" on stable kernel > 6.8.7
Date: Tue, 21 May 2024 10:15:28 +0200 [thread overview]
Message-ID: <CAHe5sWb7kHurBvu6JC6OgXZm9mSg5a2W2XK9L8gCygYaFZz7JQ@mail.gmail.com> (raw)
In-Reply-To: <20240521051151.GK1421138@black.fi.intel.com>
Here you go:
0x0080 0x003c01c0 0b00000000 00111100 00000001 11000000 .... LANE_ADP_CS_0
[00:07] 0xc0 Next Capability Pointer
[08:15] 0x1 Capability ID
[16:19] 0xc Supported Link Speeds
[20:21] 0x3 Supported Link Widths (SLW)
[22:23] 0x0 Gen 4 Asymmetric Support (G4AS)
[26:26] 0x0 CL0s Support
[27:27] 0x0 CL1 Support
[28:28] 0x0 CL2 Support
0x0081 0x0828003c 0b00001000 00101000 00000000 00111100 .... LANE_ADP_CS_1
[00:03] 0xc Target Link Speed → Router shall attempt Gen 3 speed
[04:05] 0x3 Target Link Width → Establish a Symmetric Link
[06:07] 0x0 Target Asymmetric Link → Establish Symmetric Link
[10:10] 0x0 CL0s Enable
[11:11] 0x0 CL1 Enable
[12:12] 0x0 CL2 Enable
[14:14] 0x0 Lane Disable (LD)
[15:15] 0x0 Lane Bonding (LB)
[16:19] 0x8 Current Link Speed → Gen 2
[20:25] 0x2 Negotiated Link Width → Symmetric Link (x2)
[26:29] 0x2 Adapter State → CL0
[30:30] 0x0 PM Secondary (PMS)
On Tue, May 21, 2024 at 7:11 AM Mika Westerberg
<mika.westerberg@linux.intel.com> wrote:
>
> Hi,
>
> On Mon, May 20, 2024 at 07:30:28PM +0200, Gia wrote:
> > In my case I use the official Thunderbolt cable that came with my
> > CalDigit TS3 Plus and yet the log - attached in a previous email -
> > says current link speed 10.0 Gb/s. I just tried a good quality USB4
> > cable too and nothing changed.
>
> I will take a look at your logs today but in the meantime can you run
> following command on the system with the dock connected?
>
> # tbdump -r 0 -a 1 -vv -N 2 LANE_ADP_CS_0
>
> Here tbdump comes from https://github.com/intel/tbtools. It should be
> pretty straighforward to build but let me know if any issues
> (unfortunately there is no binary package available at this time).
>
> The '-a 1' should match the adapter the dock is connected. You can get
> it for instance like this (this is an example from my system):
>
> # tblist
> Domain 0 Route 0: 8087:7eb2 Intel Gen14
> Domain 0 Route 1: 003d:0011 CalDigit, Inc. TS3 Plus
> Domain 1 Route 0: 8087:7eb2 Intel Gen14
>
> Here the CalDigit has "Route 1" so it means I use "-a 1" above. It could
> be also "Domain 0 Route 3" in which case replace the "-a 1" with "-a 3".
>
> This command should dump two lane adapter registers LANE_ADP_CS_0/1 that
> show the link capabilities.
next prev parent reply other threads:[~2024-05-21 8:15 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CAHe5sWavQcUTg2zTYaryRsMywSBgBgETG=R1jRexg4qDqwCfdw@mail.gmail.com>
2024-05-06 12:53 ` [REGRESSION] Thunderbolt Host Reset Change Causes eGPU Disconnection from 6.8.7=>6.8.8 Linux regression tracking (Thorsten Leemhuis)
2024-05-20 9:19 ` Gia
2024-05-20 13:43 ` Mario Limonciello
2024-05-20 14:39 ` [REGRESSION][BISECTED] "xHCI host controller not responding, assume dead" on stable kernel > 6.8.7 Christian Heusel
2024-05-20 14:41 ` Mario Limonciello
2024-05-20 15:12 ` Benjamin Böhmke
2024-05-20 16:21 ` Mika Westerberg
2024-05-20 16:53 ` Benjamin Böhmke
2024-05-20 17:30 ` Gia
2024-05-21 5:11 ` Mika Westerberg
2024-05-21 8:15 ` Gia [this message]
2024-05-21 8:59 ` Mika Westerberg
2024-05-21 9:12 ` Gia
2024-05-21 11:26 ` Mika Westerberg
2024-05-22 14:41 ` Gia
2024-05-22 15:19 ` Mario Limonciello
2024-05-23 4:45 ` Mika Westerberg
2024-05-21 4:59 ` Mika Westerberg
2024-05-21 10:52 ` Limonciello, Mario
2024-05-20 15:57 ` Gia
2024-05-21 5:15 ` Mika Westerberg
2024-05-21 8:07 ` Gia
2024-05-21 8:55 ` Mika Westerberg
2024-05-21 9:24 ` Gia
2024-05-21 11:29 ` Mika Westerberg
2024-05-21 10:50 ` Limonciello, Mario
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