From: p.fedin@samsung.com (Pavel Fedin)
To: linux-arm-kernel@lists.infradead.org
Subject: IRQFD support with GICv3 ITS (WAS: RE: [PATCH 00/13] arm64: KVM: GICv3 ITS emulation)
Date: Wed, 10 Jun 2015 18:38:44 +0300 [thread overview]
Message-ID: <05db01d0a393$895bf710$9c13e530$@samsung.com> (raw)
In-Reply-To: <557842A0.9070503@linaro.org>
Hello!
> KVM GSI routing, even if only used for MSI routing then mandates to
> build entries for non MSI IRQs, using irqchip routing entries. Then you
> draw the irqchip.c kvm_irq_routing_table
> chip[KVM_NR_IRQCHIPS][KVM_IRQCHIP_NUM_PINS] static allocation issue.
Sorry for this add-on, needed time to look at the code.
Actually, if we don't use this code at all, and implement our own kvm_set_irq_routing()
and kvm_free_irq_routing(), we don't have to bother about all these limitations.
The simplest thing to do there would be to store GSI number in struct its_itte. In this
case raising an MSI by GSI would not differ from what i currently do.
Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia
WARNING: multiple messages have this Message-ID (diff)
From: Pavel Fedin <p.fedin@samsung.com>
To: 'Eric Auger' <eric.auger@linaro.org>,
'Marc Zyngier' <marc.zyngier@arm.com>,
'Andre Przywara' <Andre.Przywara@arm.com>,
christoffer.dall@linaro.org
Cc: kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org
Subject: RE: IRQFD support with GICv3 ITS (WAS: RE: [PATCH 00/13] arm64: KVM: GICv3 ITS emulation)
Date: Wed, 10 Jun 2015 18:38:44 +0300 [thread overview]
Message-ID: <05db01d0a393$895bf710$9c13e530$@samsung.com> (raw)
In-Reply-To: <557842A0.9070503@linaro.org>
Hello!
> KVM GSI routing, even if only used for MSI routing then mandates to
> build entries for non MSI IRQs, using irqchip routing entries. Then you
> draw the irqchip.c kvm_irq_routing_table
> chip[KVM_NR_IRQCHIPS][KVM_IRQCHIP_NUM_PINS] static allocation issue.
Sorry for this add-on, needed time to look at the code.
Actually, if we don't use this code at all, and implement our own kvm_set_irq_routing()
and kvm_free_irq_routing(), we don't have to bother about all these limitations.
The simplest thing to do there would be to store GSI number in struct its_itte. In this
case raising an MSI by GSI would not differ from what i currently do.
Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia
next prev parent reply other threads:[~2015-06-10 15:38 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-10 8:31 IRQFD support with GICv3 ITS (WAS: RE: [PATCH 00/13] arm64: KVM: GICv3 ITS emulation) Pavel Fedin
2015-06-10 8:31 ` Pavel Fedin
2015-06-10 13:58 ` Eric Auger
2015-06-10 13:58 ` Eric Auger
2015-06-10 15:30 ` Pavel Fedin
2015-06-10 15:30 ` Pavel Fedin
2015-06-17 9:21 ` Pavel Fedin
2015-06-17 9:34 ` Marc Zyngier
2015-06-17 10:00 ` Pavel Fedin
2015-06-17 11:02 ` Andre Przywara
2015-06-17 11:46 ` Pavel Fedin
2015-06-18 6:35 ` Eric Auger
2015-06-18 14:19 ` Pavel Fedin
2015-06-10 15:38 ` Pavel Fedin [this message]
2015-06-10 15:38 ` Pavel Fedin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='05db01d0a393$895bf710$9c13e530$@samsung.com' \
--to=p.fedin@samsung.com \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.