From: Vineet Gupta <Vineet.Gupta1@synopsys.com> To: <linux-arch@vger.kernel.org>, <linux-kernel@vger.kernel.org> Cc: <arnd@arndb.de>, <arc-linux-dev@synopsys.com>, Vineet Gupta <Vineet.Gupta1@synopsys.com> Subject: [PATCH 08/28] ARCv2: MMUv4: support aliasing icache config Date: Tue, 9 Jun 2015 17:18:08 +0530 [thread overview] Message-ID: <1433850508-26317-9-git-send-email-vgupta@synopsys.com> (raw) In-Reply-To: <1433850508-26317-1-git-send-email-vgupta@synopsys.com> This is also default for AXS103 release Signed-off-by: Vineet Gupta <vgupta@synopsys.com> --- arch/arc/include/asm/cache.h | 4 +--- arch/arc/mm/cache.c | 14 +++++++++++++- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index e54977a7d006..d21c76d6b054 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -60,7 +60,7 @@ extern void read_decode_cache_bcr(void); #define ARC_REG_IC_IVIC 0x10 #define ARC_REG_IC_CTRL 0x11 #define ARC_REG_IC_IVIL 0x19 -#if defined(CONFIG_ARC_MMU_V3) +#if defined(CONFIG_ARC_MMU_V3) || defined(CONFIG_ARC_MMU_V4) #define ARC_REG_IC_PTAG 0x1E #endif @@ -74,9 +74,7 @@ extern void read_decode_cache_bcr(void); #define ARC_REG_DC_IVDL 0x4A #define ARC_REG_DC_FLSH 0x4B #define ARC_REG_DC_FLDL 0x4C -#if defined(CONFIG_ARC_MMU_V3) #define ARC_REG_DC_PTAG 0x5C -#endif /* Bit val in DC_CTRL */ #define DC_CTRL_INV_MODE_FLUSH 0x40 diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c index 7a898f57d84b..0eaaee60fd0b 100644 --- a/arch/arc/mm/cache.c +++ b/arch/arc/mm/cache.c @@ -21,6 +21,9 @@ #include <asm/cachectl.h> #include <asm/setup.h> +void (*_cache_line_loop_ic_fn)(unsigned long paddr, unsigned long vaddr, + unsigned long sz, const int cacheop); + char *arc_cache_mumbojumbo(int c, char *buf, int len) { int n = 0; @@ -414,7 +417,7 @@ __ic_line_inv_vaddr_local(unsigned long paddr, unsigned long vaddr, unsigned long flags; local_irq_save(flags); - __cache_line_loop(paddr, vaddr, sz, OP_INV_IC); + (*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC); local_irq_restore(flags); } @@ -746,6 +749,15 @@ void arc_cache_init(void) if (ic->ver != CONFIG_ARC_MMU_VER) panic("Cache ver [%d] doesn't match MMU ver [%d]\n", ic->ver, CONFIG_ARC_MMU_VER); + + /* + * In MMU v4 (HS38x) the alising icache config uses IVIL/PTAG + * pair to provide vaddr/paddr respectively, just as in MMU v3 + */ + if (is_isa_arcv2() && ic->alias) + _cache_line_loop_ic_fn = __cache_line_loop_v3; + else + _cache_line_loop_ic_fn = __cache_line_loop; } if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) { -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: Vineet Gupta <Vineet.Gupta1@synopsys.com> To: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org Cc: arnd@arndb.de, arc-linux-dev@synopsys.com, Vineet Gupta <Vineet.Gupta1@synopsys.com> Subject: [PATCH 08/28] ARCv2: MMUv4: support aliasing icache config Date: Tue, 9 Jun 2015 17:18:08 +0530 [thread overview] Message-ID: <1433850508-26317-9-git-send-email-vgupta@synopsys.com> (raw) In-Reply-To: <1433850508-26317-1-git-send-email-vgupta@synopsys.com> This is also default for AXS103 release Signed-off-by: Vineet Gupta <vgupta@synopsys.com> --- arch/arc/include/asm/cache.h | 4 +--- arch/arc/mm/cache.c | 14 +++++++++++++- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index e54977a7d006..d21c76d6b054 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -60,7 +60,7 @@ extern void read_decode_cache_bcr(void); #define ARC_REG_IC_IVIC 0x10 #define ARC_REG_IC_CTRL 0x11 #define ARC_REG_IC_IVIL 0x19 -#if defined(CONFIG_ARC_MMU_V3) +#if defined(CONFIG_ARC_MMU_V3) || defined(CONFIG_ARC_MMU_V4) #define ARC_REG_IC_PTAG 0x1E #endif @@ -74,9 +74,7 @@ extern void read_decode_cache_bcr(void); #define ARC_REG_DC_IVDL 0x4A #define ARC_REG_DC_FLSH 0x4B #define ARC_REG_DC_FLDL 0x4C -#if defined(CONFIG_ARC_MMU_V3) #define ARC_REG_DC_PTAG 0x5C -#endif /* Bit val in DC_CTRL */ #define DC_CTRL_INV_MODE_FLUSH 0x40 diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c index 7a898f57d84b..0eaaee60fd0b 100644 --- a/arch/arc/mm/cache.c +++ b/arch/arc/mm/cache.c @@ -21,6 +21,9 @@ #include <asm/cachectl.h> #include <asm/setup.h> +void (*_cache_line_loop_ic_fn)(unsigned long paddr, unsigned long vaddr, + unsigned long sz, const int cacheop); + char *arc_cache_mumbojumbo(int c, char *buf, int len) { int n = 0; @@ -414,7 +417,7 @@ __ic_line_inv_vaddr_local(unsigned long paddr, unsigned long vaddr, unsigned long flags; local_irq_save(flags); - __cache_line_loop(paddr, vaddr, sz, OP_INV_IC); + (*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC); local_irq_restore(flags); } @@ -746,6 +749,15 @@ void arc_cache_init(void) if (ic->ver != CONFIG_ARC_MMU_VER) panic("Cache ver [%d] doesn't match MMU ver [%d]\n", ic->ver, CONFIG_ARC_MMU_VER); + + /* + * In MMU v4 (HS38x) the alising icache config uses IVIL/PTAG + * pair to provide vaddr/paddr respectively, just as in MMU v3 + */ + if (is_isa_arcv2() && ic->alias) + _cache_line_loop_ic_fn = __cache_line_loop_v3; + else + _cache_line_loop_ic_fn = __cache_line_loop; } if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) { -- 1.9.1
next prev parent reply other threads:[~2015-06-09 11:50 UTC|newest] Thread overview: 109+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-06-09 11:48 [PATCH 00/28] ARCv2 port to Linux - (B) ISA / Core / platform support Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 01/28] ARCv2: [intc] HS38 core interrupt controller Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 02/28] ARCv2: Support for ARCv2 ISA and HS38x cores Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 03/28] ARCv2: STAR 9000793984: Handle return from intr to Delay Slot Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 04/28] ARCv2: STAR 9000808988: signals involving " Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 05/28] ARCv2: STAR 9000814690: Really Re-enable interrupts to avoid deadlocks Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 06/28] ARCv2: MMUv4: TLB programming Model changes Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 07/28] ARCv2: MMUv4: cache programming model changes Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta [this message] 2015-06-09 11:48 ` [PATCH 08/28] ARCv2: MMUv4: support aliasing icache config Vineet Gupta 2015-06-09 11:48 ` [PATCH 09/28] ARCv2: optimised string/mem lib routines Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 10/28] ARCv2: Adhere to Zero Delay loop restriction Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 11/28] ARCv2: extable: Enable sorting at build time Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-24 5:51 ` Vineet Gupta 2015-06-24 5:51 ` Vineet Gupta 2015-06-29 20:38 ` David Daney 2015-06-30 4:41 ` Vineet Gupta 2015-06-30 4:41 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 12/28] ARCv2: clocksource: Introduce 64bit local RTC counter Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 13/28] ARC: make plat_smp_ops weak to allow over-rides Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 14/28] ARCv2: SMP: ARConnect debug/robustness Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 15/28] ARCv2: SMP: clocksource: Enable Global Real Time counter Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 16/28] ARCv2: SMP: intc: IDU 2nd level intc for dynamic IRQ distribution Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 17/28] ARC: add compiler barrier to LLSC based cmpxchg Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 12:23 ` Peter Zijlstra 2015-06-09 11:48 ` [PATCH 18/28] ARC: add smp barriers around atomics per memory-barrriers.txt Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 12:30 ` Peter Zijlstra 2015-06-10 9:17 ` Vineet Gupta 2015-06-10 10:53 ` Peter Zijlstra 2015-06-11 13:03 ` Vineet Gupta 2015-06-12 12:15 ` [PATCH v2] ARC: add smp barriers around atomics per Documentation/atomic_ops.txt Vineet Gupta 2015-06-12 12:15 ` Vineet Gupta 2015-06-12 13:04 ` Peter Zijlstra 2015-06-12 13:16 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 19/28] arch: conditionally define smp_{mb,rmb,wmb} Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 12:32 ` Peter Zijlstra 2015-06-09 11:48 ` [PATCH 20/28] ARCv2: barriers Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 12:40 ` Peter Zijlstra 2015-06-10 9:34 ` Vineet Gupta 2015-06-10 10:58 ` Peter Zijlstra 2015-06-10 13:01 ` Will Deacon 2015-06-11 12:13 ` Vineet Gupta 2015-06-11 13:39 ` Will Deacon 2015-06-19 13:13 ` Vineet Gupta 2015-06-19 13:13 ` Vineet Gupta 2015-06-19 13:13 ` Vineet Gupta 2015-06-22 13:36 ` Will Deacon 2015-06-22 13:36 ` Will Deacon 2015-06-22 13:36 ` Will Deacon 2015-06-23 7:58 ` [PATCH v2 " Vineet Gupta 2015-06-23 7:58 ` Vineet Gupta 2015-06-23 8:49 ` Will Deacon 2015-06-23 9:03 ` Vineet Gupta 2015-06-23 9:26 ` Will Deacon 2015-06-23 9:52 ` [PATCH v3 22/28] " Vineet Gupta 2015-06-23 9:52 ` Vineet Gupta 2015-06-23 16:28 ` Will Deacon 2015-06-23 9:25 ` [PATCH v2 20/28] " Peter Zijlstra 2015-06-23 8:02 ` [PATCH " Vineet Gupta 2015-06-09 11:48 ` [PATCH 21/28] ARC: Reduce bitops lines of code using macros Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-12 12:20 ` [PATCH v2] " Vineet Gupta 2015-06-12 12:20 ` Vineet Gupta 2015-06-12 13:05 ` Peter Zijlstra 2015-06-09 11:48 ` [PATCH 22/28] ARCv2: STAR 9000837815 workaround hardware exclusive transactions livelock Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 12:35 ` Peter Zijlstra 2015-06-10 10:01 ` Vineet Gupta 2015-06-10 11:02 ` Peter Zijlstra 2015-06-19 9:55 ` [PATCH v2 " Vineet Gupta 2015-06-19 9:55 ` Vineet Gupta 2015-06-19 9:59 ` Will Deacon 2015-06-19 10:09 ` Vineet Gupta 2015-06-23 7:59 ` Vineet Gupta 2015-06-23 7:59 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 23/28] ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency) Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 24/28] ARCv2: All bits in place, allow ARCv2 builds Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 25/28] ARCv2: [nsim*hs*] Support simulation platforms for HS38x cores Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 26/28] ARC: [axs101] Prepare for AXS103 Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 27/28] ARCv2: [axs103] Support ARC SDP FPGA platform for HS38x cores Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta 2015-06-09 11:48 ` [PATCH 28/28] ARCv2: [vdk] dts files and defconfig for HS38 VDK Vineet Gupta 2015-06-09 11:48 ` Vineet Gupta
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