All the mail mirrored from lore.kernel.org
 help / color / mirror / Atom feed
From: thomas.petazzoni@free-electrons.com (Thomas Petazzoni)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 23/34] pinctrl: mvebu: armada-xp: rename spi to spi0
Date: Tue,  9 Jun 2015 18:47:15 +0200	[thread overview]
Message-ID: <1433868446-11028-24-git-send-email-thomas.petazzoni@free-electrons.com> (raw)
In-Reply-To: <1433868446-11028-1-git-send-email-thomas.petazzoni@free-electrons.com>

After updating to the latest Armada XP datasheet, we discovered that
there is a second SPI bus accessible from the MPP pins, called 'spi1'.

In order to be consistent with other SoCs having two SPI busses, this
commit renames the functions of the first SPI bus to 'spi0' instead of
just 'spi'.

This commit obviously breaks the DT backward compatibility for the
people using the "spi" function name in their Device Tree.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 22 +++++++++++-----------
 drivers/pinctrl/mvebu/pinctrl-armada-xp.c          | 22 +++++++++++-----------
 2 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
index f2d2d40..e8e0a27 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
@@ -54,20 +54,20 @@ mpp32         32       gpio, tdm(int3), sd0(d0)
 mpp33         33       gpio, tdm(int4), sd0(d1), dram(bat)
 mpp34         34       gpio, tdm(int5), sd0(d2), sata0(prsnt)
 mpp35         35       gpio, tdm(int6), sd0(d3), sata1(prsnt)
-mpp36         36       gpio, spi(mosi)
-mpp37         37       gpio, spi(miso)
-mpp38         38       gpio, spi(sck)
-mpp39         39       gpio, spi(cs0)
-mpp40         40       gpio, spi(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0)
-mpp41         41       gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
+mpp36         36       gpio, spi0(mosi)
+mpp37         37       gpio, spi0(miso)
+mpp38         38       gpio, spi0(sck)
+mpp39         39       gpio, spi0(cs0)
+mpp40         40       gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0)
+mpp41         41       gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
                        pcie(clkreq1)
 mpp42         42       gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer)
-mpp43         43       gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout)
-mpp44         44       gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
+mpp43         43       gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout)
+mpp44         44       gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2),
                        dram(bat)
-mpp45         45       gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
-mpp46         46       gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
-mpp47         47       gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
+mpp45         45       gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt)
+mpp46         46       gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt)
+mpp47         47       gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3),
                        ref(clkout)
 mpp48         48       gpio, dev(clkout), dev(burst/last)
 
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
index fb5ffa5..74ff211 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
@@ -224,25 +224,25 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
 		 MPP_VAR_FUNCTION(0x3, "tdm", "int6",       V_MV78230_PLUS)),
 	MPP_MODE(36,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
-		 MPP_VAR_FUNCTION(0x1, "spi", "mosi",       V_MV78230_PLUS)),
+		 MPP_VAR_FUNCTION(0x1, "spi0", "mosi",      V_MV78230_PLUS)),
 	MPP_MODE(37,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
-		 MPP_VAR_FUNCTION(0x1, "spi", "miso",       V_MV78230_PLUS)),
+		 MPP_VAR_FUNCTION(0x1, "spi0", "miso",      V_MV78230_PLUS)),
 	MPP_MODE(38,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
-		 MPP_VAR_FUNCTION(0x1, "spi", "sck",        V_MV78230_PLUS)),
+		 MPP_VAR_FUNCTION(0x1, "spi0", "sck",       V_MV78230_PLUS)),
 	MPP_MODE(39,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
-		 MPP_VAR_FUNCTION(0x1, "spi", "cs0",        V_MV78230_PLUS)),
+		 MPP_VAR_FUNCTION(0x1, "spi0", "cs0",       V_MV78230_PLUS)),
 	MPP_MODE(40,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
-		 MPP_VAR_FUNCTION(0x1, "spi", "cs1",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "spi0", "cs1",       V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x2, "uart2", "cts",      V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync",  V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0",   V_MV78230_PLUS)),
 	MPP_MODE(41,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
-		 MPP_VAR_FUNCTION(0x1, "spi", "cs2",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "spi0", "cs2",       V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x2, "uart2", "rts",      V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x3, "sata1", "prsnt",    V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync",  V_MV78230_PLUS),
@@ -257,32 +257,32 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x1, "uart2", "txd",      V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x2, "uart0", "rts",      V_MV78230_PLUS),
-		 MPP_VAR_FUNCTION(0x3, "spi", "cs3",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "spi0", "cs3",       V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x4, "pcie", "rstout",    V_MV78230_PLUS)),
 	MPP_MODE(44,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x1, "uart2", "cts",      V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x2, "uart3", "rxd",      V_MV78230_PLUS),
-		 MPP_VAR_FUNCTION(0x3, "spi", "cs4",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "spi0", "cs4",       V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x4, "dram", "bat",       V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2",   V_MV78230_PLUS)),
 	MPP_MODE(45,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x1, "uart2", "rts",      V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x2, "uart3", "txd",      V_MV78230_PLUS),
-		 MPP_VAR_FUNCTION(0x3, "spi", "cs5",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "spi0", "cs5",       V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x4, "sata1", "prsnt",    V_MV78230_PLUS)),
 	MPP_MODE(46,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x1, "uart3", "rts",      V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x2, "uart1", "rts",      V_MV78230_PLUS),
-		 MPP_VAR_FUNCTION(0x3, "spi", "cs6",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "spi0", "cs6",       V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x4, "sata0", "prsnt",    V_MV78230_PLUS)),
 	MPP_MODE(47,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x1, "uart3", "cts",      V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x2, "uart1", "cts",      V_MV78230_PLUS),
-		 MPP_VAR_FUNCTION(0x3, "spi", "cs7",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "spi0", "cs7",       V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x4, "ref", "clkout",     V_MV78230_PLUS),
 		 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3",   V_MV78230_PLUS)),
 	MPP_MODE(48,
-- 
2.1.0

  parent reply	other threads:[~2015-06-09 16:47 UTC|newest]

Thread overview: 95+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-09 16:46 [PATCH 00/34] pinctrl: mvebu: numerous fixes, cleanups and improvements Thomas Petazzoni
2015-06-09 16:46 ` [PATCH 01/34] pinctrl: mvebu: armada-38x: fix PCIe functions Thomas Petazzoni
2015-06-09 16:46   ` Thomas Petazzoni
2015-06-10  8:51   ` Linus Walleij
2015-06-10  8:51     ` Linus Walleij
2015-06-09 16:46 ` [PATCH 02/34] pinctrl: mvebu: armada-370: fix spi0 pin description Thomas Petazzoni
2015-06-09 16:46   ` Thomas Petazzoni
2015-06-10  8:52   ` Linus Walleij
2015-06-10  8:52     ` Linus Walleij
2015-06-09 16:46 ` [PATCH 03/34] pinctrl: mvebu: armada-375: remove non-existing NAND re/we pins Thomas Petazzoni
2015-06-09 16:46   ` Thomas Petazzoni
2015-06-09 16:58   ` Andrew Lunn
2015-06-09 16:58     ` Andrew Lunn
2015-06-16 13:17     ` Thomas Petazzoni
2015-06-16 13:17       ` Thomas Petazzoni
2015-06-10  8:54   ` Linus Walleij
2015-06-10  8:54     ` Linus Walleij
2015-06-09 16:46 ` [PATCH 04/34] pinctrl: mvebu: armada-xp: remove non-existing NAND pins Thomas Petazzoni
2015-06-09 16:46   ` Thomas Petazzoni
2015-06-09 16:46 ` [PATCH 05/34] pinctrl: mvebu: armada-xp: remove non-existing VDD cpu_pd functions Thomas Petazzoni
2015-06-09 16:46   ` Thomas Petazzoni
2015-06-10  8:55   ` Linus Walleij
2015-06-10  8:55     ` Linus Walleij
2015-06-09 16:46 ` [PATCH 06/34] pinctrl: mvebu: armada-xp: fix functions of MPP48 Thomas Petazzoni
2015-06-09 16:46   ` Thomas Petazzoni
2015-06-09 16:46 ` [PATCH 07/34] pinctrl: mvebu: armada-375: remove incorrect space in pin description Thomas Petazzoni
2015-06-09 16:46   ` Thomas Petazzoni
2015-06-09 16:47 ` [PATCH 08/34] pinctrl: mvebu: armada-38x: fix incorrect total number of GPIOs Thomas Petazzoni
2015-06-09 16:47   ` Thomas Petazzoni
2015-06-10  8:57   ` Linus Walleij
2015-06-10  8:57     ` Linus Walleij
2015-06-09 16:47 ` [PATCH 09/34] pinctrl: mvebu: armada-39x: " Thomas Petazzoni
2015-06-09 16:47   ` Thomas Petazzoni
2015-06-09 16:47 ` [PATCH 10/34] pinctrl: mvebu: armada-{375, 38x, 39x}: normalize naming of PTP subnames Thomas Petazzoni
2015-06-10  8:59   ` [PATCH 10/34] pinctrl: mvebu: armada-{375,38x,39x}: " Linus Walleij
2015-06-09 16:47 ` [PATCH 11/34] pinctrl: mvebu: armada-{38x, 39x, xp}: normalize naming of DRAM functions Thomas Petazzoni
2015-06-10  9:08   ` [PATCH 11/34] pinctrl: mvebu: armada-{38x,39x,xp}: " Linus Walleij
2015-06-09 16:47 ` [PATCH 12/34] pinctrl: mvebu: armada-39x: normalize SATA present functionality naming Thomas Petazzoni
2015-06-10  9:09   ` Linus Walleij
2015-06-09 16:47 ` [PATCH 13/34] pinctrl: mvebu: armada-39x: normalize SDIO pin naming Thomas Petazzoni
2015-06-10  9:10   ` Linus Walleij
2015-06-09 16:47 ` [PATCH 14/34] pinctrl: mvebu: armada-{370, 375, 38x, 39x}: normalize dev pins Thomas Petazzoni
2015-06-10  9:11   ` Linus Walleij
2015-06-09 16:47 ` [PATCH 15/34] pinctrl: mvebu: armada-39x: align NAND pin naming Thomas Petazzoni
2015-06-10  9:12   ` Linus Walleij
2015-06-10  9:15   ` Linus Walleij
2015-06-09 16:47 ` [PATCH 16/34] pinctrl: mvebu: armada-{370, 375, 38x, 39x, xp}: normalize TDM pins Thomas Petazzoni
2015-06-10 11:36   ` [PATCH 16/34] pinctrl: mvebu: armada-{370,375,38x,39x,xp}: " Linus Walleij
2015-06-09 16:47 ` [PATCH 17/34] pinctrl: mvebu: armada-{370,375}: normalize PCIe pins Thomas Petazzoni
2015-06-10 11:43   ` [PATCH 17/34] pinctrl: mvebu: armada-{370, 375}: " Linus Walleij
2015-06-09 16:47 ` [PATCH 18/34] pinctrl: mvebu: armada-{370,375}: normalize audio pins Thomas Petazzoni
2015-06-10 11:44   ` [PATCH 18/34] pinctrl: mvebu: armada-{370, 375}: " Linus Walleij
2015-06-09 16:47 ` [PATCH 19/34] pinctrl: mvebu: armada-{370, xp}: normalize ethernet txclkout pins Thomas Petazzoni
2015-06-10 11:50   ` Linus Walleij
2015-06-09 16:47 ` [PATCH 20/34] pinctrl: mvebu: armada-xp: fix binding documentation of ge1 pins Thomas Petazzoni
2015-06-10 11:56   ` Linus Walleij
2015-06-09 16:47 ` [PATCH 21/34] pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet Thomas Petazzoni
2015-06-10 11:57   ` Linus Walleij
2015-06-09 16:47 ` [PATCH 22/34] pinctrl: mvebu: armada-370: align spi1 clock pin naming Thomas Petazzoni
2015-06-10 12:00   ` Linus Walleij
2015-06-09 16:47 ` Thomas Petazzoni [this message]
2015-06-09 16:53   ` [PATCH 23/34] pinctrl: mvebu: armada-xp: rename spi to spi0 Andrew Lunn
2015-06-10 12:02     ` Linus Walleij
2015-06-10 12:01   ` Linus Walleij
2015-06-09 16:47 ` [PATCH 24/34] pinctrl: mvebu: armada-39x: normalize ref clock naming Thomas Petazzoni
2015-06-10 12:09   ` Linus Walleij
2015-06-09 16:47 ` [PATCH 25/34] pinctrl: mvebu: armada-xp: add spi1 function Thomas Petazzoni
2015-06-10 12:10   ` Linus Walleij
2015-06-09 16:47 ` [PATCH 26/34] pinctrl: mvebu: armada-xp: add nand rb function Thomas Petazzoni
2015-06-10 12:11   ` Linus Walleij
2015-06-09 16:47 ` [PATCH 27/34] pinctrl: mvebu: armada-xp: add dram functions Thomas Petazzoni
2015-06-10 12:12   ` Linus Walleij
2015-06-09 16:47 ` [PATCH 28/34] pinctrl: mvebu: armada-38x: add sata functions Thomas Petazzoni
2015-06-10 12:24   ` Linus Walleij
2015-06-09 16:47 ` [PATCH 29/34] pinctrl: mvebu: armada-38x: add nand functions Thomas Petazzoni
2015-06-10 12:25   ` Linus Walleij
2015-06-09 16:47 ` [PATCH 30/34] pinctrl: mvebu: armada-38x: add ua1 functions Thomas Petazzoni
2015-06-10 12:30   ` Linus Walleij
2015-06-09 16:47 ` [PATCH 31/34] pinctrl: mvebu: armada-38x: add ptp functions Thomas Petazzoni
2015-06-10 12:31   ` Linus Walleij
2015-06-09 16:47 ` [PATCH 32/34] pinctrl: mvebu: armada-39x: add missing PCIe functions Thomas Petazzoni
2015-06-10 12:32   ` Linus Walleij
2015-06-09 16:47 ` [PATCH 33/34] pinctrl: mvebu: armada-39x: add missing SATA functions Thomas Petazzoni
2015-06-10 12:35   ` Linus Walleij
2015-06-09 16:47 ` [PATCH 34/34] pinctrl: mvebu: armada-39x: add support for Armada 395 variant Thomas Petazzoni
2015-06-10 12:37   ` Linus Walleij
2015-06-09 17:01 ` [PATCH 00/34] pinctrl: mvebu: numerous fixes, cleanups and improvements Andrew Lunn
2015-06-09 19:22   ` Thomas Petazzoni
2015-06-09 19:47     ` Andrew Lunn
2015-06-09 20:34       ` Thomas Petazzoni
2015-06-09 21:36         ` Andrew Lunn
2015-06-10  8:08           ` Thomas Petazzoni
2015-06-10 12:39 ` Linus Walleij
2015-06-13 15:53   ` Gregory CLEMENT
2015-06-29 10:49     ` Linus Walleij

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1433868446-11028-24-git-send-email-thomas.petazzoni@free-electrons.com \
    --to=thomas.petazzoni@free-electrons.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.