From: marc.zyngier@arm.com (Marc Zyngier) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 02/12] KVM: arm64: add active register handling to GICv3 emulation as well Date: Fri, 19 Jun 2015 13:53:06 +0100 [thread overview] Message-ID: <1434718396-13110-3-git-send-email-marc.zyngier@arm.com> (raw) In-Reply-To: <1434718396-13110-1-git-send-email-marc.zyngier@arm.com> From: Andre Przywara <andre.przywara@arm.com> Commit 47a98b15ba7c ("arm/arm64: KVM: support for un-queuing active IRQs") introduced handling of the GICD_I[SC]ACTIVER registers, but only for the GICv2 emulation. For the sake of completeness and as this is a pre-requisite for save/restore of the GICv3 distributor state, we should also emulate their handling in the distributor and redistributor frames of an emulated GICv3. Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- virt/kvm/arm/vgic-v3-emul.c | 54 +++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 50 insertions(+), 4 deletions(-) diff --git a/virt/kvm/arm/vgic-v3-emul.c b/virt/kvm/arm/vgic-v3-emul.c index e9c3a7a..2b369de 100644 --- a/virt/kvm/arm/vgic-v3-emul.c +++ b/virt/kvm/arm/vgic-v3-emul.c @@ -173,6 +173,32 @@ static bool handle_mmio_clear_pending_reg_dist(struct kvm_vcpu *vcpu, return false; } +static bool handle_mmio_set_active_reg_dist(struct kvm_vcpu *vcpu, + struct kvm_exit_mmio *mmio, + phys_addr_t offset) +{ + if (likely(offset >= VGIC_NR_PRIVATE_IRQS / 8)) + return vgic_handle_set_active_reg(vcpu->kvm, mmio, offset, + vcpu->vcpu_id); + + vgic_reg_access(mmio, NULL, offset, + ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED); + return false; +} + +static bool handle_mmio_clear_active_reg_dist(struct kvm_vcpu *vcpu, + struct kvm_exit_mmio *mmio, + phys_addr_t offset) +{ + if (likely(offset >= VGIC_NR_PRIVATE_IRQS / 8)) + return vgic_handle_clear_active_reg(vcpu->kvm, mmio, offset, + vcpu->vcpu_id); + + vgic_reg_access(mmio, NULL, offset, + ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED); + return false; +} + static bool handle_mmio_priority_reg_dist(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, phys_addr_t offset) @@ -428,13 +454,13 @@ static const struct vgic_io_range vgic_v3_dist_ranges[] = { .base = GICD_ISACTIVER, .len = 0x80, .bits_per_irq = 1, - .handle_mmio = handle_mmio_raz_wi, + .handle_mmio = handle_mmio_set_active_reg_dist, }, { .base = GICD_ICACTIVER, .len = 0x80, .bits_per_irq = 1, - .handle_mmio = handle_mmio_raz_wi, + .handle_mmio = handle_mmio_clear_active_reg_dist, }, { .base = GICD_IPRIORITYR, @@ -561,6 +587,26 @@ static bool handle_mmio_clear_enable_reg_redist(struct kvm_vcpu *vcpu, ACCESS_WRITE_CLEARBIT); } +static bool handle_mmio_set_active_reg_redist(struct kvm_vcpu *vcpu, + struct kvm_exit_mmio *mmio, + phys_addr_t offset) +{ + struct kvm_vcpu *redist_vcpu = mmio->private; + + return vgic_handle_set_active_reg(vcpu->kvm, mmio, offset, + redist_vcpu->vcpu_id); +} + +static bool handle_mmio_clear_active_reg_redist(struct kvm_vcpu *vcpu, + struct kvm_exit_mmio *mmio, + phys_addr_t offset) +{ + struct kvm_vcpu *redist_vcpu = mmio->private; + + return vgic_handle_clear_active_reg(vcpu->kvm, mmio, offset, + redist_vcpu->vcpu_id); +} + static bool handle_mmio_set_pending_reg_redist(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, phys_addr_t offset) @@ -674,13 +720,13 @@ static const struct vgic_io_range vgic_redist_ranges[] = { .base = SGI_base(GICR_ISACTIVER0), .len = 0x04, .bits_per_irq = 1, - .handle_mmio = handle_mmio_raz_wi, + .handle_mmio = handle_mmio_set_active_reg_redist, }, { .base = SGI_base(GICR_ICACTIVER0), .len = 0x04, .bits_per_irq = 1, - .handle_mmio = handle_mmio_raz_wi, + .handle_mmio = handle_mmio_clear_active_reg_redist, }, { .base = SGI_base(GICR_IPRIORITYR0), -- 2.1.4
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <marc.zyngier@arm.com> To: Paolo Bonzini <pbonzini@redhat.com>, Marcelo Tosatti <mtosatti@redhat.com>, Gleb Natapov <gleb@kernel.org> Cc: "Andre Przywara" <andre.przywara@arm.com>, "Christoffer Dall" <christoffer.dall@linaro.org>, "Firo Yang" <firogm@gmail.com>, "Tiejun Chen" <tiejun.chen@intel.com>, "Eric Auger" <eric.auger@linaro.org>, "Alex Bennée" <alex.bennee@linaro.org>, "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Subject: [PATCH 02/12] KVM: arm64: add active register handling to GICv3 emulation as well Date: Fri, 19 Jun 2015 13:53:06 +0100 [thread overview] Message-ID: <1434718396-13110-3-git-send-email-marc.zyngier@arm.com> (raw) In-Reply-To: <1434718396-13110-1-git-send-email-marc.zyngier@arm.com> From: Andre Przywara <andre.przywara@arm.com> Commit 47a98b15ba7c ("arm/arm64: KVM: support for un-queuing active IRQs") introduced handling of the GICD_I[SC]ACTIVER registers, but only for the GICv2 emulation. For the sake of completeness and as this is a pre-requisite for save/restore of the GICv3 distributor state, we should also emulate their handling in the distributor and redistributor frames of an emulated GICv3. Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- virt/kvm/arm/vgic-v3-emul.c | 54 +++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 50 insertions(+), 4 deletions(-) diff --git a/virt/kvm/arm/vgic-v3-emul.c b/virt/kvm/arm/vgic-v3-emul.c index e9c3a7a..2b369de 100644 --- a/virt/kvm/arm/vgic-v3-emul.c +++ b/virt/kvm/arm/vgic-v3-emul.c @@ -173,6 +173,32 @@ static bool handle_mmio_clear_pending_reg_dist(struct kvm_vcpu *vcpu, return false; } +static bool handle_mmio_set_active_reg_dist(struct kvm_vcpu *vcpu, + struct kvm_exit_mmio *mmio, + phys_addr_t offset) +{ + if (likely(offset >= VGIC_NR_PRIVATE_IRQS / 8)) + return vgic_handle_set_active_reg(vcpu->kvm, mmio, offset, + vcpu->vcpu_id); + + vgic_reg_access(mmio, NULL, offset, + ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED); + return false; +} + +static bool handle_mmio_clear_active_reg_dist(struct kvm_vcpu *vcpu, + struct kvm_exit_mmio *mmio, + phys_addr_t offset) +{ + if (likely(offset >= VGIC_NR_PRIVATE_IRQS / 8)) + return vgic_handle_clear_active_reg(vcpu->kvm, mmio, offset, + vcpu->vcpu_id); + + vgic_reg_access(mmio, NULL, offset, + ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED); + return false; +} + static bool handle_mmio_priority_reg_dist(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, phys_addr_t offset) @@ -428,13 +454,13 @@ static const struct vgic_io_range vgic_v3_dist_ranges[] = { .base = GICD_ISACTIVER, .len = 0x80, .bits_per_irq = 1, - .handle_mmio = handle_mmio_raz_wi, + .handle_mmio = handle_mmio_set_active_reg_dist, }, { .base = GICD_ICACTIVER, .len = 0x80, .bits_per_irq = 1, - .handle_mmio = handle_mmio_raz_wi, + .handle_mmio = handle_mmio_clear_active_reg_dist, }, { .base = GICD_IPRIORITYR, @@ -561,6 +587,26 @@ static bool handle_mmio_clear_enable_reg_redist(struct kvm_vcpu *vcpu, ACCESS_WRITE_CLEARBIT); } +static bool handle_mmio_set_active_reg_redist(struct kvm_vcpu *vcpu, + struct kvm_exit_mmio *mmio, + phys_addr_t offset) +{ + struct kvm_vcpu *redist_vcpu = mmio->private; + + return vgic_handle_set_active_reg(vcpu->kvm, mmio, offset, + redist_vcpu->vcpu_id); +} + +static bool handle_mmio_clear_active_reg_redist(struct kvm_vcpu *vcpu, + struct kvm_exit_mmio *mmio, + phys_addr_t offset) +{ + struct kvm_vcpu *redist_vcpu = mmio->private; + + return vgic_handle_clear_active_reg(vcpu->kvm, mmio, offset, + redist_vcpu->vcpu_id); +} + static bool handle_mmio_set_pending_reg_redist(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, phys_addr_t offset) @@ -674,13 +720,13 @@ static const struct vgic_io_range vgic_redist_ranges[] = { .base = SGI_base(GICR_ISACTIVER0), .len = 0x04, .bits_per_irq = 1, - .handle_mmio = handle_mmio_raz_wi, + .handle_mmio = handle_mmio_set_active_reg_redist, }, { .base = SGI_base(GICR_ICACTIVER0), .len = 0x04, .bits_per_irq = 1, - .handle_mmio = handle_mmio_raz_wi, + .handle_mmio = handle_mmio_clear_active_reg_redist, }, { .base = SGI_base(GICR_IPRIORITYR0), -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe kvm" in
next prev parent reply other threads:[~2015-06-19 12:53 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-06-19 12:53 [PULL] KVM/ARM changes for 4.2 Marc Zyngier 2015-06-19 12:53 ` Marc Zyngier 2015-06-19 12:53 ` [PATCH 01/12] ARM: KVM: Remove pointless void pointer cast Marc Zyngier 2015-06-19 12:53 ` Marc Zyngier 2015-06-19 12:53 ` Marc Zyngier [this message] 2015-06-19 12:53 ` [PATCH 02/12] KVM: arm64: add active register handling to GICv3 emulation as well Marc Zyngier 2015-06-19 12:53 ` [PATCH 03/12] arm: KVM: force execution of HCPTR access on VM exit Marc Zyngier 2015-06-19 12:53 ` Marc Zyngier 2015-06-19 12:53 ` [PATCH 04/12] kvm: remove one useless check extension Marc Zyngier 2015-06-19 12:53 ` Marc Zyngier 2015-06-19 12:53 ` [PATCH 05/12] arm/arm64: KVM: Properly account for guest CPU time Marc Zyngier 2015-06-19 12:53 ` Marc Zyngier 2015-07-10 14:16 ` KVM/ARM: trap every load /store instruction hiwu 2015-11-02 18:36 ` Christopher Covington 2015-06-19 12:53 ` [PATCH 06/12] KVM: arm/arm64: Enable the KVM-VFIO device Marc Zyngier 2015-06-19 12:53 ` Marc Zyngier 2015-06-19 12:53 ` [PATCH 07/12] KVM: arm64: fix misleading comments in save/restore Marc Zyngier 2015-06-19 12:53 ` Marc Zyngier 2015-06-19 12:53 ` [PATCH 08/12] ARM: kvm: psci: fix handling of unimplemented functions Marc Zyngier 2015-06-19 12:53 ` Marc Zyngier 2015-06-19 12:53 ` [PATCH 09/12] KVM: arm: vgic: Drop useless Group0 warning Marc Zyngier 2015-06-19 12:53 ` Marc Zyngier 2015-06-19 12:53 ` [PATCH 10/12] arm/arm64: KVM: vgic: Do not save GICH_HCR / ICH_HCR_EL2 Marc Zyngier 2015-06-19 12:53 ` Marc Zyngier 2015-06-19 12:53 ` [PATCH 11/12] KVM: arm/arm64: vgic: Avoid injecting reserved IRQ numbers Marc Zyngier 2015-06-19 12:53 ` Marc Zyngier 2015-06-19 12:53 ` [PATCH 12/12] KVM: arm/arm64: vgic: Remove useless arm-gic.h #include Marc Zyngier 2015-06-19 12:53 ` Marc Zyngier 2015-06-19 15:16 ` [PULL] KVM/ARM changes for 4.2 Paolo Bonzini 2015-06-19 15:16 ` Paolo Bonzini
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