From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 07/12] target-arm: Add support for Cortex-R5
Date: Fri, 19 Jun 2015 14:47:11 +0100 [thread overview]
Message-ID: <1434721636-25357-8-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1434721636-25357-1-git-send-email-peter.maydell@linaro.org>
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Introduce a CPU model for the Cortex R5 processor. ARMv7 with MPU,
and both thumb and ARM div instructions.
Also implement dummy ATCM and BTCM. These CPs are defined for R5 but
don't have a lot of meaning in QEMU yet. Raz them so the guest can
proceed if they are read. The TCM registers will return a size of 0,
indicating no TCM.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: efe213163e6800578494aba864ac30329de4d396.1434501320.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index eb10f59..b3d07ac 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -856,6 +856,43 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
}
+static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
+ /* Dummy the TCM region regs for the moment */
+ { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST },
+ { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
+ .access = PL1_RW, .type = ARM_CP_CONST },
+ REGINFO_SENTINEL
+};
+
+static void cortex_r5_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
+ set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
+ set_feature(&cpu->env, ARM_FEATURE_V7MP);
+ set_feature(&cpu->env, ARM_FEATURE_MPU);
+ cpu->midr = 0x411fc153; /* r1p3 */
+ cpu->id_pfr0 = 0x0131;
+ cpu->id_pfr1 = 0x001;
+ cpu->id_dfr0 = 0x010400;
+ cpu->id_afr0 = 0x0;
+ cpu->id_mmfr0 = 0x0210030;
+ cpu->id_mmfr1 = 0x00000000;
+ cpu->id_mmfr2 = 0x01200000;
+ cpu->id_mmfr3 = 0x0211;
+ cpu->id_isar0 = 0x2101111;
+ cpu->id_isar1 = 0x13112111;
+ cpu->id_isar2 = 0x21232141;
+ cpu->id_isar3 = 0x01112131;
+ cpu->id_isar4 = 0x0010142;
+ cpu->id_isar5 = 0x0;
+ cpu->mp_is_up = true;
+ define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
+}
+
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -1249,6 +1286,7 @@ static const ARMCPUInfo arm_cpus[] = {
.class_init = arm_v7m_class_init },
{ .name = "cortex-m4", .initfn = cortex_m4_initfn,
.class_init = arm_v7m_class_init },
+ { .name = "cortex-r5", .initfn = cortex_r5_initfn },
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
--
1.9.1
next prev parent reply other threads:[~2015-06-19 13:47 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-19 13:47 [Qemu-devel] [PULL 00/12] target-arm queue Peter Maydell
2015-06-19 13:47 ` [Qemu-devel] [PULL 01/12] target-arm: Add the Cortex-M4 CPU Peter Maydell
2015-06-19 13:47 ` [Qemu-devel] [PULL 02/12] hw/arm/sysbus-fdt: enable vfio-calxeda-xgmac dynamic instantiation Peter Maydell
2015-06-19 13:47 ` [Qemu-devel] [PULL 03/12] target-arm: Do not reset sysregs marked as ALIAS Peter Maydell
2015-06-19 13:47 ` [Qemu-devel] [PULL 04/12] target-arm/helper.c: define MPUIR register Peter Maydell
2015-06-19 13:47 ` [Qemu-devel] [PULL 05/12] target-arm: Add registers for PMSAv7 Peter Maydell
2015-06-19 13:47 ` [Qemu-devel] [PULL 06/12] target-arm: Implement PMSAv7 MPU Peter Maydell
2015-06-19 13:47 ` Peter Maydell [this message]
2017-05-05 12:05 ` [Qemu-devel] [PULL 07/12] target-arm: Add support for Cortex-R5 Philippe Mathieu-Daudé
2015-06-19 13:47 ` [Qemu-devel] [PULL 08/12] arm: xlnx-zynqmp: Preface CPU variables with "apu" Peter Maydell
2015-06-19 13:47 ` [Qemu-devel] [PULL 09/12] arm: xlnx-zynqmp: Add boot-cpu property Peter Maydell
2015-06-19 13:47 ` [Qemu-devel] [PULL 10/12] arm: xlnx-zynqmp: Add 2xCortexR5 CPUs Peter Maydell
2015-07-09 14:19 ` Paolo Bonzini
2015-06-19 13:47 ` [Qemu-devel] [PULL 11/12] semihosting: create SemihostingConfig structure and semihost.h Peter Maydell
2015-06-19 13:47 ` [Qemu-devel] [PULL 12/12] semihosting: add --semihosting-config arg sub-argument Peter Maydell
2015-06-19 17:32 ` [Qemu-devel] [PULL 00/12] target-arm queue Peter Maydell
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