From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH 0/2] target-mips: minor clean up in mtc0 and mfc0
Date: Mon, 14 Sep 2015 13:45:52 +0100 [thread overview]
Message-ID: <1442234754-15692-1-git-send-email-leon.alrae@imgtec.com> (raw)
This patchset removes the gen_mtc0_store64() which is actually incorrect
as MTC0 instruction in MIPS64 is supposed to move entire content (if
dst CP0 register is 64-bit) without sign extending. It also removes the
gen_mfc0_load64() and replaces the pair of tcg_gen_ld_tl() +
tcg_gen_ext32s_tl() with single tcg_gen_ld32s_tl().
Leon Alrae (2):
target-mips: correct MTC0 instruction on MIPS64
target-mips: remove gen_mfc0_load64() and use tcg_gen_ld32s_tl()
target-mips/translate.c | 61 +++++++++++++++++++------------------------------
1 file changed, 24 insertions(+), 37 deletions(-)
--
2.1.0
next reply other threads:[~2015-09-14 12:46 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-14 12:45 Leon Alrae [this message]
2015-09-14 12:45 ` [Qemu-devel] [PATCH 1/2] target-mips: correct MTC0 instruction on MIPS64 Leon Alrae
2015-09-14 12:45 ` [Qemu-devel] [PATCH 2/2] target-mips: remove gen_mfc0_load64() and use tcg_gen_ld32s_tl() Leon Alrae
2015-09-16 18:14 ` Richard Henderson
2015-09-16 19:00 ` Leon Alrae
2015-09-16 4:46 ` [Qemu-devel] [PATCH 0/2] target-mips: minor clean up in mtc0 and mfc0 Aurelien Jarno
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