From: Leon Alrae <leon.alrae@imgtec.com>
To: Richard Henderson <rth@twiddle.net>, qemu-devel@nongnu.org
Cc: aurelien@aurel32.net
Subject: Re: [Qemu-devel] [PATCH 2/2] target-mips: remove gen_mfc0_load64() and use tcg_gen_ld32s_tl()
Date: Wed, 16 Sep 2015 20:00:45 +0100 [thread overview]
Message-ID: <55F9BC5D.6020604@imgtec.com> (raw)
In-Reply-To: <55F9B198.3070708@twiddle.net>
On 16/09/15 19:14, Richard Henderson wrote:
> On 09/14/2015 05:45 AM, Leon Alrae wrote:
>> -static inline void gen_mfc0_load64 (TCGv arg, target_ulong off)
>> -{
>> - tcg_gen_ld_tl(arg, cpu_env, off);
>> - tcg_gen_ext32s_tl(arg, arg);
>> -}
>> -
>> static inline void gen_mtc0_store32 (TCGv arg, target_ulong off)
>> {
>> TCGv_i32 t0 = tcg_temp_new_i32();
>> @@ -4972,17 +4966,19 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
>> break;
>> case 4:
>> CP0_CHECK(ctx->insn_flags & ASE_MT);
>> - gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask));
>> + tcg_gen_ld32s_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
>> rn = "YQMask";
>> break;
>
> This change is broken for 64-bit guest and big-endian host -- one has to adjust
> the offset in that case. I suspect that's why the extension was separate to
> begin with...
Uh, I think I wasn't expecting that ld32s_i64 actually does 32-bit load.
It means that CP0_UserLocal needs fixing in current code.
Thanks,
Leon
next prev parent reply other threads:[~2015-09-16 19:01 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-14 12:45 [Qemu-devel] [PATCH 0/2] target-mips: minor clean up in mtc0 and mfc0 Leon Alrae
2015-09-14 12:45 ` [Qemu-devel] [PATCH 1/2] target-mips: correct MTC0 instruction on MIPS64 Leon Alrae
2015-09-14 12:45 ` [Qemu-devel] [PATCH 2/2] target-mips: remove gen_mfc0_load64() and use tcg_gen_ld32s_tl() Leon Alrae
2015-09-16 18:14 ` Richard Henderson
2015-09-16 19:00 ` Leon Alrae [this message]
2015-09-16 4:46 ` [Qemu-devel] [PATCH 0/2] target-mips: minor clean up in mtc0 and mfc0 Aurelien Jarno
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