From: Yash Shah <yash.shah@sifive.com> To: paul.walmsley@sifive.com, palmer@dabbelt.com, robh+dt@kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sachin.ghadi@sifive.com Cc: aou@eecs.berkeley.edu, bmeng.cn@gmail.com, green.wan@sifive.com, atish.patra@wdc.com, anup@brainfault.org, alistair.francis@wdc.com, lollivier@baylibre.com, deepa.kernel@gmail.com, Yash Shah <yash.shah@sifive.com> Subject: [PATCH 3/3] riscv: dts: HiFive Unleashed: define a default set of CPU OPPs Date: Tue, 16 Jun 2020 17:31:04 +0530 [thread overview] Message-ID: <1592308864-30205-4-git-send-email-yash.shah@sifive.com> (raw) In-Reply-To: <1592308864-30205-1-git-send-email-yash.shah@sifive.com> Define a default set of CPU OPPs for the HiFive Unleashed with the FU540-C000 SoC. This allows CPUFreq to be enabled for this board. The FU540-C000 SoC PVT corners haven't been characterized separately from the HiFive Unleashed board. Thus the OPPs are added to the board DT file, rather than the SoC itself. The specific selection of OPPs are designed to enable fast switching by simply changing the CORE PLL output divider. The exception is the 1GHz OPP. Since the OPP code apparently requires that, upon kernel start, the CPU clock frequency must have been set to an existing OPP frequency, the 1GHz rate is present solely because the default HiFive Unleashed bootloaders set the CPU to run at 1GHz before starting the kernel. Signed-off-by: Yash Shah <yash.shah@sifive.com> --- .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts index 4a2729f..59db9c0 100644 --- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts @@ -46,6 +46,44 @@ compatible = "gpio-restart"; gpios = <&gpio 10 GPIO_ACTIVE_LOW>; }; + + fu540_c000_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-350000000 { + opp-hz = /bits/ 64 <350000000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + }; + opp-999999999 { + opp-hz = /bits/ 64 <999999999>; + }; + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&fu540_c000_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&fu540_c000_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&fu540_c000_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&fu540_c000_opp_table>; +}; + +&cpu4 { + operating-points-v2 = <&fu540_c000_opp_table>; }; &uart0 { -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Yash Shah <yash.shah@sifive.com> To: paul.walmsley@sifive.com, palmer@dabbelt.com, robh+dt@kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sachin.ghadi@sifive.com Cc: aou@eecs.berkeley.edu, anup@brainfault.org, lollivier@baylibre.com, green.wan@sifive.com, atish.patra@wdc.com, Yash Shah <yash.shah@sifive.com>, alistair.francis@wdc.com, deepa.kernel@gmail.com, bmeng.cn@gmail.com Subject: [PATCH 3/3] riscv: dts: HiFive Unleashed: define a default set of CPU OPPs Date: Tue, 16 Jun 2020 17:31:04 +0530 [thread overview] Message-ID: <1592308864-30205-4-git-send-email-yash.shah@sifive.com> (raw) In-Reply-To: <1592308864-30205-1-git-send-email-yash.shah@sifive.com> Define a default set of CPU OPPs for the HiFive Unleashed with the FU540-C000 SoC. This allows CPUFreq to be enabled for this board. The FU540-C000 SoC PVT corners haven't been characterized separately from the HiFive Unleashed board. Thus the OPPs are added to the board DT file, rather than the SoC itself. The specific selection of OPPs are designed to enable fast switching by simply changing the CORE PLL output divider. The exception is the 1GHz OPP. Since the OPP code apparently requires that, upon kernel start, the CPU clock frequency must have been set to an existing OPP frequency, the 1GHz rate is present solely because the default HiFive Unleashed bootloaders set the CPU to run at 1GHz before starting the kernel. Signed-off-by: Yash Shah <yash.shah@sifive.com> --- .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts index 4a2729f..59db9c0 100644 --- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts @@ -46,6 +46,44 @@ compatible = "gpio-restart"; gpios = <&gpio 10 GPIO_ACTIVE_LOW>; }; + + fu540_c000_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-350000000 { + opp-hz = /bits/ 64 <350000000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + }; + opp-999999999 { + opp-hz = /bits/ 64 <999999999>; + }; + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&fu540_c000_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&fu540_c000_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&fu540_c000_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&fu540_c000_opp_table>; +}; + +&cpu4 { + operating-points-v2 = <&fu540_c000_opp_table>; }; &uart0 { -- 2.7.4
next prev parent reply other threads:[~2020-06-16 12:01 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-06-16 12:01 [PATCH 0/3] Dynamic CPU frequency switching for the HiFive Yash Shah 2020-06-16 12:01 ` Yash Shah 2020-06-16 12:01 ` [PATCH 1/3] riscv: defconfig, Kconfig: enable CPU power management Yash Shah 2020-06-16 12:01 ` Yash Shah 2020-06-16 12:01 ` [PATCH 2/3] riscv: dts: fu540-c000: define hart clocks Yash Shah 2020-06-16 12:01 ` Yash Shah 2021-06-16 3:16 ` Bin Meng 2021-06-16 3:16 ` Bin Meng 2021-06-16 15:13 ` David Abdurachmanov 2021-06-16 15:13 ` David Abdurachmanov 2021-06-16 22:56 ` Bin Meng 2021-06-16 22:56 ` Bin Meng 2020-06-16 12:01 ` Yash Shah [this message] 2020-06-16 12:01 ` [PATCH 3/3] riscv: dts: HiFive Unleashed: define a default set of CPU OPPs Yash Shah 2020-06-29 9:30 ` [PATCH 0/3] Dynamic CPU frequency switching for the HiFive Greentime Hu 2020-06-29 9:30 ` Greentime Hu 2020-07-01 10:40 ` Andreas Schwab 2020-07-01 10:40 ` Andreas Schwab 2020-07-01 12:04 ` David Abdurachmanov 2020-07-01 12:04 ` David Abdurachmanov 2020-07-03 5:53 ` Yash Shah 2020-07-03 5:53 ` Yash Shah 2020-07-06 8:15 ` Andreas Schwab 2020-07-06 8:15 ` Andreas Schwab 2020-07-09 20:48 ` Palmer Dabbelt 2020-07-09 20:48 ` Palmer Dabbelt 2020-07-08 12:06 ` Yash Shah 2020-07-08 12:06 ` Yash Shah
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