From: Andrey Shinkevich <andrey.shinkevich@huawei.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "peter.maydell@linaro.org" <peter.maydell@linaro.org>,
"drjones@redhat.com" <drjones@redhat.com>,
"richard.henderson@linaro.org" <richard.henderson@linaro.org>,
"qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
"Chengen \(William, FixNet\)" <chengen@huawei.com>,
"alex.bennee@linaro.org" <alex.bennee@linaro.org>
Subject: GICv3 for MTTCG
Date: Tue, 11 May 2021 17:51:17 +0000 [thread overview]
Message-ID: <1f157423cc544731beb743287a4be5cb@huawei.com> (raw)
Dear colleagues,
I am looking for ways to accelerate the MTTCG for ARM guest on x86-64 host.
The maximum number of CPUs for MTTCG that uses GICv2 is limited by 8:
include/hw/intc/arm_gic_common.h:#define GIC_NCPU 8
The version 3 of the Generic Interrupt Controller (GICv3) is not
supported in QEMU for some reason unknown to me. It would allow to
increase the limit of CPUs and accelerate the MTTCG performance on a
multiple core hypervisor.
I have got an idea to implement the Interrupt Translation Service (ITS)
for using by MTTCG for ARM architecture.
Do you find that idea useful and feasible?
If yes, how much time do you estimate for such a project to complete by
one developer?
If no, what are reasons for not implementing GICv3 for MTTCG in QEMU?
Best regards,
Andrey Shinkevich
next reply other threads:[~2021-05-11 20:12 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-11 17:51 Andrey Shinkevich [this message]
2021-05-11 19:53 ` GICv3 for MTTCG Richard Henderson
2021-05-12 1:44 ` Zenghui Yu
2021-05-12 15:26 ` Alex Bennée
2021-05-13 16:35 ` Andrey Shinkevich
2021-05-13 16:45 ` Shashi Mallela
2021-05-13 18:29 ` Andrey Shinkevich
2021-06-17 16:43 ` Andrey Shinkevich
2021-06-17 17:44 ` shashi.mallela
2021-06-17 18:55 ` Andrey Shinkevich
2021-06-18 13:15 ` Alex Bennée
2021-06-18 15:18 ` Andrey Shinkevich
2021-05-13 17:19 ` Alex Bennée
2021-05-13 18:33 ` Andrey Shinkevich
2021-05-14 5:21 ` Andrey Shinkevich
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