Re: [Intel-gfx] [-next] WARNING at i915_gem_track_fb

From: Daniel Vetter <daniel@ffwll.ch>
To: Sergey Senozhatsky <sergey.senozhatsky@gmail.com>
Cc: Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@linux.ie>,
	intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	linux-kernel@vger.kernel.org
Subject: Re: [Intel-gfx] [-next] WARNING at i915_gem_track_fb
Date: Tue, 14 Jul 2015 17:11:56 +0200	[thread overview]
Message-ID: <20150714151156.GC3736@phenom.ffwll.local> (raw)
In-Reply-To: <20150714134142.GA556@swordfish>

On Tue, Jul 14, 2015 at 10:41:42PM +0900, Sergey Senozhatsky wrote:
> On (07/14/15 14:44), Daniel Vetter wrote:
> > > that helped. seems to be working only on -next.
> > 
> > You mean you only get a backtrace on -next, right? 
> 
> yeah, sure :-)
> 
> > Otherwise I'd be confused ;-)
> > 
> > Next up. Please boot with drm.debug=0xe, repro the issue and attach
> > complete dmesg (from boot-up up to the WARNING). That should help us
> > reconstruct how things went wrong here.
> 
> can't reproduce it thus far.

Have you forwarded to a more recent -nightly? I just merged a patch which
might have fixed this ...
-Daniel

> 
> sometimes `xset dpms force off' just turns off the panel for a second,
> sometimes -- until I generate a `wakeup' event (key press, etc.)
> part of dmesg (no WARNING yet)
> 
> [  253.699215] [drm:check_encoder_state] [ENCODER:32:DAC-32]
> [  253.699217] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
> [  253.699219] [drm:check_encoder_state] [ENCODER:41:TMDS-41]
> [  253.699221] [drm:check_crtc_state] [CRTC:21]
> [  253.699225] [drm:check_crtc_state] [CRTC:25]
> [  253.699226] [drm:check_crtc_state] [CRTC:29]
> [  253.699228] [drm:check_shared_dpll_state] WRPLL 1
> [  253.699230] [drm:check_shared_dpll_state] WRPLL 2
> [  253.699270] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/976
> [  256.612288] [drm:drm_mode_setcrtc] [CRTC:21]
> [  256.612299] [drm:drm_mode_setcrtc] [CONNECTOR:34:eDP-1]
> [  256.612302] [drm:intel_crtc_set_config] [CRTC:21] [FB:45] #connectors=1 (x y) (0 0)
> [  256.612308] [drm:intel_modeset_stage_output_state] [CONNECTOR:34:eDP-1] to [CRTC:21]
> [  256.612317] [drm:connected_sink_compute_bpp] [CONNECTOR:34:eDP-1] checking for sink bpp constrains
> [  256.612318] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 18
> [  256.612322] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 143000KHz
> [  256.612324] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
> [  256.612326] [drm:intel_dp_compute_config] DP link bw required 257400 available 432000
> [  256.612328] [drm:intel_modeset_pipe_config] plane bpp: 36, pipe bpp: 18, dithering: 1
> [  256.612331] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff8800c6683400 for pipe A
> [  256.612332] [drm:intel_dump_pipe_config] cpu_transcoder: D
> [  256.612333] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
> [  256.612335] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
> [  256.612337] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4998212, gmch_n: 8388608, link_m: 277678, link_n: 524288, tu: 64
> [  256.612339] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
> [  256.612340] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
> [  256.612342] [drm:intel_dump_pipe_config] requested mode:
> [  256.612344] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 143000 1920 1968 2000 2080 1080 1082 1087 1144 0x0 0xa
> [  256.612346] [drm:intel_dump_pipe_config] adjusted mode:
> [  256.612348] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 143000 1920 1968 2000 2080 1080 1082 1087 1144 0x48 0xa
> [  256.612350] [drm:intel_dump_crtc_timings] crtc timings: 143000 1920 1968 2000 2080 1080 1082 1087 1144, type: 0x48 flags: 0xa
> [  256.612351] [drm:intel_dump_pipe_config] port clock: 270000
> [  256.612353] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
> [  256.612354] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
> [  256.612356] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
> [  256.612358] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
> [  256.612359] [drm:intel_dump_pipe_config] ips: 0
> [  256.612360] [drm:intel_dump_pipe_config] double wide: 0
> [  256.612362] [drm:intel_dump_pipe_config] ddi_pll_sel: 536870912; dpll_hw_state: wrpll: 0x0
> [  256.612363] [drm:intel_dump_pipe_config] planes on this crtc
> [  256.612365] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 enabled
> [  256.612367] [drm:intel_dump_pipe_config] 	FB:45, fb = 1920x1080 format = 0x34325258
> [  256.612369] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 0x0 dst (0, 0) 0x0
> [  256.612371] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 disabled, scaler_id = 0
> [  256.612372] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = 0
> [  256.612425] [drm:edp_panel_on] Turn eDP port A panel power on
> [  256.612429] [drm:wait_panel_power_cycle] Wait for panel power cycle
> [  256.612433] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
> [  256.612436] [drm:wait_panel_status] Wait complete
> [  256.612441] [drm:wait_panel_on] Wait for panel power on
> [  256.612445] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
> [  256.820170] [drm:wait_panel_status] Wait complete
> [  256.820188] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
> [  256.820198] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
> [  256.821378] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
> [  256.821381] [drm:intel_dp_set_signal_levels] Using vswing level 0
> [  256.821382] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
> [  256.822078] [drm:intel_dp_start_link_train] clock recovery OK
> [  256.823078] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
> [  256.823193] [drm:intel_enable_pipe] enabling pipe A
> [  256.823373] [drm:intel_edp_backlight_on] 
> [  256.823376] [drm:intel_panel_enable_backlight] pipe A
> [  256.823382] [drm:intel_panel_actually_set_backlight] set backlight PWM = 976
> [  256.902952] [drm:intel_psr_enable] PSR not supported by this panel
> [  256.902957] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
> [  256.906664] [drm:intel_connector_check_state] [CONNECTOR:34:eDP-1]
> [  256.906672] [drm:check_encoder_state] [ENCODER:32:DAC-32]
> [  256.906675] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
> [  256.906678] [drm:check_encoder_state] [ENCODER:41:TMDS-41]
> [  256.906681] [drm:check_crtc_state] [CRTC:21]
> [  256.906694] [drm:check_crtc_state] [CRTC:25]
> [  256.906696] [drm:check_crtc_state] [CRTC:29]
> [  256.906699] [drm:check_shared_dpll_state] WRPLL 1
> [  256.906701] [drm:check_shared_dpll_state] WRPLL 2
> [  256.907526] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=48/976
> [  256.907530] [drm:intel_panel_actually_set_backlight] set backlight PWM = 66
> [  259.832755] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
> [  259.832766] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
> [  319.905770] [drm:connected_sink_compute_bpp] [CONNECTOR:34:eDP-1] checking for sink bpp constrains
> [  319.905774] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 18
> [  319.905779] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 143000KHz
> [  319.905781] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
> [  319.905783] [drm:intel_dp_compute_config] DP link bw required 257400 available 432000
> [  319.905785] [drm:intel_modeset_pipe_config] plane bpp: 36, pipe bpp: 18, dithering: 1
> [  319.905788] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff88041719ec00 for pipe A
> [  319.905789] [drm:intel_dump_pipe_config] cpu_transcoder: D
> [  319.905790] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
> [  319.905792] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
> [  319.905794] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4998212, gmch_n: 8388608, link_m: 277678, link_n: 524288, tu: 64
> [  319.905796] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
> [  319.905797] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
> [  319.905798] [drm:intel_dump_pipe_config] requested mode:
> [  319.905801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 143000 1920 1968 2000 2080 1080 1082 1087 1144 0x0 0xa
> [  319.905802] [drm:intel_dump_pipe_config] adjusted mode:
> [  319.905805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 143000 1920 1968 2000 2080 1080 1082 1087 1144 0x48 0xa
> [  319.905807] [drm:intel_dump_crtc_timings] crtc timings: 143000 1920 1968 2000 2080 1080 1082 1087 1144, type: 0x48 flags: 0xa
> [  319.905808] [drm:intel_dump_pipe_config] port clock: 270000
> [  319.905810] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
> [  319.905811] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
> [  319.905813] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
> [  319.905815] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
> [  319.905816] [drm:intel_dump_pipe_config] ips: 0
> [  319.905817] [drm:intel_dump_pipe_config] double wide: 0
> [  319.905819] [drm:intel_dump_pipe_config] ddi_pll_sel: 536870912; dpll_hw_state: wrpll: 0x0
> [  319.905820] [drm:intel_dump_pipe_config] planes on this crtc
> [  319.905822] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 enabled
> [  319.905823] [drm:intel_dump_pipe_config] 	FB:45, fb = 1920x1080 format = 0x34325258
> [  319.905826] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 1920x1080 dst (0, 0) 1920x1080
> [  319.905827] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 enabled
> [  319.905829] [drm:intel_dump_pipe_config] 	FB:47, fb = 64x64 format = 0x34325241
> [  319.905831] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 64x64 dst (834, 885) 64x64
> [  319.905833] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = 0
> [  319.905861] [drm:intel_edp_backlight_off] 
> [  320.109032] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
> [  320.109052] [drm:intel_disable_pipe] disabling pipe A
> [  320.126997] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
> [  320.127010] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
> [  320.127242] [drm:edp_panel_off] Turn eDP port A panel power off
> [  320.127249] [drm:wait_panel_off] Wait for panel power off time
> [  320.127254] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
> [  320.187583] [drm:wait_panel_status] Wait complete
> [  320.187632] [drm:check_encoder_state] [ENCODER:32:DAC-32]
> [  320.187636] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
> [  320.187638] [drm:check_encoder_state] [ENCODER:41:TMDS-41]
> [  320.187641] [drm:check_crtc_state] [CRTC:21]
> [  320.187645] [drm:check_crtc_state] [CRTC:25]
> [  320.187647] [drm:check_crtc_state] [CRTC:29]
> [  320.187649] [drm:check_shared_dpll_state] WRPLL 1
> [  320.187651] [drm:check_shared_dpll_state] WRPLL 2
> [  320.187657] [drm:check_encoder_state] [ENCODER:32:DAC-32]
> [  320.187660] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
> [  320.187662] [drm:check_encoder_state] [ENCODER:41:TMDS-41]
> [  320.187664] [drm:check_crtc_state] [CRTC:21]
> [  320.187667] [drm:check_crtc_state] [CRTC:25]
> [  320.187669] [drm:check_crtc_state] [CRTC:29]
> [  320.187671] [drm:check_shared_dpll_state] WRPLL 1
> [  320.187673] [drm:check_shared_dpll_state] WRPLL 2
> [  320.187712] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/976
> [  320.187784] [drm:drm_mode_setcrtc] [CRTC:21]
> [  320.187792] [drm:drm_mode_setcrtc] [CONNECTOR:34:eDP-1]
> [  320.187794] [drm:intel_crtc_set_config] [CRTC:21] [FB:45] #connectors=1 (x y) (0 0)
> [  320.187799] [drm:intel_modeset_stage_output_state] [CONNECTOR:34:eDP-1] to [CRTC:21]
> [  320.187807] [drm:connected_sink_compute_bpp] [CONNECTOR:34:eDP-1] checking for sink bpp constrains
> [  320.187809] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 18
> [  320.187812] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 143000KHz
> [  320.187814] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
> [  320.187816] [drm:intel_dp_compute_config] DP link bw required 257400 available 432000
> [  320.187818] [drm:intel_modeset_pipe_config] plane bpp: 36, pipe bpp: 18, dithering: 1
> [  320.187820] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff88040b881c00 for pipe A
> [  320.187822] [drm:intel_dump_pipe_config] cpu_transcoder: D
> [  320.187823] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
> [  320.187825] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
> [  320.187827] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4998212, gmch_n: 8388608, link_m: 277678, link_n: 524288, tu: 64
> [  320.187829] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
> [  320.187830] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
> [  320.187831] [drm:intel_dump_pipe_config] requested mode:
> [  320.187834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 143000 1920 1968 2000 2080 1080 1082 1087 1144 0x0 0xa
> [  320.187835] [drm:intel_dump_pipe_config] adjusted mode:
> [  320.187837] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 143000 1920 1968 2000 2080 1080 1082 1087 1144 0x48 0xa
> [  320.187840] [drm:intel_dump_crtc_timings] crtc timings: 143000 1920 1968 2000 2080 1080 1082 1087 1144, type: 0x48 flags: 0xa
> [  320.187841] [drm:intel_dump_pipe_config] port clock: 270000
> [  320.187842] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
> [  320.187844] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
> [  320.187846] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
> [  320.187847] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
> [  320.187849] [drm:intel_dump_pipe_config] ips: 0
> [  320.187850] [drm:intel_dump_pipe_config] double wide: 0
> [  320.187851] [drm:intel_dump_pipe_config] ddi_pll_sel: 536870912; dpll_hw_state: wrpll: 0x0
> [  320.187853] [drm:intel_dump_pipe_config] planes on this crtc
> [  320.187854] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 enabled
> [  320.187856] [drm:intel_dump_pipe_config] 	FB:45, fb = 1920x1080 format = 0x34325258
> [  320.187858] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 0x0 dst (0, 0) 0x0
> [  320.187860] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 disabled, scaler_id = 0
> [  320.187862] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = 0
> [  320.187898] [drm:edp_panel_on] Turn eDP port A panel power on
> [  320.187902] [drm:wait_panel_power_cycle] Wait for panel power cycle
> [  320.729710] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
> [  320.729716] [drm:wait_panel_status] Wait complete
> [  320.729722] [drm:wait_panel_on] Wait for panel power on
> [  320.729726] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
> [  320.930809] [drm:wait_panel_status] Wait complete
> [  320.930828] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
> [  320.930838] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
> [  320.932056] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
> [  320.932058] [drm:intel_dp_set_signal_levels] Using vswing level 0
> [  320.932060] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
> [  320.932758] [drm:intel_dp_start_link_train] clock recovery OK
> [  320.933750] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
> [  320.933871] [drm:intel_enable_pipe] enabling pipe A
> [  320.934063] [drm:intel_edp_backlight_on] 
> [  320.934066] [drm:intel_panel_enable_backlight] pipe A
> [  320.934072] [drm:intel_panel_actually_set_backlight] set backlight PWM = 976
> [  321.013306] [drm:intel_psr_enable] PSR not supported by this panel
> [  321.013308] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
> [  321.017360] [drm:intel_connector_check_state] [CONNECTOR:34:eDP-1]
> [  321.017369] [drm:check_encoder_state] [ENCODER:32:DAC-32]
> [  321.017372] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
> [  321.017375] [drm:check_encoder_state] [ENCODER:41:TMDS-41]
> [  321.017377] [drm:check_crtc_state] [CRTC:21]
> [  321.017391] [drm:check_crtc_state] [CRTC:25]
> [  321.017393] [drm:check_crtc_state] [CRTC:29]
> [  321.017395] [drm:check_shared_dpll_state] WRPLL 1
> [  321.017398] [drm:check_shared_dpll_state] WRPLL 2
> [  321.017503] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=48/976
> [  321.017508] [drm:intel_panel_actually_set_backlight] set backlight PWM = 66
> [  323.943206] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
> [  323.943216] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
> [  324.433936] [drm:connected_sink_compute_bpp] [CONNECTOR:34:eDP-1] checking for sink bpp constrains
> [  324.433941] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 18
> [  324.433945] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 143000KHz
> [  324.433947] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
> [  324.433949] [drm:intel_dp_compute_config] DP link bw required 257400 available 432000
> [  324.433952] [drm:intel_modeset_pipe_config] plane bpp: 36, pipe bpp: 18, dithering: 1
> [  324.433954] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff88041719dc00 for pipe A
> [  324.433955] [drm:intel_dump_pipe_config] cpu_transcoder: D
> [  324.433956] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
> [  324.433958] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
> [  324.433960] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4998212, gmch_n: 8388608, link_m: 277678, link_n: 524288, tu: 64
> [  324.433962] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
> [  324.433963] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
> [  324.433965] [drm:intel_dump_pipe_config] requested mode:
> [  324.433968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 143000 1920 1968 2000 2080 1080 1082 1087 1144 0x0 0xa
> [  324.433969] [drm:intel_dump_pipe_config] adjusted mode:
> [  324.433971] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 143000 1920 1968 2000 2080 1080 1082 1087 1144 0x48 0xa
> [  324.433973] [drm:intel_dump_crtc_timings] crtc timings: 143000 1920 1968 2000 2080 1080 1082 1087 1144, type: 0x48 flags: 0xa
> [  324.433975] [drm:intel_dump_pipe_config] port clock: 270000
> [  324.433976] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
> [  324.433978] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
> [  324.433979] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
> [  324.433981] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
> [  324.433982] [drm:intel_dump_pipe_config] ips: 0
> [  324.433983] [drm:intel_dump_pipe_config] double wide: 0
> [  324.433985] [drm:intel_dump_pipe_config] ddi_pll_sel: 536870912; dpll_hw_state: wrpll: 0x0
> [  324.433986] [drm:intel_dump_pipe_config] planes on this crtc
> [  324.433988] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 enabled
> [  324.433990] [drm:intel_dump_pipe_config] 	FB:45, fb = 1920x1080 format = 0x34325258
> [  324.433992] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 1920x1080 dst (0, 0) 1920x1080
> [  324.433994] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 enabled
> [  324.433996] [drm:intel_dump_pipe_config] 	FB:47, fb = 64x64 format = 0x34325241
> [  324.433998] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 64x64 dst (834, 885) 64x64
> [  324.434000] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = 0
> [  324.434026] [drm:intel_edp_backlight_off] 
> [  324.637337] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
> [  324.637357] [drm:intel_disable_pipe] disabling pipe A
> [  324.649034] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
> [  324.649046] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
> [  324.649281] [drm:edp_panel_off] Turn eDP port A panel power off
> [  324.649288] [drm:wait_panel_off] Wait for panel power off time
> [  324.649293] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control abcd0000
> [  324.700885] [drm:wait_panel_status] Wait complete
> [  324.700937] [drm:check_encoder_state] [ENCODER:32:DAC-32]
> [  324.700940] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
> [  324.700943] [drm:check_encoder_state] [ENCODER:41:TMDS-41]
> [  324.700945] [drm:check_crtc_state] [CRTC:21]
> [  324.700949] [drm:check_crtc_state] [CRTC:25]
> [  324.700951] [drm:check_crtc_state] [CRTC:29]
> [  324.700953] [drm:check_shared_dpll_state] WRPLL 1
> [  324.700956] [drm:check_shared_dpll_state] WRPLL 2
> [  324.700962] [drm:check_encoder_state] [ENCODER:32:DAC-32]
> [  324.700964] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
> [  324.700966] [drm:check_encoder_state] [ENCODER:41:TMDS-41]
> [  324.700968] [drm:check_crtc_state] [CRTC:21]
> [  324.700972] [drm:check_crtc_state] [CRTC:25]
> [  324.700973] [drm:check_crtc_state] [CRTC:29]
> [  324.700975] [drm:check_shared_dpll_state] WRPLL 1
> [  324.700977] [drm:check_shared_dpll_state] WRPLL 2
> [  324.701016] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/976
> [  324.701086] [drm:drm_mode_setcrtc] [CRTC:21]
> [  324.701093] [drm:drm_mode_setcrtc] [CONNECTOR:34:eDP-1]
> [  324.701095] [drm:intel_crtc_set_config] [CRTC:21] [FB:45] #connectors=1 (x y) (0 0)
> [  324.701101] [drm:intel_modeset_stage_output_state] [CONNECTOR:34:eDP-1] to [CRTC:21]
> [  324.701109] [drm:connected_sink_compute_bpp] [CONNECTOR:34:eDP-1] checking for sink bpp constrains
> [  324.701111] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 18
> [  324.701114] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 143000KHz
> [  324.701116] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
> [  324.701118] [drm:intel_dp_compute_config] DP link bw required 257400 available 432000
> [  324.701120] [drm:intel_modeset_pipe_config] plane bpp: 36, pipe bpp: 18, dithering: 1
> [  324.701122] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff88041719dc00 for pipe A
> [  324.701124] [drm:intel_dump_pipe_config] cpu_transcoder: D
> [  324.701125] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
> [  324.701127] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
> [  324.701129] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4998212, gmch_n: 8388608, link_m: 277678, link_n: 524288, tu: 64
> [  324.701131] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
> [  324.701132] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
> [  324.701134] [drm:intel_dump_pipe_config] requested mode:
> [  324.701136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 143000 1920 1968 2000 2080 1080 1082 1087 1144 0x0 0xa
> [  324.701138] [drm:intel_dump_pipe_config] adjusted mode:
> [  324.701140] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 143000 1920 1968 2000 2080 1080 1082 1087 1144 0x48 0xa
> [  324.701142] [drm:intel_dump_crtc_timings] crtc timings: 143000 1920 1968 2000 2080 1080 1082 1087 1144, type: 0x48 flags: 0xa
> [  324.701143] [drm:intel_dump_pipe_config] port clock: 270000
> [  324.701145] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
> [  324.701146] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
> [  324.701148] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
> [  324.701150] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
> [  324.701151] [drm:intel_dump_pipe_config] ips: 0
> [  324.701152] [drm:intel_dump_pipe_config] double wide: 0
> [  324.701154] [drm:intel_dump_pipe_config] ddi_pll_sel: 536870912; dpll_hw_state: wrpll: 0x0
> [  324.701155] [drm:intel_dump_pipe_config] planes on this crtc
> [  324.701157] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 enabled
> [  324.701159] [drm:intel_dump_pipe_config] 	FB:45, fb = 1920x1080 format = 0x34325258
> [  324.701161] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 0x0 dst (0, 0) 0x0
> [  324.701162] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 disabled, scaler_id = 0
> [  324.701164] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = 0
> [  324.701201] [drm:edp_panel_on] Turn eDP port A panel power on
> [  324.701205] [drm:wait_panel_power_cycle] Wait for panel power cycle
> [  325.251348] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
> [  325.251354] [drm:wait_panel_status] Wait complete
> [  325.251360] [drm:wait_panel_on] Wait for panel power on
> [  325.251364] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
> [  325.472019] [drm:wait_panel_status] Wait complete
> [  325.472039] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
> [  325.472048] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
> [  325.473280] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
> [  325.473284] [drm:intel_dp_set_signal_levels] Using vswing level 0
> [  325.473286] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
> [  325.473994] [drm:intel_dp_start_link_train] clock recovery OK
> [  325.474988] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
> [  325.475102] [drm:intel_enable_pipe] enabling pipe A
> [  325.475284] [drm:intel_edp_backlight_on] 
> [  325.475287] [drm:intel_panel_enable_backlight] pipe A
> [  325.475293] [drm:intel_panel_actually_set_backlight] set backlight PWM = 976
> [  325.555017] [drm:intel_psr_enable] PSR not supported by this panel
> [  325.555022] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
> [  325.558569] [drm:intel_connector_check_state] [CONNECTOR:34:eDP-1]
> [  325.558578] [drm:check_encoder_state] [ENCODER:32:DAC-32]
> [  325.558581] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
> [  325.558584] [drm:check_encoder_state] [ENCODER:41:TMDS-41]
> [  325.558586] [drm:check_crtc_state] [CRTC:21]
> [  325.558600] [drm:check_crtc_state] [CRTC:25]
> [  325.558602] [drm:check_crtc_state] [CRTC:29]
> [  325.558604] [drm:check_shared_dpll_state] WRPLL 1
> [  325.558607] [drm:check_shared_dpll_state] WRPLL 2
> [  325.558706] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=48/976
> [  325.558711] [drm:intel_panel_actually_set_backlight] set backlight PWM = 66
> [  326.464615] [drm:connected_sink_compute_bpp] [CONNECTOR:34:eDP-1] checking for sink bpp constrains
> [  326.464620] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 18
> [  326.464624] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 143000KHz
> [  326.464626] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
> [  326.464628] [drm:intel_dp_compute_config] DP link bw required 257400 available 432000
> [  326.464631] [drm:intel_modeset_pipe_config] plane bpp: 36, pipe bpp: 18, dithering: 1
> [  326.464633] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff88041719a000 for pipe A
> [  326.464634] [drm:intel_dump_pipe_config] cpu_transcoder: D
> [  326.464635] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
> [  326.464637] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
> [  326.464639] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4998212, gmch_n: 8388608, link_m: 277678, link_n: 524288, tu: 64
> [  326.464641] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
> [  326.464643] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
> [  326.464644] [drm:intel_dump_pipe_config] requested mode:
> [  326.464647] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 143000 1920 1968 2000 2080 1080 1082 1087 1144 0x0 0xa
> [  326.464648] [drm:intel_dump_pipe_config] adjusted mode:
> [  326.464650] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 143000 1920 1968 2000 2080 1080 1082 1087 1144 0x48 0xa
> [  326.464652] [drm:intel_dump_crtc_timings] crtc timings: 143000 1920 1968 2000 2080 1080 1082 1087 1144, type: 0x48 flags: 0xa
> [  326.464654] [drm:intel_dump_pipe_config] port clock: 270000
> [  326.464655] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
> [  326.464657] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
> [  326.464658] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
> [  326.464660] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
> [  326.464661] [drm:intel_dump_pipe_config] ips: 0
> [  326.464663] [drm:intel_dump_pipe_config] double wide: 0
> [  326.464664] [drm:intel_dump_pipe_config] ddi_pll_sel: 536870912; dpll_hw_state: wrpll: 0x0
> [  326.464665] [drm:intel_dump_pipe_config] planes on this crtc
> [  326.464667] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 enabled
> [  326.464669] [drm:intel_dump_pipe_config] 	FB:45, fb = 1920x1080 format = 0x34325258
> [  326.464671] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 1920x1080 dst (0, 0) 1920x1080
> [  326.464673] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 enabled
> [  326.464674] [drm:intel_dump_pipe_config] 	FB:47, fb = 64x64 format = 0x34325241
> [  326.464676] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 64x64 dst (834, 885) 64x64
> [  326.464678] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = 0
> [  326.464706] [drm:intel_edp_backlight_off] 
> [  326.666224] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
> [  326.666244] [drm:intel_disable_pipe] disabling pipe A
> [  326.676074] [drm:edp_panel_off] Turn eDP port A panel power off
> [  326.676082] [drm:wait_panel_off] Wait for panel power off time
> [  326.676087] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
> [  326.736419] [drm:wait_panel_status] Wait complete
> [  326.736469] [drm:check_encoder_state] [ENCODER:32:DAC-32]
> [  326.736472] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
> [  326.736475] [drm:check_encoder_state] [ENCODER:41:TMDS-41]
> [  326.736477] [drm:check_crtc_state] [CRTC:21]
> [  326.736481] [drm:check_crtc_state] [CRTC:25]
> [  326.736483] [drm:check_crtc_state] [CRTC:29]
> [  326.736485] [drm:check_shared_dpll_state] WRPLL 1
> [  326.736488] [drm:check_shared_dpll_state] WRPLL 2
> [  326.736494] [drm:check_encoder_state] [ENCODER:32:DAC-32]
> [  326.736496] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
> [  326.736499] [drm:check_encoder_state] [ENCODER:41:TMDS-41]
> [  326.736501] [drm:check_crtc_state] [CRTC:21]
> [  326.736504] [drm:check_crtc_state] [CRTC:25]
> [  326.736506] [drm:check_crtc_state] [CRTC:29]
> [  326.736508] [drm:check_shared_dpll_state] WRPLL 1
> [  326.736510] [drm:check_shared_dpll_state] WRPLL 2
> [  326.736549] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/976
> [  326.736617] [drm:drm_mode_setcrtc] [CRTC:21]
> [  326.736624] [drm:drm_mode_setcrtc] [CONNECTOR:34:eDP-1]
> [  326.736627] [drm:intel_crtc_set_config] [CRTC:21] [FB:45] #connectors=1 (x y) (0 0)
> [  326.736632] [drm:intel_modeset_stage_output_state] [CONNECTOR:34:eDP-1] to [CRTC:21]
> [  326.736640] [drm:connected_sink_compute_bpp] [CONNECTOR:34:eDP-1] checking for sink bpp constrains
> [  326.736642] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 18
> [  326.736645] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 143000KHz
> [  326.736647] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
> [  326.736649] [drm:intel_dp_compute_config] DP link bw required 257400 available 432000
> [  326.736651] [drm:intel_modeset_pipe_config] plane bpp: 36, pipe bpp: 18, dithering: 1
> [  326.736653] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff88040b880000 for pipe A
> [  326.736655] [drm:intel_dump_pipe_config] cpu_transcoder: D
> [  326.736656] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
> [  326.736658] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
> [  326.736660] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4998212, gmch_n: 8388608, link_m: 277678, link_n: 524288, tu: 64
> [  326.736662] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
> [  326.736663] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
> [  326.736664] [drm:intel_dump_pipe_config] requested mode:
> [  326.736667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 143000 1920 1968 2000 2080 1080 1082 1087 1144 0x0 0xa
> [  326.736668] [drm:intel_dump_pipe_config] adjusted mode:
> [  326.736670] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 143000 1920 1968 2000 2080 1080 1082 1087 1144 0x48 0xa
> [  326.736673] [drm:intel_dump_crtc_timings] crtc timings: 143000 1920 1968 2000 2080 1080 1082 1087 1144, type: 0x48 flags: 0xa
> [  326.736674] [drm:intel_dump_pipe_config] port clock: 270000
> [  326.736675] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
> [  326.736677] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
> [  326.736679] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
> [  326.736680] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
> [  326.736682] [drm:intel_dump_pipe_config] ips: 0
> [  326.736683] [drm:intel_dump_pipe_config] double wide: 0
> [  326.736684] [drm:intel_dump_pipe_config] ddi_pll_sel: 536870912; dpll_hw_state: wrpll: 0x0
> [  326.736686] [drm:intel_dump_pipe_config] planes on this crtc
> [  326.736687] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 enabled
> [  326.736689] [drm:intel_dump_pipe_config] 	FB:45, fb = 1920x1080 format = 0x34325258
> [  326.736691] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 0x0 dst (0, 0) 0x0
> [  326.736693] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 disabled, scaler_id = 0
> [  326.736695] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = 0
> [  326.736732] [drm:edp_panel_on] Turn eDP port A panel power on
> [  326.736736] [drm:wait_panel_power_cycle] Wait for panel power cycle
> [  327.276903] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
> [  327.276908] [drm:wait_panel_status] Wait complete
> [  327.276914] [drm:wait_panel_on] Wait for panel power on
> [  327.276919] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
> [  327.497467] [drm:wait_panel_status] Wait complete
> [  327.497487] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
> [  327.497497] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
> [  327.498727] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
> [  327.498731] [drm:intel_dp_set_signal_levels] Using vswing level 0
> [  327.498733] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
> [  327.499434] [drm:intel_dp_start_link_train] clock recovery OK
> [  327.500433] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
> [  327.500566] [drm:intel_enable_pipe] enabling pipe A
> [  327.500748] [drm:intel_edp_backlight_on] 
> [  327.500751] [drm:intel_panel_enable_backlight] pipe A
> [  327.500757] [drm:intel_panel_actually_set_backlight] set backlight PWM = 976
> [  327.580514] [drm:intel_psr_enable] PSR not supported by this panel
> [  327.580516] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
> [  327.583996] [drm:intel_connector_check_state] [CONNECTOR:34:eDP-1]
> [  327.584006] [drm:check_encoder_state] [ENCODER:32:DAC-32]
> [  327.584010] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
> [  327.584013] [drm:check_encoder_state] [ENCODER:41:TMDS-41]
> [  327.584016] [drm:check_crtc_state] [CRTC:21]
> [  327.584029] [drm:check_crtc_state] [CRTC:25]
> [  327.584031] [drm:check_crtc_state] [CRTC:29]
> [  327.584033] [drm:check_shared_dpll_state] WRPLL 1
> [  327.584036] [drm:check_shared_dpll_state] WRPLL 2
> [  327.584126] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=48/976
> [  327.584130] [drm:intel_panel_actually_set_backlight] set backlight PWM = 66
> [  330.510468] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
> [  330.510479] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
> [  346.857939] [drm:connected_sink_compute_bpp] [CONNECTOR:34:eDP-1] checking for sink bpp constrains
> [  346.857944] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 18
> [  346.857948] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 143000KHz
> [  346.857950] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
> [  346.857951] [drm:intel_dp_compute_config] DP link bw required 257400 available 432000
> [  346.857954] [drm:intel_modeset_pipe_config] plane bpp: 36, pipe bpp: 18, dithering: 1
> [  346.857956] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff8800c6fe3000 for pipe A
> [  346.857957] [drm:intel_dump_pipe_config] cpu_transcoder: D
> [  346.857959] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
> [  346.857961] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
> [  346.857963] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4998212, gmch_n: 8388608, link_m: 277678, link_n: 524288, tu: 64
> [  346.857965] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
> [  346.857966] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
> [  346.857967] [drm:intel_dump_pipe_config] requested mode:
> [  346.857970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 143000 1920 1968 2000 2080 1080 1082 1087 1144 0x0 0xa
> [  346.857972] [drm:intel_dump_pipe_config] adjusted mode:
> [  346.857974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 143000 1920 1968 2000 2080 1080 1082 1087 1144 0x48 0xa
> [  346.857976] [drm:intel_dump_crtc_timings] crtc timings: 143000 1920 1968 2000 2080 1080 1082 1087 1144, type: 0x48 flags: 0xa
> [  346.857977] [drm:intel_dump_pipe_config] port clock: 270000
> [  346.857979] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
> [  346.857980] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
> [  346.857982] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
> [  346.857984] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
> [  346.857985] [drm:intel_dump_pipe_config] ips: 0
> [  346.857986] [drm:intel_dump_pipe_config] double wide: 0
> [  346.857988] [drm:intel_dump_pipe_config] ddi_pll_sel: 536870912; dpll_hw_state: wrpll: 0x0
> [  346.857989] [drm:intel_dump_pipe_config] planes on this crtc
> [  346.857991] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 enabled
> [  346.857993] [drm:intel_dump_pipe_config] 	FB:45, fb = 1920x1080 format = 0x34325258
> [  346.857995] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 1920x1080 dst (0, 0) 1920x1080
> [  346.857997] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 enabled
> [  346.857998] [drm:intel_dump_pipe_config] 	FB:47, fb = 64x64 format = 0x34325241
> [  346.858000] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 64x64 dst (841, 853) 64x64
> [  346.858002] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = 0
> [  346.858030] [drm:intel_edp_backlight_off] 
> [  347.058632] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
> [  347.058653] [drm:intel_disable_pipe] disabling pipe A
> [  347.074509] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
> [  347.074521] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
> [  347.074752] [drm:edp_panel_off] Turn eDP port A panel power off
> [  347.074759] [drm:wait_panel_off] Wait for panel power off time
> [  347.074764] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
> [  347.135094] [drm:wait_panel_status] Wait complete
> [  347.135144] [drm:check_encoder_state] [ENCODER:32:DAC-32]
> [  347.135148] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
> [  347.135150] [drm:check_encoder_state] [ENCODER:41:TMDS-41]
> [  347.135153] [drm:check_crtc_state] [CRTC:21]
> [  347.135157] [drm:check_crtc_state] [CRTC:25]
> [  347.135159] [drm:check_crtc_state] [CRTC:29]
> [  347.135161] [drm:check_shared_dpll_state] WRPLL 1
> [  347.135164] [drm:check_shared_dpll_state] WRPLL 2
> [  347.135170] [drm:check_encoder_state] [ENCODER:32:DAC-32]
> [  347.135172] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
> [  347.135174] [drm:check_encoder_state] [ENCODER:41:TMDS-41]
> [  347.135176] [drm:check_crtc_state] [CRTC:21]
> [  347.135180] [drm:check_crtc_state] [CRTC:25]
> [  347.135181] [drm:check_crtc_state] [CRTC:29]
> [  347.135183] [drm:check_shared_dpll_state] WRPLL 1
> [  347.135185] [drm:check_shared_dpll_state] WRPLL 2
> [  347.135224] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/976
> [  356.006081] [drm:drm_mode_setcrtc] [CRTC:21]
> [  356.006092] [drm:drm_mode_setcrtc] [CONNECTOR:34:eDP-1]
> [  356.006095] [drm:intel_crtc_set_config] [CRTC:21] [FB:45] #connectors=1 (x y) (0 0)
> [  356.006101] [drm:intel_modeset_stage_output_state] [CONNECTOR:34:eDP-1] to [CRTC:21]
> [  356.006110] [drm:connected_sink_compute_bpp] [CONNECTOR:34:eDP-1] checking for sink bpp constrains
> [  356.006112] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 18
> [  356.006115] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 143000KHz
> [  356.006118] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
> [  356.006119] [drm:intel_dp_compute_config] DP link bw required 257400 available 432000
> [  356.006122] [drm:intel_modeset_pipe_config] plane bpp: 36, pipe bpp: 18, dithering: 1
> [  356.006124] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff88040b883000 for pipe A
> [  356.006125] [drm:intel_dump_pipe_config] cpu_transcoder: D
> [  356.006127] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
> [  356.006129] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
> [  356.006131] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4998212, gmch_n: 8388608, link_m: 277678, link_n: 524288, tu: 64
> [  356.006133] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
> [  356.006134] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
> [  356.006135] [drm:intel_dump_pipe_config] requested mode:
> [  356.006138] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 143000 1920 1968 2000 2080 1080 1082 1087 1144 0x0 0xa
> [  356.006139] [drm:intel_dump_pipe_config] adjusted mode:
> [  356.006142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 143000 1920 1968 2000 2080 1080 1082 1087 1144 0x48 0xa
> [  356.006144] [drm:intel_dump_crtc_timings] crtc timings: 143000 1920 1968 2000 2080 1080 1082 1087 1144, type: 0x48 flags: 0xa
> [  356.006145] [drm:intel_dump_pipe_config] port clock: 270000
> [  356.006146] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
> [  356.006148] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
> [  356.006150] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
> [  356.006151] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
> [  356.006153] [drm:intel_dump_pipe_config] ips: 0
> [  356.006154] [drm:intel_dump_pipe_config] double wide: 0
> [  356.006155] [drm:intel_dump_pipe_config] ddi_pll_sel: 536870912; dpll_hw_state: wrpll: 0x0
> [  356.006157] [drm:intel_dump_pipe_config] planes on this crtc
> [  356.006158] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 enabled
> [  356.006160] [drm:intel_dump_pipe_config] 	FB:45, fb = 1920x1080 format = 0x34325258
> [  356.006162] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 0x0 dst (0, 0) 0x0
> [  356.006164] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 disabled, scaler_id = 0
> [  356.006166] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = 0
> [  356.006204] [drm:edp_panel_on] Turn eDP port A panel power on
> [  356.006208] [drm:wait_panel_power_cycle] Wait for panel power cycle
> [  356.006212] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
> [  356.006215] [drm:wait_panel_status] Wait complete
> [  356.006219] [drm:wait_panel_on] Wait for panel power on
> [  356.006224] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
> [  356.207133] [drm:wait_panel_status] Wait complete
> [  356.207153] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
> [  356.207163] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
> [  356.208372] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
> [  356.208375] [drm:intel_dp_set_signal_levels] Using vswing level 0
> [  356.208376] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
> [  356.209127] [drm:intel_dp_start_link_train] clock recovery OK
> [  356.210124] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
> [  356.210252] [drm:intel_enable_pipe] enabling pipe A
> [  356.210467] [drm:intel_edp_backlight_on] 
> [  356.210470] [drm:intel_panel_enable_backlight] pipe A
> [  356.210475] [drm:intel_panel_actually_set_backlight] set backlight PWM = 976
> [  356.288794] [drm:intel_psr_enable] PSR not supported by this panel
> [  356.288799] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
> [  356.293734] [drm:intel_connector_check_state] [CONNECTOR:34:eDP-1]
> [  356.293743] [drm:check_encoder_state] [ENCODER:32:DAC-32]
> [  356.293745] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
> [  356.293748] [drm:check_encoder_state] [ENCODER:41:TMDS-41]
> [  356.293751] [drm:check_crtc_state] [CRTC:21]
> [  356.293765] [drm:check_crtc_state] [CRTC:25]
> [  356.293767] [drm:check_crtc_state] [CRTC:29]
> [  356.293769] [drm:check_shared_dpll_state] WRPLL 1
> [  356.293772] [drm:check_shared_dpll_state] WRPLL 2
> [  356.294908] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=48/976
> [  356.294912] [drm:intel_panel_actually_set_backlight] set backlight PWM = 66
> [  359.215327] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
> [  359.215339] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
> 
> 
> 	-ss

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch