From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 23/24] target/arm: Fix typos in trans function prototypes
Date: Mon, 17 Jun 2019 15:34:11 +0100 [thread overview]
Message-ID: <20190617143412.5734-24-peter.maydell@linaro.org> (raw)
In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org>
In several places cut and paste errors meant we were using the wrong
type for the 'arg' struct in trans_ functions called by the
decodetree decoder, because we were using the _sp version of the
struct in the _dp function. These were harmless, because the two
structs were identical and so decodetree made them typedefs of the
same underlying structure (and we'd have had a compile error if they
were not harmless), but we should clean them up anyway.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190614104457.24703-2-peter.maydell@linaro.org
---
target/arm/translate-vfp.inc.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 8b732761f26..390441a1104 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -868,7 +868,7 @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a)
return true;
}
-static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_sp *a)
+static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a)
{
TCGv_i32 tmp;
@@ -943,7 +943,7 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
return true;
}
-static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_sp *a)
+static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
{
uint32_t offset;
TCGv_i32 addr;
@@ -1533,7 +1533,7 @@ static void gen_VMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
tcg_temp_free_i64(tmp);
}
-static bool trans_VMLA_dp(DisasContext *s, arg_VMLA_sp *a)
+static bool trans_VMLA_dp(DisasContext *s, arg_VMLA_dp *a)
{
return do_vfp_3op_dp(s, gen_VMLA_dp, a->vd, a->vn, a->vm, true);
}
@@ -1571,7 +1571,7 @@ static void gen_VMLS_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
tcg_temp_free_i64(tmp);
}
-static bool trans_VMLS_dp(DisasContext *s, arg_VMLS_sp *a)
+static bool trans_VMLS_dp(DisasContext *s, arg_VMLS_dp *a)
{
return do_vfp_3op_dp(s, gen_VMLS_dp, a->vd, a->vn, a->vm, true);
}
@@ -1613,7 +1613,7 @@ static void gen_VNMLS_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
tcg_temp_free_i64(tmp);
}
-static bool trans_VNMLS_dp(DisasContext *s, arg_VNMLS_sp *a)
+static bool trans_VNMLS_dp(DisasContext *s, arg_VNMLS_dp *a)
{
return do_vfp_3op_dp(s, gen_VNMLS_dp, a->vd, a->vn, a->vm, true);
}
@@ -1647,7 +1647,7 @@ static void gen_VNMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
tcg_temp_free_i64(tmp);
}
-static bool trans_VNMLA_dp(DisasContext *s, arg_VNMLA_sp *a)
+static bool trans_VNMLA_dp(DisasContext *s, arg_VNMLA_dp *a)
{
return do_vfp_3op_dp(s, gen_VNMLA_dp, a->vd, a->vn, a->vm, true);
}
@@ -1657,7 +1657,7 @@ static bool trans_VMUL_sp(DisasContext *s, arg_VMUL_sp *a)
return do_vfp_3op_sp(s, gen_helper_vfp_muls, a->vd, a->vn, a->vm, false);
}
-static bool trans_VMUL_dp(DisasContext *s, arg_VMUL_sp *a)
+static bool trans_VMUL_dp(DisasContext *s, arg_VMUL_dp *a)
{
return do_vfp_3op_dp(s, gen_helper_vfp_muld, a->vd, a->vn, a->vm, false);
}
@@ -1681,7 +1681,7 @@ static void gen_VNMUL_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
gen_helper_vfp_negd(vd, vd);
}
-static bool trans_VNMUL_dp(DisasContext *s, arg_VNMUL_sp *a)
+static bool trans_VNMUL_dp(DisasContext *s, arg_VNMUL_dp *a)
{
return do_vfp_3op_dp(s, gen_VNMUL_dp, a->vd, a->vn, a->vm, false);
}
@@ -1691,7 +1691,7 @@ static bool trans_VADD_sp(DisasContext *s, arg_VADD_sp *a)
return do_vfp_3op_sp(s, gen_helper_vfp_adds, a->vd, a->vn, a->vm, false);
}
-static bool trans_VADD_dp(DisasContext *s, arg_VADD_sp *a)
+static bool trans_VADD_dp(DisasContext *s, arg_VADD_dp *a)
{
return do_vfp_3op_dp(s, gen_helper_vfp_addd, a->vd, a->vn, a->vm, false);
}
@@ -1701,7 +1701,7 @@ static bool trans_VSUB_sp(DisasContext *s, arg_VSUB_sp *a)
return do_vfp_3op_sp(s, gen_helper_vfp_subs, a->vd, a->vn, a->vm, false);
}
-static bool trans_VSUB_dp(DisasContext *s, arg_VSUB_sp *a)
+static bool trans_VSUB_dp(DisasContext *s, arg_VSUB_dp *a)
{
return do_vfp_3op_dp(s, gen_helper_vfp_subd, a->vd, a->vn, a->vm, false);
}
@@ -1711,7 +1711,7 @@ static bool trans_VDIV_sp(DisasContext *s, arg_VDIV_sp *a)
return do_vfp_3op_sp(s, gen_helper_vfp_divs, a->vd, a->vn, a->vm, false);
}
-static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_sp *a)
+static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a)
{
return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false);
}
@@ -1774,7 +1774,7 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
return true;
}
-static bool trans_VFM_dp(DisasContext *s, arg_VFM_sp *a)
+static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
{
/*
* VFNMA : fd = muladd(-fd, fn, fm)
@@ -2214,7 +2214,7 @@ static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a)
return true;
}
-static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_sp *a)
+static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
{
TCGv_ptr fpst;
TCGv_i64 tmp;
@@ -2270,7 +2270,7 @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
return true;
}
-static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_sp *a)
+static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
{
TCGv_ptr fpst;
TCGv_i64 tmp;
--
2.20.1
next prev parent reply other threads:[~2019-06-17 15:10 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-17 14:33 [Qemu-devel] [PULL 00/24] target-arm queue Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 01/24] hw/arm/boot: Don't assume RAM starts at address zero Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 02/24] hw/arm/boot: Diagnose layouts that put initrd or DTB off the end of RAM Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 03/24] hw/arm/boot: Avoid placing the initrd on top of the kernel Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 04/24] hw/arm/boot: Honour image size field in AArch64 Image format kernels Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 05/24] target/arm: Allow VFP and Neon to be disabled via a CPU property Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 06/24] target/arm: Allow M-profile CPUs to disable the DSP extension via " Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 07/24] hw/arm/armv7m: Forward "vfp" and "dsp" properties to CPU Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 08/24] hw/arm: Correctly disable FPU/DSP for some ARMSSE-based boards Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 09/24] hw/intc/arm_gicv3: Fix decoding of ID register range Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 10/24] hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1 Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 11/24] target/arm: Move vfp_expand_imm() to translate.[ch] Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 12/24] target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 13/24] target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 14/24] target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_F Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 15/24] target/arm: Stop using cpu_F0s for NEON_2RM_VRINT* Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 16/24] target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US] Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 17/24] target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 18/24] target/arm: Stop using cpu_F0s for Neon f32/s32 VCVT Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 19/24] target/arm: Stop using cpu_F0s in Neon VCVT fixed-point ops Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 20/24] target/arm: stop using deprecated functions in NEON_2RM_VCVT_F16_F32 Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 21/24] target/arm: Stop using deprecated functions in NEON_2RM_VCVT_F32_F16 Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 22/24] target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d Peter Maydell
2019-06-17 14:34 ` Peter Maydell [this message]
2019-06-17 14:34 ` [Qemu-devel] [PULL 24/24] target/arm: Only implement doubles if the FPU supports them Peter Maydell
2019-06-17 15:41 ` [Qemu-devel] [PULL 00/24] target-arm queue Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190617143412.5734-24-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.