From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 24/24] target/arm: Only implement doubles if the FPU supports them
Date: Mon, 17 Jun 2019 15:34:12 +0100 [thread overview]
Message-ID: <20190617143412.5734-25-peter.maydell@linaro.org> (raw)
In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org>
The architecture permits FPUs which have only single-precision
support, not double-precision; Cortex-M4 and Cortex-M33 are
both like that. Add the necessary checks on the MVFR0 FPDP
field so that we UNDEF any double-precision instructions on
CPUs like this.
Note that even if FPDP==0 the insns like VMOV-to/from-gpreg,
VLDM/VSTM, VLDR/VSTR which take double precision registers
still exist.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190614104457.24703-3-peter.maydell@linaro.org
---
target/arm/cpu.h | 6 +++
target/arm/translate-vfp.inc.c | 84 ++++++++++++++++++++++++++++++++++
2 files changed, 90 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a98c45b1ff0..f9da672be57 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3388,6 +3388,12 @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0;
}
+static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
+{
+ /* Return true if CPU supports double precision floating point */
+ return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0;
+}
+
/*
* We always set the FP and SIMD FP16 fields to indicate identical
* levels of support (assuming SIMD is implemented at all), so
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 390441a1104..348173d6026 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -206,6 +206,11 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}
+
+ if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
rd = a->vd;
rn = a->vn;
rm = a->vm;
@@ -334,6 +339,11 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}
+
+ if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
rd = a->vd;
rn = a->vn;
rm = a->vm;
@@ -415,6 +425,11 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
((a->vm | a->vd) & 0x10)) {
return false;
}
+
+ if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
rd = a->vd;
rm = a->vm;
@@ -473,6 +488,11 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
if (dp && !dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
return false;
}
+
+ if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
rd = a->vd;
rm = a->vm;
@@ -1301,6 +1321,10 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
return false;
}
+ if (!dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_fpshvec, s) &&
(veclen != 0 || s->vec_stride != 0)) {
return false;
@@ -1446,6 +1470,10 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
return false;
}
+ if (!dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_fpshvec, s) &&
(veclen != 0 || s->vec_stride != 0)) {
return false;
@@ -1743,6 +1771,10 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
return false;
}
+ if (!dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
@@ -1901,6 +1933,10 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
return false;
}
+ if (!dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_fpshvec, s) &&
(veclen != 0 || s->vec_stride != 0)) {
return false;
@@ -2041,6 +2077,10 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
return false;
}
+ if (!dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
@@ -2110,6 +2150,10 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
return false;
}
+ if (!dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
@@ -2172,6 +2216,10 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
return false;
}
+ if (!dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
@@ -2228,6 +2276,10 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
return false;
}
+ if (!dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
@@ -2285,6 +2337,10 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
return false;
}
+ if (!dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
@@ -2340,6 +2396,10 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
return false;
}
+ if (!dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
@@ -2364,6 +2424,10 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
return false;
}
+ if (!dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
@@ -2388,6 +2452,10 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
return false;
}
+ if (!dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
@@ -2438,6 +2506,10 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
return false;
}
+ if (!dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
@@ -2474,6 +2546,10 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
return false;
}
+ if (!dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
@@ -2563,6 +2639,10 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
return false;
}
+ if (!dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
@@ -2655,6 +2735,10 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
return false;
}
+ if (!dc_isar_feature(aa32_fpdp, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
--
2.20.1
next prev parent reply other threads:[~2019-06-17 14:57 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-17 14:33 [Qemu-devel] [PULL 00/24] target-arm queue Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 01/24] hw/arm/boot: Don't assume RAM starts at address zero Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 02/24] hw/arm/boot: Diagnose layouts that put initrd or DTB off the end of RAM Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 03/24] hw/arm/boot: Avoid placing the initrd on top of the kernel Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 04/24] hw/arm/boot: Honour image size field in AArch64 Image format kernels Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 05/24] target/arm: Allow VFP and Neon to be disabled via a CPU property Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 06/24] target/arm: Allow M-profile CPUs to disable the DSP extension via " Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 07/24] hw/arm/armv7m: Forward "vfp" and "dsp" properties to CPU Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 08/24] hw/arm: Correctly disable FPU/DSP for some ARMSSE-based boards Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 09/24] hw/intc/arm_gicv3: Fix decoding of ID register range Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 10/24] hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1 Peter Maydell
2019-06-17 14:33 ` [Qemu-devel] [PULL 11/24] target/arm: Move vfp_expand_imm() to translate.[ch] Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 12/24] target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 13/24] target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 14/24] target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_F Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 15/24] target/arm: Stop using cpu_F0s for NEON_2RM_VRINT* Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 16/24] target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US] Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 17/24] target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 18/24] target/arm: Stop using cpu_F0s for Neon f32/s32 VCVT Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 19/24] target/arm: Stop using cpu_F0s in Neon VCVT fixed-point ops Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 20/24] target/arm: stop using deprecated functions in NEON_2RM_VCVT_F16_F32 Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 21/24] target/arm: Stop using deprecated functions in NEON_2RM_VCVT_F32_F16 Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 22/24] target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d Peter Maydell
2019-06-17 14:34 ` [Qemu-devel] [PULL 23/24] target/arm: Fix typos in trans function prototypes Peter Maydell
2019-06-17 14:34 ` Peter Maydell [this message]
2019-06-17 15:41 ` [Qemu-devel] [PULL 00/24] target-arm queue Peter Maydell
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