From: Vladimir Oltean <olteanv@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH] pci: layerscape: Change to allocate zeroed memery for struct ls_pcie
Date: Tue, 16 Mar 2021 12:20:50 +0200 [thread overview]
Message-ID: <20210316102050.jsiu2fxvm4sdi7f6@skbuf> (raw)
In-Reply-To: <20210311073051.1548-1-Zhiqiang.Hou@nxp.com>
On Thu, Mar 11, 2021 at 03:30:51PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> As on some incipient Layerscape platforms (LS1043A series) there isn't
> separate PF control register block, these registers reside in the LUT
> register block, so when the driver detected there isn't 'ctrl', it will
> assign the 'lut' address to the ls_pcie->ctrl.
>
> The current code allocate memory for the struct ls_pcie with random
> contents, this can result in skipping to assign the ls_pcie->ctrl with
> the 'lut' address, then further crash with the incorrect address.
>
> Fixes: 118e58e26eba ("pci: layerscape: Split the EP and RC driver")
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
prev parent reply other threads:[~2021-03-16 10:20 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-11 7:30 [PATCH] pci: layerscape: Change to allocate zeroed memery for struct ls_pcie Zhiqiang Hou
2021-03-16 10:20 ` Vladimir Oltean [this message]
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