* [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver
@ 2021-04-13 5:09 Lucas De Marchi
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 01/12] drm/i915/display: use DISPLAY_VER() on remaining users Lucas De Marchi
` (17 more replies)
0 siblings, 18 replies; 39+ messages in thread
From: Lucas De Marchi @ 2021-04-13 5:09 UTC (permalink / raw)
To: intel-gfx
Like was done for the display part that parted ways with INTEL_GEN(),
replacing with DISPLAY_VER(), do a similar conversion for the rest of
the driver.
v1.1: Remove .ko that was incorrectly added as part of patch 11, making it
very big and not going through the mailing list. Sorry for those in CC
who received it.
v2:
- Add "drm/i915/display: rename display version macros" to rename
macro and repurpose it: s/IS_DISPLAY_RANGE/IS_DISPLAY_VER/ and convert
the current users of IS_DISPLAY_VER to use direct comparison
- Group display patches to easily apply independently
Lucas De Marchi (12):
drm/i915/display: use DISPLAY_VER() on remaining users
drm/i915: rename display.version to display.ver
drm/i915/display: rename display version macros
drm/i915: add macros for graphics and media versions
drm/i915/gt: replace gen use in intel_engine_cs
drm/i915/selftests: replace unused mask with simple version
drm/i915/selftests: eliminate use of gen_mask
drm/i915: finish removal of gen_mask
drm/i915: eliminate remaining uses of intel_device_info->gen
drm/i915: finish removal of gen from intel_device_info
drm/i915: add media and display versions to device_info print
drm/i915: split dgfx features from gen 12
drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
drivers/gpu/drm/i915/display/icl_dsi.c | 4 +-
drivers/gpu/drm/i915/display/intel_atomic.c | 2 +-
drivers/gpu/drm/i915/display/intel_audio.c | 4 +-
drivers/gpu/drm/i915/display/intel_bios.c | 4 +-
drivers/gpu/drm/i915/display/intel_bw.c | 8 +--
drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +++---
drivers/gpu/drm/i915/display/intel_color.c | 6 +-
drivers/gpu/drm/i915/display/intel_crt.c | 6 +-
drivers/gpu/drm/i915/display/intel_crtc.c | 4 +-
drivers/gpu/drm/i915/display/intel_csr.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 26 ++++-----
.../drm/i915/display/intel_ddi_buf_trans.c | 8 +--
drivers/gpu/drm/i915/display/intel_display.c | 56 +++++++++----------
.../drm/i915/display/intel_display_power.c | 26 ++++-----
drivers/gpu/drm/i915/display/intel_dp.c | 8 +--
drivers/gpu/drm/i915/display/intel_dpll.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 20 +++----
.../drm/i915/display/intel_fifo_underrun.c | 4 +-
drivers/gpu/drm/i915/display/intel_gmbus.c | 4 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 10 ++--
drivers/gpu/drm/i915/display/intel_panel.c | 8 +--
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 4 +-
drivers/gpu/drm/i915/display/intel_psr.c | 4 +-
drivers/gpu/drm/i915/display/intel_tc.c | 6 +-
drivers/gpu/drm/i915/display/intel_tv.c | 6 +-
.../drm/i915/display/skl_universal_plane.c | 8 +--
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 22 ++++----
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 40 ++++++-------
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 18 +++---
.../gpu/drm/i915/gt/selftest_workarounds.c | 10 ++--
drivers/gpu/drm/i915/i915_drv.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 41 ++++++++------
drivers/gpu/drm/i915/i915_irq.c | 10 ++--
drivers/gpu/drm/i915/i915_pci.c | 13 +++--
drivers/gpu/drm/i915/intel_device_info.c | 4 +-
drivers/gpu/drm/i915/intel_device_info.h | 6 +-
drivers/gpu/drm/i915/intel_pm.c | 48 ++++++++--------
drivers/gpu/drm/i915/intel_uncore.c | 8 ++-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 8 ++-
.../gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
46 files changed, 260 insertions(+), 246 deletions(-)
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH v2 01/12] drm/i915/display: use DISPLAY_VER() on remaining users
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
@ 2021-04-13 5:09 ` Lucas De Marchi
2021-04-13 9:24 ` Jani Nikula
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 02/12] drm/i915: rename display.version to display.ver Lucas De Marchi
` (16 subsequent siblings)
17 siblings, 1 reply; 39+ messages in thread
From: Lucas De Marchi @ 2021-04-13 5:09 UTC (permalink / raw)
To: intel-gfx
Commit 989634fb49ad ("drm/i915/audio: set HDA link parameters in driver")
added INTEL_GEN() in the display code, where it should actually be using
DISPLAY_VER(). Switch to the new macro.
Cc: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 9671c8f6e892..9fe3a25710b8 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -1309,7 +1309,7 @@ static void i915_audio_component_init(struct drm_i915_private *dev_priv)
if (DISPLAY_VER(dev_priv) >= 9) {
aud_freq_init = intel_de_read(dev_priv, AUD_FREQ_CNTRL);
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
aud_freq = AUD_FREQ_GEN12;
else
aud_freq = aud_freq_init;
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH v2 02/12] drm/i915: rename display.version to display.ver
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 01/12] drm/i915/display: use DISPLAY_VER() on remaining users Lucas De Marchi
@ 2021-04-13 5:09 ` Lucas De Marchi
2021-04-13 9:25 ` Jani Nikula
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 03/12] drm/i915/display: rename display version macros Lucas De Marchi
` (15 subsequent siblings)
17 siblings, 1 reply; 39+ messages in thread
From: Lucas De Marchi @ 2021-04-13 5:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
The macro we use to check is called DISPLAY_VER(). While using this
macro and the new ones being added in following changes I made the
mistake multiple times when mixing both "ver" and "version". Although
it's usually better to prefer the complete name, the shorhand
DISPLAY_VER() / GRAPHICS_VER / MEDIA_VER are clear and cause less
visual polution.
Another issue is when copying the variable to other places.
"display.version" would be copied to a "display_version" variable which
is long and would make people abbreviate as "version", or "display_ver".
In the first case it's not always clear what version refers to, and in
the second case it just hints it should be the name in the first place.
So, in the same way use used "gen" rather than "generation", use "ver"
instead of "version".
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 69e43bf91a15..8c62bb2abd31 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1237,7 +1237,7 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
#define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
-#define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.version)
+#define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
#define IS_DISPLAY_RANGE(i915, from, until) \
(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
#define IS_DISPLAY_VER(i915, v) (DISPLAY_VER(i915) == (v))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 480553746794..ce5cbeaf036d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -36,7 +36,7 @@
#include "i915_selftest.h"
#define PLATFORM(x) .platform = (x)
-#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1), .display.version = (x)
+#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1), .display.ver = (x)
#define I845_PIPE_OFFSETS \
.pipe_offsets = { \
@@ -723,7 +723,7 @@ static const struct intel_device_info bxt_info = {
static const struct intel_device_info glk_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_GEMINILAKE),
- .display.version = 10,
+ .display.ver = 10,
.ddb_size = 1024,
GLK_COLORS,
};
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 2f442d418a15..b16c75927a12 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -189,7 +189,7 @@ struct intel_device_info {
#undef DEFINE_FLAG
struct {
- u8 version;
+ u8 ver;
#define DEFINE_FLAG(name) u8 name:1
DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH v2 03/12] drm/i915/display: rename display version macros
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 01/12] drm/i915/display: use DISPLAY_VER() on remaining users Lucas De Marchi
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 02/12] drm/i915: rename display.version to display.ver Lucas De Marchi
@ 2021-04-13 5:09 ` Lucas De Marchi
2021-04-13 9:35 ` Jani Nikula
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 04/12] drm/i915: add macros for graphics and media versions Lucas De Marchi
` (14 subsequent siblings)
17 siblings, 1 reply; 39+ messages in thread
From: Lucas De Marchi @ 2021-04-13 5:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
While converting the rest of the driver to use GRAPHICS_VER() and
MEDIA_VER(), following what was done for display, some discussions went
back on what we did for display:
1) Why is the == comparison special that deserves a separate
macro instead of just getting the version and comparing directly
like is done for >, >=, <=?
2) IS_DISPLAY_RANGE() is weird in that it omits the "_VER" for
brevity. If we remove the current users of IS_DISPLAY_VER(), we
could actually repurpose it for a range check
With (1) there could be an advantage if we used gen_mask since multiple
conditionals be combined by the compiler in a single and instruction and
check the result. However a) INTEL_GEN() doesn't use the mask since it
would make the code bigger everywhere else and b) in the cases it made
sense, it also made sense to convert to the _RANGE() variant.
So here we repurpose IS_DISPLAY_VER() to work with a [ from, to ] range
like was the IS_DISPLAY_RANGE() and convert the current IS_DISPLAY_VER()
users to use == and != operators. Aside from the definition changes,
this was done by the following semantic patch:
@@ expression dev_priv, E1; @@
- !IS_DISPLAY_VER(dev_priv, E1)
+ DISPLAY_VER(dev_priv) != E1
@@ expression dev_priv, E1; @@
- IS_DISPLAY_VER(dev_priv, E1)
+ DISPLAY_VER(dev_priv) == E1
@@ expression dev_priv, from, until; @@
- IS_DISPLAY_RANGE(dev_priv, from, until)
+ IS_DISPLAY_VER(dev_priv, from, until)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
drivers/gpu/drm/i915/display/icl_dsi.c | 4 +-
drivers/gpu/drm/i915/display/intel_atomic.c | 2 +-
drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
drivers/gpu/drm/i915/display/intel_bios.c | 4 +-
drivers/gpu/drm/i915/display/intel_bw.c | 8 +--
drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +++---
drivers/gpu/drm/i915/display/intel_color.c | 6 +-
drivers/gpu/drm/i915/display/intel_crt.c | 6 +-
drivers/gpu/drm/i915/display/intel_crtc.c | 4 +-
drivers/gpu/drm/i915/display/intel_csr.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 26 ++++-----
.../drm/i915/display/intel_ddi_buf_trans.c | 8 +--
drivers/gpu/drm/i915/display/intel_display.c | 56 +++++++++----------
.../drm/i915/display/intel_display_power.c | 26 ++++-----
drivers/gpu/drm/i915/display/intel_dp.c | 8 +--
drivers/gpu/drm/i915/display/intel_dpll.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 20 +++----
.../drm/i915/display/intel_fifo_underrun.c | 4 +-
drivers/gpu/drm/i915/display/intel_gmbus.c | 4 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 10 ++--
drivers/gpu/drm/i915/display/intel_panel.c | 8 +--
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 4 +-
drivers/gpu/drm/i915/display/intel_psr.c | 4 +-
drivers/gpu/drm/i915/display/intel_tc.c | 6 +-
drivers/gpu/drm/i915/display/intel_tv.c | 6 +-
.../drm/i915/display/skl_universal_plane.c | 8 +--
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/i915_irq.c | 10 ++--
drivers/gpu/drm/i915/intel_pm.c | 48 ++++++++--------
35 files changed, 165 insertions(+), 166 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 456374ddf37a..80da0e3571a4 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -144,7 +144,7 @@ static bool i9xx_plane_has_windowing(struct intel_plane *plane)
return i9xx_plane == PLANE_B;
else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
return false;
- else if (IS_DISPLAY_VER(dev_priv, 4))
+ else if (DISPLAY_VER(dev_priv) == 4)
return i9xx_plane == PLANE_C;
else
return i9xx_plane == PLANE_B ||
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 9282978060b0..37e2d93d064c 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -592,7 +592,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
* a value '0' inside TA_PARAM_REGISTERS otherwise
* leave all fields at HW default values.
*/
- if (IS_DISPLAY_VER(dev_priv, 11)) {
+ if (DISPLAY_VER(dev_priv) == 11) {
if (afe_clk(encoder, crtc_state) <= 800000) {
for_each_dsi_port(port, intel_dsi->ports) {
tmp = intel_de_read(dev_priv,
@@ -1158,7 +1158,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
gen11_dsi_configure_transcoder(encoder, crtc_state);
/* Step 4l: Gate DDI clocks */
- if (IS_DISPLAY_VER(dev_priv, 11))
+ if (DISPLAY_VER(dev_priv) == 11)
gen11_dsi_gate_clocks(encoder);
}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 4fa389fce8cb..45feaaddab26 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -332,7 +332,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
plane_state->hw.fb->format->is_yuv &&
plane_state->hw.fb->format->num_planes > 1) {
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- if (IS_DISPLAY_VER(dev_priv, 9)) {
+ if (DISPLAY_VER(dev_priv) == 9) {
mode = SKL_PS_SCALER_MODE_NV12;
} else if (icl_is_hdr_plane(dev_priv, plane->id)) {
/*
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 9fe3a25710b8..b40e929a167e 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -591,7 +591,7 @@ static void enable_audio_dsc_wa(struct intel_encoder *encoder,
val = intel_de_read(i915, AUD_CONFIG_BE);
- if (IS_DISPLAY_VER(i915, 11))
+ if (DISPLAY_VER(i915) == 11)
val |= HBLANK_EARLY_ENABLE_ICL(pipe);
else if (DISPLAY_VER(i915) >= 12)
val |= HBLANK_EARLY_ENABLE_TGL(pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index ea4837d485a1..befab891a6b9 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -610,7 +610,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *i915)
* Only parse SDVO mappings on gens that could have SDVO. This isn't
* accurate and doesn't have to be, as long as it's not too strict.
*/
- if (!IS_DISPLAY_RANGE(i915, 3, 7)) {
+ if (!IS_DISPLAY_VER(i915, 3, 7)) {
drm_dbg_kms(&i915->drm, "Skipping SDVO device mapping\n");
return;
}
@@ -1659,7 +1659,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
} else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) {
ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);
- } else if (HAS_PCH_TGP(i915) && IS_DISPLAY_VER(i915, 9)) {
+ } else if (HAS_PCH_TGP(i915) && DISPLAY_VER(i915) == 9) {
ddc_pin_map = gen9bc_tgp_ddc_pin_map;
n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map);
} else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 584ab5ce4106..20dbc3759d27 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -77,7 +77,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
qi->num_points = dram_info->num_qgv_points;
- if (IS_DISPLAY_VER(dev_priv, 12))
+ if (DISPLAY_VER(dev_priv) == 12)
switch (dram_info->type) {
case INTEL_DRAM_DDR4:
qi->t_bl = 4;
@@ -89,7 +89,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
qi->t_bl = 16;
break;
}
- else if (IS_DISPLAY_VER(dev_priv, 11))
+ else if (DISPLAY_VER(dev_priv) == 11)
qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
if (drm_WARN_ON(&dev_priv->drm,
@@ -271,9 +271,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
icl_get_bw_info(dev_priv, &adls_sa_info);
else if (IS_ROCKETLAKE(dev_priv))
icl_get_bw_info(dev_priv, &rkl_sa_info);
- else if (IS_DISPLAY_VER(dev_priv, 12))
+ else if (DISPLAY_VER(dev_priv) == 12)
icl_get_bw_info(dev_priv, &tgl_sa_info);
- else if (IS_DISPLAY_VER(dev_priv, 11))
+ else if (DISPLAY_VER(dev_priv) == 11)
icl_get_bw_info(dev_priv, &icl_sa_info);
}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 489acf6b5cf1..1f0bd23bb883 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1801,7 +1801,7 @@ void intel_cdclk_init_hw(struct drm_i915_private *i915)
{
if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
bxt_cdclk_init_hw(i915);
- else if (IS_DISPLAY_VER(i915, 9))
+ else if (DISPLAY_VER(i915) == 9)
skl_cdclk_init_hw(i915);
}
@@ -1816,7 +1816,7 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
{
if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
bxt_cdclk_uninit_hw(i915);
- else if (IS_DISPLAY_VER(i915, 9))
+ else if (DISPLAY_VER(i915) == 9)
skl_cdclk_uninit_hw(i915);
}
@@ -2004,7 +2004,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
if (DISPLAY_VER(dev_priv) >= 10)
return DIV_ROUND_UP(pixel_rate, 2);
- else if (IS_DISPLAY_VER(dev_priv, 9) ||
+ else if (DISPLAY_VER(dev_priv) == 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
return pixel_rate;
else if (IS_CHERRYVIEW(dev_priv))
@@ -2052,10 +2052,10 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
crtc_state->has_audio &&
crtc_state->port_clock >= 540000 &&
crtc_state->lane_count == 4) {
- if (IS_DISPLAY_VER(dev_priv, 10)) {
+ if (DISPLAY_VER(dev_priv) == 10) {
/* Display WA #1145: glk,cnl */
min_cdclk = max(316800, min_cdclk);
- } else if (IS_DISPLAY_VER(dev_priv, 9) || IS_BROADWELL(dev_priv)) {
+ } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) {
/* Display WA #1144: skl,bxt */
min_cdclk = max(432000, min_cdclk);
}
@@ -2594,7 +2594,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
if (DISPLAY_VER(dev_priv) >= 10)
return 2 * max_cdclk_freq;
- else if (IS_DISPLAY_VER(dev_priv, 9) ||
+ else if (DISPLAY_VER(dev_priv) == 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
return max_cdclk_freq;
else if (IS_CHERRYVIEW(dev_priv))
@@ -2631,7 +2631,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
dev_priv->max_cdclk_freq = 316800;
} else if (IS_BROXTON(dev_priv)) {
dev_priv->max_cdclk_freq = 624000;
- } else if (IS_DISPLAY_VER(dev_priv, 9)) {
+ } else if (DISPLAY_VER(dev_priv) == 9) {
u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
int max_cdclk, vco;
@@ -2889,7 +2889,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
dev_priv->cdclk.table = glk_cdclk_table;
else
dev_priv->cdclk.table = bxt_cdclk_table;
- } else if (IS_DISPLAY_VER(dev_priv, 9)) {
+ } else if (DISPLAY_VER(dev_priv) == 9) {
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.set_cdclk = skl_set_cdclk;
dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
@@ -2912,7 +2912,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
if (DISPLAY_VER(dev_priv) >= 10 || IS_BROXTON(dev_priv))
dev_priv->display.get_cdclk = bxt_get_cdclk;
- else if (IS_DISPLAY_VER(dev_priv, 9))
+ else if (DISPLAY_VER(dev_priv) == 9)
dev_priv->display.get_cdclk = skl_get_cdclk;
else if (IS_BROADWELL(dev_priv))
dev_priv->display.get_cdclk = bdw_get_cdclk;
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index c75d7124d57a..5fae69879adf 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -225,7 +225,7 @@ static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
*/
return crtc_state->limited_color_range &&
(IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
- IS_DISPLAY_RANGE(dev_priv, 9, 10));
+ IS_DISPLAY_VER(dev_priv, 9, 10));
}
static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
@@ -1711,7 +1711,7 @@ int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_stat
} else {
if (DISPLAY_VER(dev_priv) >= 11)
return icl_gamma_precision(crtc_state);
- else if (IS_DISPLAY_VER(dev_priv, 10))
+ else if (DISPLAY_VER(dev_priv) == 10)
return glk_gamma_precision(crtc_state);
else if (IS_IRONLAKE(dev_priv))
return ilk_gamma_precision(crtc_state);
@@ -2136,7 +2136,7 @@ void intel_color_init(struct intel_crtc *crtc)
if (DISPLAY_VER(dev_priv) >= 11) {
dev_priv->display.load_luts = icl_load_luts;
dev_priv->display.read_luts = icl_read_luts;
- } else if (IS_DISPLAY_VER(dev_priv, 10)) {
+ } else if (DISPLAY_VER(dev_priv) == 10) {
dev_priv->display.load_luts = glk_load_luts;
dev_priv->display.read_luts = glk_read_luts;
} else if (DISPLAY_VER(dev_priv) >= 8) {
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 580d652c3276..c85092eaa5c2 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -356,7 +356,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
* DAC limit supposedly 355 MHz.
*/
max_clock = 270000;
- else if (IS_DISPLAY_RANGE(dev_priv, 3, 4))
+ else if (IS_DISPLAY_VER(dev_priv, 3, 4))
max_clock = 400000;
else
max_clock = 350000;
@@ -711,7 +711,7 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
/* Set the border color to purple. */
intel_uncore_write(uncore, bclrpat_reg, 0x500050);
- if (!IS_DISPLAY_VER(dev_priv, 2)) {
+ if (DISPLAY_VER(dev_priv) != 2) {
u32 pipeconf = intel_uncore_read(uncore, pipeconf_reg);
intel_uncore_write(uncore,
pipeconf_reg,
@@ -1047,7 +1047,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
else
crt->base.pipe_mask = ~0;
- if (IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
connector->interlace_allowed = 0;
else
connector->interlace_allowed = 1;
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 39358076c05b..95ff1707b4bd 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -302,11 +302,11 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
if (IS_CHERRYVIEW(dev_priv) ||
IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
funcs = &g4x_crtc_funcs;
- else if (IS_DISPLAY_VER(dev_priv, 4))
+ else if (DISPLAY_VER(dev_priv) == 4)
funcs = &i965_crtc_funcs;
else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
funcs = &i915gm_crtc_funcs;
- else if (IS_DISPLAY_VER(dev_priv, 3))
+ else if (DISPLAY_VER(dev_priv) == 3)
funcs = &i915_crtc_funcs;
else
funcs = &i8xx_crtc_funcs;
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index e54521d7b931..26a3c6787e9e 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -709,7 +709,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
csr->fw_path = TGL_CSR_PATH;
csr->required_version = TGL_CSR_VERSION_REQUIRED;
csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
- } else if (IS_DISPLAY_VER(dev_priv, 11)) {
+ } else if (DISPLAY_VER(dev_priv) == 11) {
csr->fw_path = ICL_CSR_PATH;
csr->required_version = ICL_CSR_VERSION_REQUIRED;
csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index deef24da00b5..6bb2d2bb7239 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -113,7 +113,7 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
&n_entries);
/* If we're boosting the current, set bit 31 of trans1 */
- if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv) &&
+ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
intel_bios_encoder_dp_boost_level(encoder->devdata))
iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
@@ -147,7 +147,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
level = n_entries - 1;
/* If we're boosting the current, set bit 31 of trans1 */
- if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv) &&
+ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
intel_bios_encoder_hdmi_boost_level(encoder->devdata))
iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
@@ -473,7 +473,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
}
- if (IS_DISPLAY_RANGE(dev_priv, 8, 10) &&
+ if (IS_DISPLAY_VER(dev_priv, 8, 10) &&
crtc_state->master_transcoder != INVALID_TRANSCODER) {
u8 master_select =
bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
@@ -548,7 +548,7 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
ctl &= ~TRANS_DDI_FUNC_ENABLE;
- if (IS_DISPLAY_RANGE(dev_priv, 8, 10))
+ if (IS_DISPLAY_VER(dev_priv, 8, 10))
ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
@@ -978,7 +978,7 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
else
tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
- } else if (IS_DISPLAY_VER(dev_priv, 11)) {
+ } else if (DISPLAY_VER(dev_priv) == 11) {
if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
@@ -1557,7 +1557,7 @@ hsw_set_signal_levels(struct intel_dp *intel_dp,
intel_dp->DP &= ~DDI_BUF_EMP_MASK;
intel_dp->DP |= signal_levels;
- if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv))
+ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
skl_ddi_set_iboost(encoder, crtc_state, level);
intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
@@ -3094,7 +3094,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) >= 12)
tgl_ddi_vswing_sequence(encoder, crtc_state, level);
- else if (IS_DISPLAY_VER(dev_priv, 11))
+ else if (DISPLAY_VER(dev_priv) == 11)
icl_ddi_vswing_sequence(encoder, crtc_state, level);
else if (IS_CANNONLAKE(dev_priv))
cnl_ddi_vswing_sequence(encoder, crtc_state, level);
@@ -3103,11 +3103,11 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
else
intel_prepare_hdmi_ddi_buffers(encoder, level);
- if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv))
+ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
skl_ddi_set_iboost(encoder, crtc_state, level);
/* Display WA #1143: skl,kbl,cfl */
- if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
/*
* For some reason these chicken bits have been
* stuffed into a transcoder register, event though
@@ -4590,7 +4590,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
/* BXT/GLK have fixed PLL->port mapping */
encoder->get_config = bxt_ddi_get_config;
- } else if (IS_DISPLAY_VER(dev_priv, 9)) {
+ } else if (DISPLAY_VER(dev_priv) == 9) {
encoder->enable_clock = skl_ddi_enable_clock;
encoder->disable_clock = skl_ddi_disable_clock;
encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
@@ -4610,11 +4610,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
else if (IS_JSL_EHL(dev_priv))
encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
- else if (IS_DISPLAY_VER(dev_priv, 11))
+ else if (DISPLAY_VER(dev_priv) == 11)
encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
- else if (IS_DISPLAY_VER(dev_priv, 10))
+ else if (DISPLAY_VER(dev_priv) == 10)
encoder->hpd_pin = cnl_hpd_pin(dev_priv, port);
- else if (IS_DISPLAY_VER(dev_priv, 9))
+ else if (DISPLAY_VER(dev_priv) == 9)
encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
else
encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index fdd25861edd5..58d6417b8f3e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -881,7 +881,7 @@ intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
const struct ddi_buf_trans *ddi_translations =
skl_get_buf_trans_edp(encoder, n_entries);
*n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
@@ -919,7 +919,7 @@ intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
return skl_get_buf_trans_hdmi(dev_priv, n_entries);
} else if (IS_BROADWELL(dev_priv)) {
*n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
@@ -1361,7 +1361,7 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder,
else
tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries);
*default_entry = n_entries - 1;
- } else if (IS_DISPLAY_VER(dev_priv, 11)) {
+ } else if (DISPLAY_VER(dev_priv) == 11) {
if (intel_phy_is_combo(dev_priv, phy))
icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
else
@@ -1373,7 +1373,7 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder,
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
bxt_get_buf_trans_hdmi(encoder, &n_entries);
*default_entry = n_entries - 1;
- } else if (IS_DISPLAY_VER(dev_priv, 9)) {
+ } else if (DISPLAY_VER(dev_priv) == 9) {
intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
*default_entry = 8;
} else if (IS_BROADWELL(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 411b46c012f8..fababa82b4af 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -230,7 +230,7 @@ static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
u32 line1, line2;
u32 line_mask;
- if (IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
line_mask = DSL_LINEMASK_GEN2;
else
line_mask = DSL_LINEMASK_GEN3;
@@ -874,7 +874,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
case DRM_FORMAT_MOD_LINEAR:
return intel_tile_size(dev_priv);
case I915_FORMAT_MOD_X_TILED:
- if (IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
return 128;
else
return 512;
@@ -889,7 +889,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
return 64;
fallthrough;
case I915_FORMAT_MOD_Y_TILED:
- if (IS_DISPLAY_VER(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
+ if (DISPLAY_VER(dev_priv) == 2 || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
else
return 512;
@@ -1406,7 +1406,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
* require the entire fb to accommodate that to avoid
* potential runtime errors at plane configuration time.
*/
- if (IS_DISPLAY_VER(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
+ if (DISPLAY_VER(dev_priv) == 9 && color_plane == 0 && fb->width > 3840)
tile_width *= 4;
/*
* The main surface pitch must be padded to a multiple of four
@@ -1608,7 +1608,7 @@ static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
* Gen2 reports pipe underruns whenever all planes are disabled.
* So disable underrun reporting before all the planes get disabled.
*/
- if (IS_DISPLAY_VER(dev_priv, 2) && !crtc_state->active_planes)
+ if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
intel_disable_plane(plane, crtc_state);
@@ -2471,7 +2471,7 @@ static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
return false;
/* WA Display #0827: Gen9:all */
- if (IS_DISPLAY_VER(dev_priv, 9))
+ if (DISPLAY_VER(dev_priv) == 9)
return true;
return false;
@@ -2482,7 +2482,7 @@ static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
/* Wa_2006604312:icl,ehl */
- if (crtc_state->scaler_state.scaler_users > 0 && IS_DISPLAY_VER(dev_priv, 11))
+ if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
return true;
return false;
@@ -2682,7 +2682,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
* chance of catching underruns with the intermediate watermarks
* vs. the old plane configuration.
*/
- if (IS_DISPLAY_VER(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
+ if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
/*
@@ -3201,7 +3201,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
crtc->active = true;
/* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
- psl_clkgate_wa = IS_DISPLAY_VER(dev_priv, 10) &&
+ psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
new_crtc_state->pch_pfit.enabled;
if (psl_clkgate_wa)
glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
@@ -3655,7 +3655,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
crtc->active = true;
- if (!IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
intel_encoders_pre_enable(state, crtc);
@@ -3680,7 +3680,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
intel_encoders_enable(state, crtc);
/* prevents spurious underruns */
- if (IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
intel_wait_for_vblank(dev_priv, pipe);
}
@@ -3711,7 +3711,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
* On gen2 planes are double buffered but the pipe isn't, so we must
* wait for planes to fully turn off before disabling the pipe.
*/
- if (IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
intel_wait_for_vblank(dev_priv, pipe);
intel_encoders_disable(state, crtc);
@@ -3735,7 +3735,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
intel_encoders_post_pll_disable(state, crtc);
- if (!IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
if (!dev_priv->display.initial_watermarks)
@@ -4302,7 +4302,7 @@ static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
* Strictly speaking some registers are available before
* gen7, but we only support DRRS on gen7+
*/
- return IS_DISPLAY_VER(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
+ return DISPLAY_VER(dev_priv) == 7 || IS_CHERRYVIEW(dev_priv);
}
static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
@@ -4449,7 +4449,7 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
return false;
if (DISPLAY_VER(dev_priv) >= 9 ||
@@ -5644,7 +5644,7 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
* ivb/hsw (since we don't use the higher upscaling modes which
* differentiates them) so just WARN about this case for now.
*/
- drm_WARN_ON(&dev_priv->drm, IS_DISPLAY_VER(dev_priv, 7) &&
+ drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 &&
(ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
}
@@ -6327,7 +6327,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
return dev_priv->vbt.lvds_ssc_freq;
else if (HAS_PCH_SPLIT(dev_priv))
return 120000;
- else if (!IS_DISPLAY_VER(dev_priv, 2))
+ else if (DISPLAY_VER(dev_priv) != 2)
return 96000;
else
return 48000;
@@ -6360,7 +6360,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
}
- if (!IS_DISPLAY_VER(dev_priv, 2)) {
+ if (DISPLAY_VER(dev_priv) != 2) {
if (IS_PINEVIEW(dev_priv))
clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
@@ -8788,7 +8788,7 @@ intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
* However if queried just before the start of vblank we'll get an
* answer that's slightly in the future.
*/
- if (IS_DISPLAY_VER(dev_priv, 2)) {
+ if (DISPLAY_VER(dev_priv) == 2) {
int vtotal;
vtotal = adjusted_mode.crtc_vtotal;
@@ -9665,7 +9665,7 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- if (!IS_DISPLAY_VER(dev_priv, 2) || crtc_state->active_planes)
+ if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
if (crtc_state->has_pch_encoder) {
@@ -10283,7 +10283,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
* chance of catching underruns with the intermediate watermarks
* vs. the new plane configuration.
*/
- if (IS_DISPLAY_VER(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
+ if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
if (dev_priv->display.optimize_watermarks)
@@ -10862,7 +10862,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
intel_ddi_init(dev_priv, PORT_C);
intel_ddi_init(dev_priv, PORT_D);
icl_dsi_init(dev_priv);
- } else if (IS_DISPLAY_VER(dev_priv, 11)) {
+ } else if (DISPLAY_VER(dev_priv) == 11) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
@@ -10903,7 +10903,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
*/
found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
/* WaIgnoreDDIAStrap: skl */
- if (found || IS_DISPLAY_VER(dev_priv, 9))
+ if (found || DISPLAY_VER(dev_priv) == 9)
intel_ddi_init(dev_priv, PORT_A);
/* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
@@ -10928,7 +10928,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
/*
* On SKL we don't have a way to detect DDI-E so we rely on VBT.
*/
- if (IS_DISPLAY_VER(dev_priv, 9) &&
+ if (DISPLAY_VER(dev_priv) == 9 &&
intel_bios_is_port_present(dev_priv, PORT_E))
intel_ddi_init(dev_priv, PORT_E);
@@ -11019,7 +11019,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
} else if (IS_PINEVIEW(dev_priv)) {
intel_lvds_init(dev_priv);
intel_crt_init(dev_priv);
- } else if (IS_DISPLAY_RANGE(dev_priv, 3, 4)) {
+ } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
bool found = false;
if (IS_MOBILE(dev_priv))
@@ -11063,7 +11063,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (SUPPORTS_TV(dev_priv))
intel_tv_init(dev_priv);
- } else if (IS_DISPLAY_VER(dev_priv, 2)) {
+ } else if (DISPLAY_VER(dev_priv) == 2) {
if (IS_I85X(dev_priv))
intel_lvds_init(dev_priv);
@@ -11734,7 +11734,7 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
} else if (DISPLAY_VER(i915) >= 4) {
mode_config->max_width = 8192;
mode_config->max_height = 8192;
- } else if (IS_DISPLAY_VER(i915, 3)) {
+ } else if (DISPLAY_VER(i915) == 3) {
mode_config->max_width = 4096;
mode_config->max_height = 4096;
} else {
@@ -12627,7 +12627,7 @@ static void intel_early_display_was(struct drm_i915_private *dev_priv)
* Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
* Also known as Wa_14010480278.
*/
- if (IS_DISPLAY_RANGE(dev_priv, 10, 12))
+ if (IS_DISPLAY_VER(dev_priv, 10, 12))
intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index ad30947c58a3..0af1dee1ac95 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -550,7 +550,7 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
if (drm_WARN_ON(&dev_priv->drm, !dig_port))
return;
- if (IS_DISPLAY_VER(dev_priv, 11) && dig_port->tc_legacy_port)
+ if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port)
return;
drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
@@ -619,7 +619,7 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
* exit sequence.
*/
timeout_expected = is_tbt;
- if (IS_DISPLAY_VER(dev_priv, 11) && dig_port->tc_legacy_port) {
+ if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port) {
icl_tc_cold_exit(dev_priv);
timeout_expected = true;
}
@@ -709,7 +709,7 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
* BIOS's own request bits, which are forced-on for these power wells
* when exiting DC5/6.
*/
- if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv) &&
+ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
(id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
val |= intel_de_read(dev_priv, regs->bios);
@@ -807,7 +807,7 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
if (DISPLAY_VER(dev_priv) >= 12)
mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
| DC_STATE_EN_DC9;
- else if (IS_DISPLAY_VER(dev_priv, 11))
+ else if (DISPLAY_VER(dev_priv) == 11)
mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
mask |= DC_STATE_EN_DC9;
@@ -1066,7 +1066,7 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n");
/* Wa Display #1183: skl,kbl,cfl */
- if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv))
+ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1,
intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
@@ -1093,7 +1093,7 @@ static void skl_enable_dc6(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n");
/* Wa Display #1183: skl,kbl,cfl */
- if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv))
+ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1,
intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
@@ -4694,9 +4694,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
} else if (IS_ROCKETLAKE(dev_priv)) {
err = set_power_wells(power_domains, rkl_power_wells);
- } else if (IS_DISPLAY_VER(dev_priv, 12)) {
+ } else if (DISPLAY_VER(dev_priv) == 12) {
err = set_power_wells(power_domains, tgl_power_wells);
- } else if (IS_DISPLAY_VER(dev_priv, 11)) {
+ } else if (DISPLAY_VER(dev_priv) == 11) {
err = set_power_wells(power_domains, icl_power_wells);
} else if (IS_CNL_WITH_PORT_F(dev_priv)) {
err = set_power_wells(power_domains, cnl_power_wells);
@@ -4708,7 +4708,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
err = set_power_wells(power_domains, glk_power_wells);
} else if (IS_BROXTON(dev_priv)) {
err = set_power_wells(power_domains, bxt_power_wells);
- } else if (IS_DISPLAY_VER(dev_priv, 9)) {
+ } else if (DISPLAY_VER(dev_priv) == 9) {
err = set_power_wells(power_domains, skl_power_wells);
} else if (IS_CHERRYVIEW(dev_priv)) {
err = set_power_wells(power_domains, chv_power_wells);
@@ -4853,7 +4853,7 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
* expect us to program the abox_ctl0 register as well, even though
* we don't have to program other instance-0 registers like BW_BUDDY.
*/
- if (IS_DISPLAY_VER(dev_priv, 12))
+ if (DISPLAY_VER(dev_priv) == 12)
abox_regs |= BIT(0);
for_each_set_bit(i, &abox_regs, sizeof(abox_regs))
@@ -5450,7 +5450,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
intel_csr_load_program(dev_priv);
/* Wa_14011508470 */
- if (IS_DISPLAY_VER(dev_priv, 12)) {
+ if (DISPLAY_VER(dev_priv) == 12) {
val = DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM |
DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR;
intel_uncore_rmw(&dev_priv->uncore, GEN11_CHICKEN_DCPR_2, 0, val);
@@ -5665,7 +5665,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
cnl_display_core_init(i915, resume);
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
bxt_display_core_init(i915, resume);
- } else if (IS_DISPLAY_VER(i915, 9)) {
+ } else if (DISPLAY_VER(i915) == 9) {
skl_display_core_init(i915, resume);
} else if (IS_CHERRYVIEW(i915)) {
mutex_lock(&power_domains->lock);
@@ -5826,7 +5826,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
cnl_display_core_uninit(i915);
else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
bxt_display_core_uninit(i915);
- else if (IS_DISPLAY_VER(i915, 9))
+ else if (DISPLAY_VER(i915) == 9)
skl_display_core_uninit(i915);
power_domains->display_core_suspended = true;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6750949aa261..5ee953aaa00c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -215,7 +215,7 @@ bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
return DISPLAY_VER(dev_priv) >= 12 ||
- (IS_DISPLAY_VER(dev_priv, 11) &&
+ (DISPLAY_VER(dev_priv) == 11 &&
encoder->port != PORT_A);
}
@@ -295,7 +295,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
source_rates = cnl_rates;
size = ARRAY_SIZE(cnl_rates);
- if (IS_DISPLAY_VER(dev_priv, 10))
+ if (DISPLAY_VER(dev_priv) == 10)
max_rate = cnl_max_source_rate(intel_dp);
else if (IS_JSL_EHL(dev_priv))
max_rate = ehl_max_source_rate(intel_dp);
@@ -304,7 +304,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
source_rates = bxt_rates;
size = ARRAY_SIZE(bxt_rates);
- } else if (IS_DISPLAY_VER(dev_priv, 9)) {
+ } else if (DISPLAY_VER(dev_priv) == 9) {
source_rates = skl_rates;
size = ARRAY_SIZE(skl_rates);
} else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
@@ -916,7 +916,7 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
if (DISPLAY_VER(dev_priv) >= 12)
return true;
- if (IS_DISPLAY_VER(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
+ if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
return true;
return false;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 158f271299a4..9114953f57f1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1356,7 +1356,7 @@ intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
else if (IS_PINEVIEW(dev_priv))
dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
- else if (!IS_DISPLAY_VER(dev_priv, 2))
+ else if (DISPLAY_VER(dev_priv) != 2)
dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
else
dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index e32de7c848e9..e1c916640768 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4443,7 +4443,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
dpll_mgr = &cnl_pll_mgr;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
dpll_mgr = &bxt_pll_mgr;
- else if (IS_DISPLAY_VER(dev_priv, 9))
+ else if (DISPLAY_VER(dev_priv) == 9)
dpll_mgr = &skl_pll_mgr;
else if (HAS_DDI(dev_priv))
dpll_mgr = &hsw_pll_mgr;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index fca41ac5b8e1..0ec9ad7220a1 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -84,7 +84,7 @@ int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
unsigned int intel_tile_size(const struct drm_i915_private *i915)
{
- return IS_DISPLAY_VER(i915, 2) ? 2048 : 4096;
+ return DISPLAY_VER(i915) == 2 ? 2048 : 4096;
}
unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 04d9c7d22b04..a6bf18835d36 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -67,7 +67,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
int lines;
intel_fbc_get_plane_source_size(cache, NULL, &lines);
- if (IS_DISPLAY_VER(dev_priv, 7))
+ if (DISPLAY_VER(dev_priv) == 7)
lines = min(lines, 2048);
else if (DISPLAY_VER(dev_priv) >= 8)
lines = min(lines, 2560);
@@ -109,7 +109,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
cfb_pitch = params->fb.stride;
/* FBC_CTL wants 32B or 64B units */
- if (IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
cfb_pitch = (cfb_pitch / 32) - 1;
else
cfb_pitch = (cfb_pitch / 64) - 1;
@@ -118,7 +118,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
intel_de_write(dev_priv, FBC_TAG(i), 0);
- if (IS_DISPLAY_VER(dev_priv, 4)) {
+ if (DISPLAY_VER(dev_priv) == 4) {
u32 fbc_ctl2;
/* Set it up... */
@@ -302,7 +302,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
int threshold = dev_priv->fbc.threshold;
/* Display WA #0529: skl, kbl, bxt. */
- if (IS_DISPLAY_VER(dev_priv, 9)) {
+ if (DISPLAY_VER(dev_priv) == 9) {
u32 val = intel_de_read(dev_priv, CHICKEN_MISC_4);
val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
@@ -445,7 +445,7 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv,
* reserved range size, so it always assumes the maximum (8mb) is used.
* If we enable FBC using a CFB on that memory range we'll get FIFO
* underruns, even if that range is not reserved by the BIOS. */
- if (IS_BROADWELL(dev_priv) || (IS_DISPLAY_VER(dev_priv, 9) &&
+ if (IS_BROADWELL(dev_priv) || (DISPLAY_VER(dev_priv) == 9 &&
!IS_BROXTON(dev_priv)))
end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
else
@@ -591,14 +591,14 @@ static bool stride_is_valid(struct drm_i915_private *dev_priv,
if (stride < 512)
return false;
- if (IS_DISPLAY_VER(dev_priv, 2) || IS_DISPLAY_VER(dev_priv, 3))
+ if (DISPLAY_VER(dev_priv) == 2 || DISPLAY_VER(dev_priv) == 3)
return stride == 4096 || stride == 8192;
- if (IS_DISPLAY_VER(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048)
+ if (DISPLAY_VER(dev_priv) == 4 && !IS_G4X(dev_priv) && stride < 2048)
return false;
/* Display WA #1105: skl,bxt,kbl,cfl,glk */
- if (IS_DISPLAY_VER(dev_priv, 9) &&
+ if (DISPLAY_VER(dev_priv) == 9 &&
modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
return false;
@@ -618,7 +618,7 @@ static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
case DRM_FORMAT_XRGB1555:
case DRM_FORMAT_RGB565:
/* 16bpp not supported on gen2 */
- if (IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
return false;
/* WaFbcOnly1to1Ratio:ctg */
if (IS_G4X(dev_priv))
@@ -760,7 +760,7 @@ static u16 intel_fbc_gen9_wa_cfb_stride(struct drm_i915_private *dev_priv)
struct intel_fbc *fbc = &dev_priv->fbc;
struct intel_fbc_state_cache *cache = &fbc->state_cache;
- if ((IS_DISPLAY_VER(dev_priv, 9)) &&
+ if ((DISPLAY_VER(dev_priv) == 9) &&
cache->fb.modifier != I915_FORMAT_MOD_X_TILED)
return DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8;
else
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index 9605a1064366..0fce9fd6e0a9 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -271,7 +271,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
ilk_set_fifo_underrun_reporting(dev, pipe, enable);
- else if (IS_DISPLAY_VER(dev_priv, 7))
+ else if (DISPLAY_VER(dev_priv) == 7)
ivb_set_fifo_underrun_reporting(dev, pipe, enable, old);
else if (DISPLAY_VER(dev_priv) >= 8)
bdw_set_fifo_underrun_reporting(dev, pipe, enable);
@@ -432,7 +432,7 @@ void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
if (HAS_GMCH(dev_priv))
i9xx_check_fifo_underruns(crtc);
- else if (IS_DISPLAY_VER(dev_priv, 7))
+ else if (DISPLAY_VER(dev_priv) == 7)
ivb_check_fifo_underruns(crtc);
}
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 2ea6adc3bd3e..17ab3cb81e02 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -109,7 +109,7 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
return &gmbus_pins_cnp[pin];
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
return &gmbus_pins_bxt[pin];
- else if (IS_DISPLAY_VER(dev_priv, 9))
+ else if (DISPLAY_VER(dev_priv) == 9)
return &gmbus_pins_skl[pin];
else if (IS_BROADWELL(dev_priv))
return &gmbus_pins_bdw[pin];
@@ -130,7 +130,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
size = ARRAY_SIZE(gmbus_pins_cnp);
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
size = ARRAY_SIZE(gmbus_pins_bxt);
- else if (IS_DISPLAY_VER(dev_priv, 9))
+ else if (DISPLAY_VER(dev_priv) == 9)
size = ARRAY_SIZE(gmbus_pins_skl);
else if (IS_BROADWELL(dev_priv))
size = ARRAY_SIZE(gmbus_pins_bdw);
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 75050a040577..d254fe67ab7f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -291,7 +291,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
* process from other platforms. These platforms use the GT Driver
* Mailbox interface.
*/
- if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
ret = sandybridge_pcode_write(dev_priv,
SKL_PCODE_LOAD_HDCP_KEYS, 1);
if (ret) {
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f2d1fef8bd9d..47a8f0a1c5e2 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1978,7 +1978,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
/* Display Wa_1405510057:icl,ehl */
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
- bpc == 10 && IS_DISPLAY_VER(dev_priv, 11) &&
+ bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
(adjusted_mode->crtc_hblank_end -
adjusted_mode->crtc_hblank_start) % 8 == 2)
return false;
@@ -2715,7 +2715,7 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
else if (IS_ROCKETLAKE(dev_priv))
ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
- else if (IS_DISPLAY_VER(dev_priv, 9) && HAS_PCH_TGP(dev_priv))
+ else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
else if (HAS_PCH_MCC(dev_priv))
ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index f31a368f34c5..dd12d15f47c7 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -280,7 +280,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
* special lvds dither control bit on pch-split platforms, dithering is
* only controlled through the PIPECONF reg.
*/
- if (IS_DISPLAY_VER(dev_priv, 4)) {
+ if (DISPLAY_VER(dev_priv) == 4) {
/*
* Bspec wording suggests that LVDS port dithering only exists
* for 18bpp panels.
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index e477b6114a60..d1255911a327 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -550,7 +550,7 @@ static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 widt
{
u32 sw;
- if (IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
sw = ALIGN((offset & 31) + width, 32);
else
sw = ALIGN((offset & 63) + width, 64);
@@ -818,7 +818,7 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay,
oconfig |= OCONF_CC_OUT_8BIT;
if (crtc_state->gamma_enable)
oconfig |= OCONF_GAMMA2_ENABLE;
- if (IS_DISPLAY_VER(dev_priv, 4))
+ if (DISPLAY_VER(dev_priv) == 4)
oconfig |= OCONF_CSC_MODE_BT709;
oconfig |= pipe == 0 ?
OCONF_PIPE_A : OCONF_PIPE_B;
@@ -1052,7 +1052,7 @@ static int check_overlay_src(struct drm_i915_private *dev_priv,
if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
return -EINVAL;
- if (IS_DISPLAY_VER(dev_priv, 4) && rec->stride_Y < 512)
+ if (DISPLAY_VER(dev_priv) == 4 && rec->stride_Y < 512)
return -EINVAL;
tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
@@ -1279,7 +1279,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
attrs->contrast = overlay->contrast;
attrs->saturation = overlay->saturation;
- if (!IS_DISPLAY_VER(dev_priv, 2)) {
+ if (DISPLAY_VER(dev_priv) != 2) {
attrs->gamma0 = intel_de_read(dev_priv, OGAMC0);
attrs->gamma1 = intel_de_read(dev_priv, OGAMC1);
attrs->gamma2 = intel_de_read(dev_priv, OGAMC2);
@@ -1303,7 +1303,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
update_reg_attrs(overlay, overlay->regs);
if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
- if (IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
goto out_unlock;
if (overlay->active) {
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 2fcbb2ba2d78..551fcaa77c2c 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -667,7 +667,7 @@ static void i9xx_set_backlight(const struct drm_connector_state *conn_state, u32
pci_write_config_byte(to_pci_dev(dev_priv->drm.dev), LBPC, lbpc);
}
- if (IS_DISPLAY_VER(dev_priv, 4)) {
+ if (DISPLAY_VER(dev_priv) == 4) {
mask = BACKLIGHT_DUTY_CYCLE_MASK;
} else {
level <<= 1;
@@ -1040,7 +1040,7 @@ static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state,
* 855gm only, but checking for gen2 is safe, as 855gm is the only gen2
* that has backlight.
*/
- if (IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
intel_de_write(dev_priv, BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);
}
@@ -1728,7 +1728,7 @@ static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unu
ctl = intel_de_read(dev_priv, BLC_PWM_CTL);
- if (IS_DISPLAY_VER(dev_priv, 2) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
+ if (DISPLAY_VER(dev_priv) == 2 || IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE;
if (IS_PINEVIEW(dev_priv))
@@ -2178,7 +2178,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
} else {
panel->backlight.pwm_funcs = &vlv_pwm_funcs;
}
- } else if (IS_DISPLAY_VER(dev_priv, 4)) {
+ } else if (DISPLAY_VER(dev_priv) == 4) {
panel->backlight.pwm_funcs = &i965_pwm_funcs;
} else {
panel->backlight.pwm_funcs = &i9xx_pwm_funcs;
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
index 7c8e0d76207f..0f6de96e6d43 100644
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
@@ -409,7 +409,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
enum pipe pipe,
enum intel_pipe_crc_source *source, u32 *val)
{
- if (IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
return i8xx_pipe_crc_ctl_reg(source, val);
else if (DISPLAY_VER(dev_priv) < 5)
return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
@@ -539,7 +539,7 @@ static int
intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
const enum intel_pipe_crc_source source)
{
- if (IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
return i8xx_crc_source_valid(dev_priv, source);
else if (DISPLAY_VER(dev_priv) < 5)
return i9xx_crc_source_valid(dev_priv, source);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index bf8e4ede2a6c..85301e894378 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -782,7 +782,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
psr_max_h = 4096;
psr_max_v = 2304;
max_bpp = 24;
- } else if (IS_DISPLAY_VER(dev_priv, 9)) {
+ } else if (DISPLAY_VER(dev_priv) == 9) {
psr_max_h = 3640;
psr_max_v = 2304;
max_bpp = 24;
@@ -922,7 +922,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
hsw_psr_setup_aux(intel_dp);
- if (intel_dp->psr.psr2_enabled && IS_DISPLAY_VER(dev_priv, 9)) {
+ if (intel_dp->psr.psr2_enabled && DISPLAY_VER(dev_priv) == 9) {
i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
u32 chicken = intel_de_read(dev_priv, reg);
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 71b8edafb1c3..88085486ee59 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -28,7 +28,7 @@ tc_cold_get_power_domain(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- if (IS_DISPLAY_VER(i915, 11))
+ if (DISPLAY_VER(i915) == 11)
return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
else
return POWER_DOMAIN_TC_COLD_OFF;
@@ -40,7 +40,7 @@ tc_cold_block(struct intel_digital_port *dig_port)
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
enum intel_display_power_domain domain;
- if (IS_DISPLAY_VER(i915, 11) && !dig_port->tc_legacy_port)
+ if (DISPLAY_VER(i915) == 11 && !dig_port->tc_legacy_port)
return 0;
domain = tc_cold_get_power_domain(dig_port);
@@ -71,7 +71,7 @@ assert_tc_cold_blocked(struct intel_digital_port *dig_port)
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
bool enabled;
- if (IS_DISPLAY_VER(i915, 11) && !dig_port->tc_legacy_port)
+ if (DISPLAY_VER(i915) == 11 && !dig_port->tc_legacy_port)
return;
enabled = intel_display_power_is_enabled(i915,
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
index e558f121ec4e..2c5c77693474 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
@@ -1165,7 +1165,7 @@ intel_tv_get_config(struct intel_encoder *encoder,
static bool intel_tv_source_too_wide(struct drm_i915_private *dev_priv,
int hdisplay)
{
- return IS_DISPLAY_VER(dev_priv, 3) && hdisplay > 1024;
+ return DISPLAY_VER(dev_priv) == 3 && hdisplay > 1024;
}
static bool intel_tv_vert_scaling(const struct drm_display_mode *tv_mode,
@@ -1789,7 +1789,7 @@ intel_tv_get_modes(struct drm_connector *connector)
continue;
/* no vertical scaling with wide sources on gen3 */
- if (IS_DISPLAY_VER(dev_priv, 3) && input->w > 1024 &&
+ if (DISPLAY_VER(dev_priv) == 3 && input->w > 1024 &&
input->h > intel_tv_mode_vdisplay(tv_mode))
continue;
@@ -1978,7 +1978,7 @@ intel_tv_init(struct drm_i915_private *dev_priv)
/* Create TV properties then attach current values */
for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
/* 1080p50/1080p60 not supported on gen3 */
- if (IS_DISPLAY_VER(dev_priv, 3) &&
+ if (DISPLAY_VER(dev_priv) == 3 &&
tv_modes[i].oversample == 1)
break;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 098636c811a8..8a8e3b5e6ef0 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1208,7 +1208,7 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s
* than the cursor ending less than 4 pixels from the left edge of the
* screen may cause FIFO underflow and display corruption.
*/
- if (IS_DISPLAY_VER(dev_priv, 10) &&
+ if (DISPLAY_VER(dev_priv) == 10 &&
(crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
drm_dbg_kms(&dev_priv->drm,
"requested plane X %s position %d invalid (valid range %d-%d)\n",
@@ -1695,7 +1695,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
return false;
- if (IS_DISPLAY_VER(dev_priv, 9) && pipe == PIPE_C)
+ if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C)
return false;
if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
@@ -2007,8 +2007,8 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->check_plane = skl_plane_check;
if (plane_id == PLANE_PRIMARY) {
- plane->need_async_flip_disable_wa = IS_DISPLAY_RANGE(dev_priv,
- 9, 10);
+ plane->need_async_flip_disable_wa = IS_DISPLAY_VER(dev_priv,
+ 9, 10);
plane->async_flip = skl_plane_async_flip;
plane->enable_flip_done = skl_plane_enable_flip_done;
plane->disable_flip_done = skl_plane_disable_flip_done;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8c62bb2abd31..907c66efb469 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1238,9 +1238,8 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
#define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
-#define IS_DISPLAY_RANGE(i915, from, until) \
+#define IS_DISPLAY_VER(i915, from, until) \
(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
-#define IS_DISPLAY_VER(i915, v) (DISPLAY_VER(i915) == (v))
#define REVID_FOREVER 0xff
#define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 920327bdcb10..798ecc718e3f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -806,7 +806,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
vtotal /= 2;
- if (IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
else
position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
@@ -857,7 +857,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
int vbl_start, vbl_end, hsync_start, htotal, vtotal;
unsigned long irqflags;
bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 ||
- IS_G4X(dev_priv) || IS_DISPLAY_VER(dev_priv, 2) ||
+ IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) == 2 ||
crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
@@ -2077,7 +2077,7 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);
}
- if (IS_DISPLAY_VER(dev_priv, 5) && de_iir & DE_PCU_EVENT)
+ if (DISPLAY_VER(dev_priv) == 5 && de_iir & DE_PCU_EVENT)
gen5_rps_irq_handler(&dev_priv->gt.rps);
}
@@ -2287,10 +2287,10 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D;
- if (IS_CNL_WITH_PORT_F(dev_priv) || IS_DISPLAY_VER(dev_priv, 11))
+ if (IS_CNL_WITH_PORT_F(dev_priv) || DISPLAY_VER(dev_priv) == 11)
mask |= CNL_AUX_CHANNEL_F;
- if (IS_DISPLAY_VER(dev_priv, 11))
+ if (DISPLAY_VER(dev_priv) == 11)
mask |= ICL_AUX_CHANNEL_E;
return mask;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3f6d8b502a61..eaf4c072ade0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2339,7 +2339,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
if (IS_I945GM(dev_priv))
wm_info = &i945_wm_info;
- else if (!IS_DISPLAY_VER(dev_priv, 2))
+ else if (DISPLAY_VER(dev_priv) != 2)
wm_info = &i915_wm_info;
else
wm_info = &i830_a_wm_info;
@@ -2353,7 +2353,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
crtc->base.primary->state->fb;
int cpp;
- if (IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
cpp = 4;
else
cpp = fb->format->cpp[0];
@@ -2368,7 +2368,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
planea_wm = wm_info->max_wm;
}
- if (IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
wm_info = &i830_bc_wm_info;
fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
@@ -2380,7 +2380,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
crtc->base.primary->state->fb;
int cpp;
- if (IS_DISPLAY_VER(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
cpp = 4;
else
cpp = fb->format->cpp[0];
@@ -2967,7 +2967,7 @@ static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
u16 wm[5])
{
/* ILK sprite LP0 latency is 1300 ns */
- if (IS_DISPLAY_VER(dev_priv, 5))
+ if (DISPLAY_VER(dev_priv) == 5)
wm[0] = 13;
}
@@ -2975,7 +2975,7 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
u16 wm[5])
{
/* ILK cursor LP0 latency is 1300 ns */
- if (IS_DISPLAY_VER(dev_priv, 5))
+ if (DISPLAY_VER(dev_priv) == 5)
wm[0] = 13;
}
@@ -3105,7 +3105,7 @@ static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
- if (IS_DISPLAY_VER(dev_priv, 6)) {
+ if (DISPLAY_VER(dev_priv) == 6) {
snb_wm_latency_quirk(dev_priv);
snb_wm_lp3_irq_quirk(dev_priv);
}
@@ -3354,7 +3354,7 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv,
* What we should check here is whether FBC can be
* enabled sometime later.
*/
- if (IS_DISPLAY_VER(dev_priv, 5) && !merged->fbc_wm_enabled &&
+ if (DISPLAY_VER(dev_priv) == 5 && !merged->fbc_wm_enabled &&
intel_fbc_is_active(dev_priv)) {
for (level = 2; level <= max_level; level++) {
struct intel_wm_level *wm = &merged->wm[level];
@@ -3654,7 +3654,7 @@ u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
*/
static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
{
- return IS_DISPLAY_VER(dev_priv, 9);
+ return DISPLAY_VER(dev_priv) == 9;
}
static bool
@@ -3680,13 +3680,13 @@ skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
}
drm_dbg(&dev_priv->drm, "Couldn't read SAGV block time!\n");
- } else if (IS_DISPLAY_VER(dev_priv, 11)) {
+ } else if (DISPLAY_VER(dev_priv) == 11) {
dev_priv->sagv_block_time_us = 10;
return;
- } else if (IS_DISPLAY_VER(dev_priv, 10)) {
+ } else if (DISPLAY_VER(dev_priv) == 10) {
dev_priv->sagv_block_time_us = 20;
return;
- } else if (IS_DISPLAY_VER(dev_priv, 9)) {
+ } else if (DISPLAY_VER(dev_priv) == 9) {
dev_priv->sagv_block_time_us = 30;
return;
} else {
@@ -4613,9 +4613,9 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- if (IS_DISPLAY_VER(dev_priv, 12))
+ if (DISPLAY_VER(dev_priv) == 12)
return tgl_compute_dbuf_slices(pipe, active_pipes);
- else if (IS_DISPLAY_VER(dev_priv, 11))
+ else if (DISPLAY_VER(dev_priv) == 11)
return icl_compute_dbuf_slices(pipe, active_pipes);
/*
* For anything else just return one slice yet.
@@ -4986,7 +4986,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
* Wa_1408961008:icl, ehl
* Underruns with WM1+ disabled
*/
- if (IS_DISPLAY_VER(dev_priv, 11) &&
+ if (DISPLAY_VER(dev_priv) == 11 &&
level == 1 && wm->wm[0].enable) {
wm->wm[level].blocks = wm->wm[0].blocks;
wm->wm[level].lines = wm->wm[0].lines;
@@ -5245,7 +5245,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
(wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
selected_result = method2;
} else if (latency >= wp->linetime_us) {
- if (IS_DISPLAY_VER(dev_priv, 9))
+ if (DISPLAY_VER(dev_priv) == 9)
selected_result = min_fixed16(method1, method2);
else
selected_result = method2;
@@ -5258,7 +5258,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
lines = div_round_up_fixed16(selected_result,
wp->plane_blocks_per_line);
- if (IS_DISPLAY_VER(dev_priv, 9)) {
+ if (DISPLAY_VER(dev_priv) == 9) {
/* Display WA #1125: skl,bxt,kbl */
if (level == 0 && wp->rc_surface)
blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
@@ -5375,7 +5375,7 @@ static void skl_compute_transition_wm(struct drm_i915_private *dev_priv,
* WaDisableTWM:skl,kbl,cfl,bxt
* Transition WM are not recommended by HW team for GEN9
*/
- if (IS_DISPLAY_VER(dev_priv, 9))
+ if (DISPLAY_VER(dev_priv) == 9)
return;
if (DISPLAY_VER(dev_priv) >= 11)
@@ -5384,7 +5384,7 @@ static void skl_compute_transition_wm(struct drm_i915_private *dev_priv,
trans_min = 14;
/* Display WA #1140: glk,cnl */
- if (IS_DISPLAY_VER(dev_priv, 10))
+ if (DISPLAY_VER(dev_priv) == 10)
trans_amount = 0;
else
trans_amount = 10; /* This is configurable amount */
@@ -7694,9 +7694,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
} else if (HAS_PCH_SPLIT(dev_priv)) {
ilk_setup_wm_latency(dev_priv);
- if ((IS_DISPLAY_VER(dev_priv, 5) && dev_priv->wm.pri_latency[1] &&
+ if ((DISPLAY_VER(dev_priv) == 5 && dev_priv->wm.pri_latency[1] &&
dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
- (!IS_DISPLAY_VER(dev_priv, 5) && dev_priv->wm.pri_latency[0] &&
+ (DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
dev_priv->display.compute_intermediate_wm =
@@ -7739,12 +7739,12 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->display.update_wm = NULL;
} else
dev_priv->display.update_wm = pnv_update_wm;
- } else if (IS_DISPLAY_VER(dev_priv, 4)) {
+ } else if (DISPLAY_VER(dev_priv) == 4) {
dev_priv->display.update_wm = i965_update_wm;
- } else if (IS_DISPLAY_VER(dev_priv, 3)) {
+ } else if (DISPLAY_VER(dev_priv) == 3) {
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
- } else if (IS_DISPLAY_VER(dev_priv, 2)) {
+ } else if (DISPLAY_VER(dev_priv) == 2) {
if (INTEL_NUM_PIPES(dev_priv) == 1) {
dev_priv->display.update_wm = i845_update_wm;
dev_priv->display.get_fifo_size = i845_get_fifo_size;
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH v2 04/12] drm/i915: add macros for graphics and media versions
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
` (2 preceding siblings ...)
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 03/12] drm/i915/display: rename display version macros Lucas De Marchi
@ 2021-04-13 5:09 ` Lucas De Marchi
2021-04-13 9:33 ` Jani Nikula
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 05/12] drm/i915/gt: replace gen use in intel_engine_cs Lucas De Marchi
` (13 subsequent siblings)
17 siblings, 1 reply; 39+ messages in thread
From: Lucas De Marchi @ 2021-04-13 5:09 UTC (permalink / raw)
To: intel-gfx
Like it was done in
commit 01eb15c9165e ("drm/i915: Add DISPLAY_VER() and related macros")
add the correspondent macros for graphics and media. Going forward we
will prefer checking the versions for the specific IPs (graphics, media
and display) rather than grouping everything under a "gen" version.
For consistency and to make the maintenance easier, it'd be preferred
not to mix the *GEN* macros with the new ones. For older platforms we
can simply consider that the previous "gen" number will extend to all
3 IPs. Then we can start replacing its use in the driver. Right now this
replacement is not done and only the infrastructure is put in place.
We also leave gen and gen_mask inside struct intel_device_info while
it's still being used throughout the code.
v2: Repurpose IS_{GRAPHICS,MEDIA}_VER() macros to work with a range
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 15 ++++++++++++++-
drivers/gpu/drm/i915/i915_pci.c | 7 ++++++-
drivers/gpu/drm/i915/intel_device_info.h | 3 +++
3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 907c66efb469..cb59eb0f6c5b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1234,9 +1234,22 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
-#define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
+/*
+ * Deprecated: this will be replaced by individual IP checks:
+ * GRAPHICS_VER(), MEDIA_VER and DISPLAY_VER()
+ */
+#define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
+
+#define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics_ver)
+#define IS_GRAPHICS_VER(i915, from, until) \
+ (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
+
+#define MEDIA_VER(i915) (INTEL_INFO(i915)->media_ver)
+#define IS_MEDIA_VER(i915, from, until) \
+ (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
+
#define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
#define IS_DISPLAY_VER(i915, from, until) \
(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index ce5cbeaf036d..97ab73276334 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -36,7 +36,12 @@
#include "i915_selftest.h"
#define PLATFORM(x) .platform = (x)
-#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1), .display.ver = (x)
+#define GEN(x) \
+ .gen_mask = BIT((x) - 1), \
+ .gen = (x), \
+ .graphics_ver = (x), \
+ .media_ver = (x), \
+ .display.ver = (x)
#define I845_PIPE_OFFSETS \
.pipe_offsets = { \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index b16c75927a12..405883a8cc84 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -162,6 +162,9 @@ enum intel_ppgtt_type {
struct intel_device_info {
u16 gen_mask;
+ u8 graphics_ver;
+ u8 media_ver;
+
u8 gen;
u8 gt; /* GT number, 0 if undefined */
intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH v2 05/12] drm/i915/gt: replace gen use in intel_engine_cs
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
` (3 preceding siblings ...)
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 04/12] drm/i915: add macros for graphics and media versions Lucas De Marchi
@ 2021-04-13 5:09 ` Lucas De Marchi
2021-04-13 9:36 ` Jani Nikula
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 06/12] drm/i915/selftests: replace unused mask with simple version Lucas De Marchi
` (12 subsequent siblings)
17 siblings, 1 reply; 39+ messages in thread
From: Lucas De Marchi @ 2021-04-13 5:09 UTC (permalink / raw)
To: intel-gfx
Start using the new fields graphics_version for the previous gen checks.
Here we rename the "gen" field and replace the comparisons using it to
start using the new GRAPHICS_VER(). Other uses of INTEL_GEN() were left
as is for automatic conversion later.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 40 ++++++++++----------
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 18 ++++-----
2 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index efe935f80c1a..6dbdbde00f14 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -45,9 +45,9 @@ struct engine_info {
unsigned int hw_id;
u8 class;
u8 instance;
- /* mmio bases table *must* be sorted in reverse gen order */
+ /* mmio bases table *must* be sorted in reverse graphics_ver order */
struct engine_mmio_base {
- u32 gen : 8;
+ u32 graphics_ver : 8;
u32 base : 24;
} mmio_bases[MAX_MMIO_BASES];
};
@@ -58,7 +58,7 @@ static const struct engine_info intel_engines[] = {
.class = RENDER_CLASS,
.instance = 0,
.mmio_bases = {
- { .gen = 1, .base = RENDER_RING_BASE }
+ { .graphics_ver = 1, .base = RENDER_RING_BASE }
},
},
[BCS0] = {
@@ -66,7 +66,7 @@ static const struct engine_info intel_engines[] = {
.class = COPY_ENGINE_CLASS,
.instance = 0,
.mmio_bases = {
- { .gen = 6, .base = BLT_RING_BASE }
+ { .graphics_ver = 6, .base = BLT_RING_BASE }
},
},
[VCS0] = {
@@ -74,9 +74,9 @@ static const struct engine_info intel_engines[] = {
.class = VIDEO_DECODE_CLASS,
.instance = 0,
.mmio_bases = {
- { .gen = 11, .base = GEN11_BSD_RING_BASE },
- { .gen = 6, .base = GEN6_BSD_RING_BASE },
- { .gen = 4, .base = BSD_RING_BASE }
+ { .graphics_ver = 11, .base = GEN11_BSD_RING_BASE },
+ { .graphics_ver = 6, .base = GEN6_BSD_RING_BASE },
+ { .graphics_ver = 4, .base = BSD_RING_BASE }
},
},
[VCS1] = {
@@ -84,8 +84,8 @@ static const struct engine_info intel_engines[] = {
.class = VIDEO_DECODE_CLASS,
.instance = 1,
.mmio_bases = {
- { .gen = 11, .base = GEN11_BSD2_RING_BASE },
- { .gen = 8, .base = GEN8_BSD2_RING_BASE }
+ { .graphics_ver = 11, .base = GEN11_BSD2_RING_BASE },
+ { .graphics_ver = 8, .base = GEN8_BSD2_RING_BASE }
},
},
[VCS2] = {
@@ -93,7 +93,7 @@ static const struct engine_info intel_engines[] = {
.class = VIDEO_DECODE_CLASS,
.instance = 2,
.mmio_bases = {
- { .gen = 11, .base = GEN11_BSD3_RING_BASE }
+ { .graphics_ver = 11, .base = GEN11_BSD3_RING_BASE }
},
},
[VCS3] = {
@@ -101,7 +101,7 @@ static const struct engine_info intel_engines[] = {
.class = VIDEO_DECODE_CLASS,
.instance = 3,
.mmio_bases = {
- { .gen = 11, .base = GEN11_BSD4_RING_BASE }
+ { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE }
},
},
[VECS0] = {
@@ -109,8 +109,8 @@ static const struct engine_info intel_engines[] = {
.class = VIDEO_ENHANCEMENT_CLASS,
.instance = 0,
.mmio_bases = {
- { .gen = 11, .base = GEN11_VEBOX_RING_BASE },
- { .gen = 7, .base = VEBOX_RING_BASE }
+ { .graphics_ver = 11, .base = GEN11_VEBOX_RING_BASE },
+ { .graphics_ver = 7, .base = VEBOX_RING_BASE }
},
},
[VECS1] = {
@@ -118,7 +118,7 @@ static const struct engine_info intel_engines[] = {
.class = VIDEO_ENHANCEMENT_CLASS,
.instance = 1,
.mmio_bases = {
- { .gen = 11, .base = GEN11_VEBOX2_RING_BASE }
+ { .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE }
},
},
};
@@ -146,9 +146,9 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
switch (class) {
case RENDER_CLASS:
- switch (INTEL_GEN(gt->i915)) {
+ switch (GRAPHICS_VER(gt->i915)) {
default:
- MISSING_CASE(INTEL_GEN(gt->i915));
+ MISSING_CASE(GRAPHICS_VER(gt->i915));
return DEFAULT_LR_CONTEXT_RENDER_SIZE;
case 12:
case 11:
@@ -184,8 +184,8 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
*/
cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
drm_dbg(>->i915->drm,
- "gen%d CXT_SIZE = %d bytes [0x%08x]\n",
- INTEL_GEN(gt->i915), cxt_size * 64,
+ "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n",
+ GRAPHICS_VER(gt->i915), cxt_size * 64,
cxt_size - 1);
return round_up(cxt_size * 64, PAGE_SIZE);
case 3:
@@ -201,7 +201,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
case VIDEO_DECODE_CLASS:
case VIDEO_ENHANCEMENT_CLASS:
case COPY_ENGINE_CLASS:
- if (INTEL_GEN(gt->i915) < 8)
+ if (GRAPHICS_VER(gt->i915) < 8)
return 0;
return GEN8_LR_CONTEXT_OTHER_SIZE;
}
@@ -213,7 +213,7 @@ static u32 __engine_mmio_base(struct drm_i915_private *i915,
int i;
for (i = 0; i < MAX_MMIO_BASES; i++)
- if (INTEL_GEN(i915) >= bases[i].gen)
+ if (GRAPHICS_VER(i915) >= bases[i].graphics_ver)
break;
GEM_BUG_ON(i == MAX_MMIO_BASES);
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index b32814a1f20b..3453eb77c498 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -376,34 +376,34 @@ static int intel_mmio_bases_check(void *arg)
u8 prev = U8_MAX;
for (j = 0; j < MAX_MMIO_BASES; j++) {
- u8 gen = info->mmio_bases[j].gen;
+ u8 ver = info->mmio_bases[j].graphics_ver;
u32 base = info->mmio_bases[j].base;
- if (gen >= prev) {
- pr_err("%s(%s, class:%d, instance:%d): mmio base for gen %x is before the one for gen %x\n",
+ if (ver >= prev) {
+ pr_err("%s(%s, class:%d, instance:%d): mmio base for graphics ver %u is before the one for ver %u\n",
__func__,
intel_engine_class_repr(info->class),
info->class, info->instance,
- prev, gen);
+ prev, ver);
return -EINVAL;
}
- if (gen == 0)
+ if (ver == 0)
break;
if (!base) {
- pr_err("%s(%s, class:%d, instance:%d): invalid mmio base (%x) for gen %x at entry %u\n",
+ pr_err("%s(%s, class:%d, instance:%d): invalid mmio base (%x) for graphics ver %u at entry %u\n",
__func__,
intel_engine_class_repr(info->class),
info->class, info->instance,
- base, gen, j);
+ base, ver, j);
return -EINVAL;
}
- prev = gen;
+ prev = ver;
}
- pr_debug("%s: min gen supported for %s%d is %d\n",
+ pr_debug("%s: min graphics version supported for %s%d is %u\n",
__func__,
intel_engine_class_repr(info->class),
info->instance,
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH v2 06/12] drm/i915/selftests: replace unused mask with simple version
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
` (4 preceding siblings ...)
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 05/12] drm/i915/gt: replace gen use in intel_engine_cs Lucas De Marchi
@ 2021-04-13 5:09 ` Lucas De Marchi
2021-04-13 9:36 ` Jani Nikula
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 07/12] drm/i915/selftests: eliminate use of gen_mask Lucas De Marchi
` (11 subsequent siblings)
17 siblings, 1 reply; 39+ messages in thread
From: Lucas De Marchi @ 2021-04-13 5:09 UTC (permalink / raw)
To: intel-gfx
Since its introduction 2 years ago, we never used the mask to span more
than one gen. Replace gen_mask a single number and start using the new
GRAPHICS_VER().
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_workarounds.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 19850489a3fc..64937ec3f2dc 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -927,7 +927,7 @@ static int scrub_whitelisted_registers(struct intel_context *ce)
struct regmask {
i915_reg_t reg;
- unsigned long gen_mask;
+ u8 graphics_ver;
};
static bool find_reg(struct drm_i915_private *i915,
@@ -938,7 +938,7 @@ static bool find_reg(struct drm_i915_private *i915,
u32 offset = i915_mmio_reg_offset(reg);
while (count--) {
- if (INTEL_INFO(i915)->gen_mask & tbl->gen_mask &&
+ if (GRAPHICS_VER(i915) == tbl->graphics_ver &&
i915_mmio_reg_offset(tbl->reg) == offset)
return true;
tbl++;
@@ -951,8 +951,8 @@ static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)
{
/* Alas, we must pardon some whitelists. Mistakes already made */
static const struct regmask pardon[] = {
- { GEN9_CTX_PREEMPT_REG, INTEL_GEN_MASK(9, 9) },
- { GEN8_L3SQCREG4, INTEL_GEN_MASK(9, 9) },
+ { GEN9_CTX_PREEMPT_REG, 9 },
+ { GEN8_L3SQCREG4, 9 },
};
return find_reg(i915, reg, pardon, ARRAY_SIZE(pardon));
@@ -974,7 +974,7 @@ static bool writeonly_reg(struct drm_i915_private *i915, i915_reg_t reg)
{
/* Some registers do not seem to behave and our writes unreadable */
static const struct regmask wo[] = {
- { GEN9_SLICE_COMMON_ECO_CHICKEN1, INTEL_GEN_MASK(9, 9) },
+ { GEN9_SLICE_COMMON_ECO_CHICKEN1, 9 },
};
return find_reg(i915, reg, wo, ARRAY_SIZE(wo));
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH v2 07/12] drm/i915/selftests: eliminate use of gen_mask
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
` (5 preceding siblings ...)
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 06/12] drm/i915/selftests: replace unused mask with simple version Lucas De Marchi
@ 2021-04-13 5:09 ` Lucas De Marchi
2021-04-13 9:38 ` Jani Nikula
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 08/12] drm/i915: finish removal " Lucas De Marchi
` (10 subsequent siblings)
17 siblings, 1 reply; 39+ messages in thread
From: Lucas De Marchi @ 2021-04-13 5:09 UTC (permalink / raw)
To: intel-gfx
Remove the remaining uses of INTEL_GEN_MASK() and the correspondent
gen_mask in struct intel_device_info. This will allow the removal of
gen_mask later since it's incompatible with the new per-IP versioning
scheme.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 8 +++++---
drivers/gpu/drm/i915/selftests/intel_uncore.c | 8 +++++---
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 661b50191f2b..ed5abe7be498 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2008,12 +2008,14 @@ void intel_uncore_fini_mmio(struct intel_uncore *uncore)
static const struct reg_whitelist {
i915_reg_t offset_ldw;
i915_reg_t offset_udw;
- u16 gen_mask;
+ u8 min_graphics_ver;
+ u8 max_graphics_ver;
u8 size;
} reg_read_whitelist[] = { {
.offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
- .gen_mask = INTEL_GEN_MASK(4, 12),
+ .min_graphics_ver = 4,
+ .max_graphics_ver = 12,
.size = 8
} };
@@ -2038,7 +2040,7 @@ int i915_reg_read_ioctl(struct drm_device *dev,
GEM_BUG_ON(entry->size > 8);
GEM_BUG_ON(entry_offset & (entry->size - 1));
- if (INTEL_INFO(i915)->gen_mask & entry->gen_mask &&
+ if (IS_GRAPHICS_VER(i915, entry->min_graphics_ver, entry->max_graphics_ver) &&
entry_offset == (reg->offset & -entry->size))
break;
entry++;
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 0e4e6be0101d..f76c9bcec735 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -125,17 +125,19 @@ static int live_forcewake_ops(void *arg)
{
static const struct reg {
const char *name;
+ u8 min_graphics_ver;
+ u8 max_graphics_ver;
unsigned long platforms;
unsigned int offset;
} registers[] = {
{
"RING_START",
- INTEL_GEN_MASK(6, 7),
+ 6, 7,
0x38,
},
{
"RING_MI_MODE",
- INTEL_GEN_MASK(8, BITS_PER_LONG),
+ 8, U8_MAX,
0x9c,
}
};
@@ -170,7 +172,7 @@ static int live_forcewake_ops(void *arg)
/* We have to pick carefully to get the exact behaviour we need */
for (r = registers; r->name; r++)
- if (r->platforms & INTEL_INFO(gt->i915)->gen_mask)
+ if (IS_GRAPHICS_VER(gt->i915, r->min_graphics_ver, r->max_graphics_ver))
break;
if (!r->name) {
pr_debug("Forcewaked register not known for %s; skipping\n",
--
2.31.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH v2 08/12] drm/i915: finish removal of gen_mask
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
` (6 preceding siblings ...)
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 07/12] drm/i915/selftests: eliminate use of gen_mask Lucas De Marchi
@ 2021-04-13 5:09 ` Lucas De Marchi
2021-04-13 9:40 ` Jani Nikula
2021-04-14 11:38 ` Tvrtko Ursulin
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 09/12] drm/i915: eliminate remaining uses of intel_device_info->gen Lucas De Marchi
` (9 subsequent siblings)
17 siblings, 2 replies; 39+ messages in thread
From: Lucas De Marchi @ 2021-04-13 5:09 UTC (permalink / raw)
To: intel-gfx
Now that it's not used anywhere, remove it from struct
intel_device_info. To allow a period in which code will be converted to
the new macro, keep IS_GEN_RANGE() around, just redefining it to use
the new fields. The size advantage from IS_GEN_RANGE() using a mask is
not that big as it has pretty limited use througout the driver:
text data bss dec hex filename
2758497 95965 6496 2860958 2ba79e drivers/gpu/drm/i915/i915.ko.old
2758586 95953 6496 2861035 2ba7eb drivers/gpu/drm/i915/i915.ko.new
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 --
drivers/gpu/drm/i915/i915_drv.h | 13 ++++---------
drivers/gpu/drm/i915/i915_pci.c | 1 -
drivers/gpu/drm/i915/intel_device_info.h | 2 --
4 files changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 305557e1942a..825b45cb3543 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -768,8 +768,6 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
memcpy(device_info, match_info, sizeof(*device_info));
RUNTIME_INFO(i915)->device_id = pdev->device;
- BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
-
return i915;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cb59eb0f6c5b..b984a340b21f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1241,6 +1241,10 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
* GRAPHICS_VER(), MEDIA_VER and DISPLAY_VER()
*/
#define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
+/*
+ * Deprecated: use IS_GRAPHICS_VER()
+ */
+#define IS_GEN_RANGE(dev_priv, s, e) IS_GRAPHICS_VER(dev_priv, (s), (e))
#define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics_ver)
#define IS_GRAPHICS_VER(i915, from, until) \
@@ -1257,15 +1261,6 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
#define REVID_FOREVER 0xff
#define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
-#define INTEL_GEN_MASK(s, e) ( \
- BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
- BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
- GENMASK((e) - 1, (s) - 1))
-
-/* Returns true if Gen is in inclusive range [Start, End] */
-#define IS_GEN_RANGE(dev_priv, s, e) \
- (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
-
#define IS_GEN(dev_priv, n) \
(BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
INTEL_INFO(dev_priv)->gen == (n))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 97ab73276334..3b9cd1af0f28 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -37,7 +37,6 @@
#define PLATFORM(x) .platform = (x)
#define GEN(x) \
- .gen_mask = BIT((x) - 1), \
.gen = (x), \
.graphics_ver = (x), \
.media_ver = (x), \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 405883a8cc84..b8f7b996f140 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -160,8 +160,6 @@ enum intel_ppgtt_type {
func(supports_tv);
struct intel_device_info {
- u16 gen_mask;
-
u8 graphics_ver;
u8 media_ver;
--
2.31.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH v2 09/12] drm/i915: eliminate remaining uses of intel_device_info->gen
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
` (7 preceding siblings ...)
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 08/12] drm/i915: finish removal " Lucas De Marchi
@ 2021-04-13 5:09 ` Lucas De Marchi
2021-04-13 9:43 ` Jani Nikula
2021-04-13 5:10 ` [Intel-gfx] [PATCH v2 10/12] drm/i915: finish removal of gen from intel_device_info Lucas De Marchi
` (8 subsequent siblings)
17 siblings, 1 reply; 39+ messages in thread
From: Lucas De Marchi @ 2021-04-13 5:09 UTC (permalink / raw)
To: intel-gfx
Replace gen with the new graphics_ver value and use GRAPHICS_VER()
in those places.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 22 +++++++++----------
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 5964e67c7d36..297143511f99 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -274,7 +274,7 @@ struct i915_execbuffer {
struct drm_mm_node node; /** temporary GTT binding */
unsigned long vaddr; /** Current kmap address */
unsigned long page; /** Currently mapped page index */
- unsigned int gen; /** Cached value of INTEL_GEN */
+ unsigned int graphics_ver; /** Cached value of GRAPHICS_VER */
bool use_64bit_reloc : 1;
bool has_llc : 1;
bool has_fence : 1;
@@ -1049,10 +1049,10 @@ static void reloc_cache_init(struct reloc_cache *cache,
cache->page = -1;
cache->vaddr = 0;
/* Must be a variable in the struct to allow GCC to unroll. */
- cache->gen = INTEL_GEN(i915);
+ cache->graphics_ver = GRAPHICS_VER(i915);
cache->has_llc = HAS_LLC(i915);
cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
- cache->has_fence = cache->gen < 4;
+ cache->has_fence = cache->graphics_ver < 4;
cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
cache->node.flags = 0;
reloc_cache_clear(cache);
@@ -1402,7 +1402,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
err = eb->engine->emit_bb_start(rq,
batch->node.start, PAGE_SIZE,
- cache->gen > 5 ? 0 : I915_DISPATCH_SECURE);
+ cache->graphics_ver > 5 ? 0 : I915_DISPATCH_SECURE);
if (err)
goto skip_request;
@@ -1503,14 +1503,14 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb,
u64 offset,
u64 target_addr)
{
- const unsigned int gen = eb->reloc_cache.gen;
+ const unsigned int ver = eb->reloc_cache.graphics_ver;
unsigned int len;
u32 *batch;
u64 addr;
- if (gen >= 8)
+ if (ver >= 8)
len = offset & 7 ? 8 : 5;
- else if (gen >= 4)
+ else if (ver >= 4)
len = 4;
else
len = 3;
@@ -1522,7 +1522,7 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb,
return false;
addr = gen8_canonical_addr(vma->node.start + offset);
- if (gen >= 8) {
+ if (ver >= 8) {
if (offset & 7) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
*batch++ = lower_32_bits(addr);
@@ -1542,7 +1542,7 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb,
*batch++ = lower_32_bits(target_addr);
*batch++ = upper_32_bits(target_addr);
}
- } else if (gen >= 6) {
+ } else if (ver >= 6) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
*batch++ = 0;
*batch++ = addr;
@@ -1552,12 +1552,12 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb,
*batch++ = 0;
*batch++ = vma_phys_addr(vma, offset);
*batch++ = target_addr;
- } else if (gen >= 4) {
+ } else if (ver >= 4) {
*batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*batch++ = 0;
*batch++ = addr;
*batch++ = target_addr;
- } else if (gen >= 3 &&
+ } else if (ver >= 3 &&
!(IS_I915G(eb->i915) || IS_I915GM(eb->i915))) {
*batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
*batch++ = addr;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 825b45cb3543..e477d278ca73 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -794,7 +794,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
return PTR_ERR(i915);
/* Disable nuclear pageflip by default on pre-ILK */
- if (!i915->params.nuclear_pageflip && match_info->gen < 5)
+ if (!i915->params.nuclear_pageflip && match_info->graphics_ver < 5)
i915->drm.driver_features &= ~DRIVER_ATOMIC;
/*
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index de02207f6ec6..b58bc7bff65e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -95,7 +95,7 @@ static const char *iommu_name(void)
void intel_device_info_print_static(const struct intel_device_info *info,
struct drm_printer *p)
{
- drm_printf(p, "gen: %d\n", info->gen);
+ drm_printf(p, "graphics_ver: %u\n", info->graphics_ver);
drm_printf(p, "gt: %d\n", info->gt);
drm_printf(p, "iommu: %s\n", iommu_name());
drm_printf(p, "memory-regions: %x\n", info->memory_regions);
--
2.31.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH v2 10/12] drm/i915: finish removal of gen from intel_device_info
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
` (8 preceding siblings ...)
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 09/12] drm/i915: eliminate remaining uses of intel_device_info->gen Lucas De Marchi
@ 2021-04-13 5:10 ` Lucas De Marchi
2021-04-13 9:45 ` Jani Nikula
2021-04-13 5:10 ` [Intel-gfx] [PATCH v2 11/12] drm/i915: add media and display versions to device_info print Lucas De Marchi
` (7 subsequent siblings)
17 siblings, 1 reply; 39+ messages in thread
From: Lucas De Marchi @ 2021-04-13 5:10 UTC (permalink / raw)
To: intel-gfx
Now that it's not being used anymore, finish its removal. Like for
gen_mask, we replace INTEL_GEN() and IS_GEN() macros to use the new
field.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 10 +++++-----
drivers/gpu/drm/i915/i915_pci.c | 1 -
drivers/gpu/drm/i915/intel_device_info.h | 1 -
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
4 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b984a340b21f..549ce0ce5bde 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1240,11 +1240,15 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
* Deprecated: this will be replaced by individual IP checks:
* GRAPHICS_VER(), MEDIA_VER and DISPLAY_VER()
*/
-#define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
+#define INTEL_GEN(dev_priv) GRAPHICS_VER(dev_priv)
/*
* Deprecated: use IS_GRAPHICS_VER()
*/
#define IS_GEN_RANGE(dev_priv, s, e) IS_GRAPHICS_VER(dev_priv, (s), (e))
+/*
+ * Deprecated: use GRAPHICS_VER()
+ */
+#define IS_GEN(dev_priv, n) (GRAPHICS_VER(dev_priv) == (n))
#define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics_ver)
#define IS_GRAPHICS_VER(i915, from, until) \
@@ -1261,10 +1265,6 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
#define REVID_FOREVER 0xff
#define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
-#define IS_GEN(dev_priv, n) \
- (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
- INTEL_INFO(dev_priv)->gen == (n))
-
#define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
/*
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 3b9cd1af0f28..1453c1436f31 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -37,7 +37,6 @@
#define PLATFORM(x) .platform = (x)
#define GEN(x) \
- .gen = (x), \
.graphics_ver = (x), \
.media_ver = (x), \
.display.ver = (x)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index b8f7b996f140..8ab4fa6c7fdd 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -163,7 +163,6 @@ struct intel_device_info {
u8 graphics_ver;
u8 media_ver;
- u8 gen;
u8 gt; /* GT number, 0 if undefined */
intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 0188f877cab2..2ffc763fe90d 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -162,7 +162,7 @@ struct drm_i915_private *mock_gem_device(void)
/* Using the global GTT may ask questions about KMS users, so prepare */
drm_mode_config_init(&i915->drm);
- mkwrite_device_info(i915)->gen = -1;
+ mkwrite_device_info(i915)->graphics_ver = -1;
mkwrite_device_info(i915)->page_sizes =
I915_GTT_PAGE_SIZE_4K |
--
2.31.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH v2 11/12] drm/i915: add media and display versions to device_info print
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
` (9 preceding siblings ...)
2021-04-13 5:10 ` [Intel-gfx] [PATCH v2 10/12] drm/i915: finish removal of gen from intel_device_info Lucas De Marchi
@ 2021-04-13 5:10 ` Lucas De Marchi
2021-04-13 9:46 ` Jani Nikula
2021-04-13 5:10 ` [Intel-gfx] [PATCH v2 12/12] drm/i915: split dgfx features from gen 12 Lucas De Marchi
` (6 subsequent siblings)
17 siblings, 1 reply; 39+ messages in thread
From: Lucas De Marchi @ 2021-04-13 5:10 UTC (permalink / raw)
To: intel-gfx
Since we are now converting from a single gen version to graphics_ver,
media_ver and display_ver, add the last 2 when printing the device info.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_device_info.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index b58bc7bff65e..6a351a709417 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -96,6 +96,8 @@ void intel_device_info_print_static(const struct intel_device_info *info,
struct drm_printer *p)
{
drm_printf(p, "graphics_ver: %u\n", info->graphics_ver);
+ drm_printf(p, "media_ver: %u\n", info->media_ver);
+ drm_printf(p, "display_ver: %u\n", info->display.ver);
drm_printf(p, "gt: %d\n", info->gt);
drm_printf(p, "iommu: %s\n", iommu_name());
drm_printf(p, "memory-regions: %x\n", info->memory_regions);
--
2.31.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH v2 12/12] drm/i915: split dgfx features from gen 12
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
` (10 preceding siblings ...)
2021-04-13 5:10 ` [Intel-gfx] [PATCH v2 11/12] drm/i915: add media and display versions to device_info print Lucas De Marchi
@ 2021-04-13 5:10 ` Lucas De Marchi
2021-04-13 9:47 ` Jani Nikula
2021-04-13 5:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Extend GEN renames to the rest of the driver (rev3) Patchwork
` (5 subsequent siblings)
17 siblings, 1 reply; 39+ messages in thread
From: Lucas De Marchi @ 2021-04-13 5:10 UTC (permalink / raw)
To: intel-gfx
Make them independent so we can use DGFX_FEATURES more generically.
For future platforms that do not use the GEN nomenclature we will define
graphics, media and display separately, so we avoid setting graphics_ver
with the GEN() macro.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1453c1436f31..44e7b94db63d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -907,8 +907,7 @@ static const struct intel_device_info rkl_info = {
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
};
-#define GEN12_DGFX_FEATURES \
- GEN12_FEATURES, \
+#define DGFX_FEATURES \
.memory_regions = REGION_SMEM | REGION_LMEM, \
.has_master_unit_irq = 1, \
.has_llc = 0, \
@@ -916,7 +915,8 @@ static const struct intel_device_info rkl_info = {
.is_dgfx = 1
static const struct intel_device_info dg1_info __maybe_unused = {
- GEN12_DGFX_FEATURES,
+ GEN12_FEATURES,
+ DGFX_FEATURES,
PLATFORM(INTEL_DG1),
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
.require_force_probe = 1,
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Extend GEN renames to the rest of the driver (rev3)
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
` (11 preceding siblings ...)
2021-04-13 5:10 ` [Intel-gfx] [PATCH v2 12/12] drm/i915: split dgfx features from gen 12 Lucas De Marchi
@ 2021-04-13 5:43 ` Patchwork
2021-04-13 5:45 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (4 subsequent siblings)
17 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2021-04-13 5:43 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Extend GEN renames to the rest of the driver (rev3)
URL : https://patchwork.freedesktop.org/series/88825/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8c34aa8e267d drm/i915/display: use DISPLAY_VER() on remaining users
7503616b85f4 drm/i915: rename display.version to display.ver
-:51: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects?
#51: FILE: drivers/gpu/drm/i915/i915_pci.c:39:
+#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1), .display.ver = (x)
total: 0 errors, 0 warnings, 1 checks, 32 lines checked
a6f37e3b5ecd drm/i915/display: rename display version macros
-:1344: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#1344: FILE: drivers/gpu/drm/i915/i915_drv.h:1241:
+#define IS_DISPLAY_VER(i915, from, until) \
(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
total: 0 errors, 0 warnings, 1 checks, 1248 lines checked
87272d4c4a0b drm/i915: add macros for graphics and media versions
-:46: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#46: FILE: drivers/gpu/drm/i915/i915_drv.h:1246:
+#define IS_GRAPHICS_VER(i915, from, until) \
+ (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
-:50: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#50: FILE: drivers/gpu/drm/i915/i915_drv.h:1250:
+#define IS_MEDIA_VER(i915, from, until) \
+ (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
-:65: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects?
#65: FILE: drivers/gpu/drm/i915/i915_pci.c:39:
+#define GEN(x) \
+ .gen_mask = BIT((x) - 1), \
+ .gen = (x), \
+ .graphics_ver = (x), \
+ .media_ver = (x), \
+ .display.ver = (x)
total: 0 errors, 0 warnings, 3 checks, 45 lines checked
da39207e3437 drm/i915/gt: replace gen use in intel_engine_cs
d41b73f73091 drm/i915/selftests: replace unused mask with simple version
155bdc7709bd drm/i915/selftests: eliminate use of gen_mask
ebc4cd343cf5 drm/i915: finish removal of gen_mask
9ca0c826016d drm/i915: eliminate remaining uses of intel_device_info->gen
5f54af83f769 drm/i915: finish removal of gen from intel_device_info
2a9ae3289b71 drm/i915: add media and display versions to device_info print
387aa72e151b drm/i915: split dgfx features from gen 12
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Extend GEN renames to the rest of the driver (rev3)
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
` (12 preceding siblings ...)
2021-04-13 5:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Extend GEN renames to the rest of the driver (rev3) Patchwork
@ 2021-04-13 5:45 ` Patchwork
2021-04-13 5:48 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
` (3 subsequent siblings)
17 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2021-04-13 5:45 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Extend GEN renames to the rest of the driver (rev3)
URL : https://patchwork.freedesktop.org/series/88825/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1329:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1203:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Extend GEN renames to the rest of the driver (rev3)
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
` (13 preceding siblings ...)
2021-04-13 5:45 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-04-13 5:48 ` Patchwork
2021-04-13 6:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
17 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2021-04-13 5:48 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Extend GEN renames to the rest of the driver (rev3)
URL : https://patchwork.freedesktop.org/series/88825/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Extend GEN renames to the rest of the driver (rev3)
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
` (14 preceding siblings ...)
2021-04-13 5:48 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
@ 2021-04-13 6:10 ` Patchwork
2021-04-13 7:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-04-13 10:03 ` [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Jani Nikula
17 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2021-04-13 6:10 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 2944 bytes --]
== Series Details ==
Series: drm/i915: Extend GEN renames to the rest of the driver (rev3)
URL : https://patchwork.freedesktop.org/series/88825/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9962 -> Patchwork_19918
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/index.html
Known issues
------------
Here are the changes found in Patchwork_19918 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +27 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/fi-bdw-5557u/igt@amdgpu/amd_basic@semaphore.html
* igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u: NOTRUN -> [WARN][2] ([i915#2283])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/fi-bdw-5557u/igt@core_hotunplug@unbind-rebind.html
* igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
Participating hosts (47 -> 41)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-icl-y fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9962 -> Patchwork_19918
CI-20190529: 20190529
CI_DRM_9962: 2847b855cf291d61694ccfefa4f37d74d61f752b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6063: d3b7f74ce5df6fdea03e490b7c64f0c6bfe76f03 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19918: 387aa72e151b334331ea0fd17725949fd25b0cfb @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
387aa72e151b drm/i915: split dgfx features from gen 12
2a9ae3289b71 drm/i915: add media and display versions to device_info print
5f54af83f769 drm/i915: finish removal of gen from intel_device_info
9ca0c826016d drm/i915: eliminate remaining uses of intel_device_info->gen
ebc4cd343cf5 drm/i915: finish removal of gen_mask
155bdc7709bd drm/i915/selftests: eliminate use of gen_mask
d41b73f73091 drm/i915/selftests: replace unused mask with simple version
da39207e3437 drm/i915/gt: replace gen use in intel_engine_cs
87272d4c4a0b drm/i915: add macros for graphics and media versions
a6f37e3b5ecd drm/i915/display: rename display version macros
7503616b85f4 drm/i915: rename display.version to display.ver
8c34aa8e267d drm/i915/display: use DISPLAY_VER() on remaining users
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/index.html
[-- Attachment #1.2: Type: text/html, Size: 3731 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Extend GEN renames to the rest of the driver (rev3)
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
` (15 preceding siblings ...)
2021-04-13 6:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-04-13 7:29 ` Patchwork
2021-04-13 10:03 ` [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Jani Nikula
17 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2021-04-13 7:29 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30284 bytes --]
== Series Details ==
Series: drm/i915: Extend GEN renames to the rest of the driver (rev3)
URL : https://patchwork.freedesktop.org/series/88825/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9962_full -> Patchwork_19918_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_19918_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@drm_import_export@flink:
- shard-kbl: [PASS][1] -> [INCOMPLETE][2] ([i915#2369])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-kbl2/igt@drm_import_export@flink.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl2/igt@drm_import_export@flink.html
* igt@gem_busy@close-race:
- shard-skl: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-skl5/igt@gem_busy@close-race.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-skl5/igt@gem_busy@close-race.html
* igt@gem_ctx_persistence@clone:
- shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-snb6/igt@gem_ctx_persistence@clone.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][6] ([i915#2846])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl8/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-kbl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][9] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb1/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-tglb6/igt@gem_exec_fair@basic-pace@vcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-tglb2/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: NOTRUN -> [FAIL][12] ([i915#2842])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-glk7/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][15] ([i915#2658])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl8/igt@gem_pread@exhaustion.html
* igt@gem_softpin@full:
- shard-snb: NOTRUN -> [SKIP][16] ([fdo#109271]) +60 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-snb6/igt@gem_softpin@full.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#3323])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl8/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@input-checking:
- shard-kbl: NOTRUN -> [DMESG-WARN][18] ([i915#3002])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl7/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@process-exit-mmap-busy@wc:
- shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#1699]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl8/igt@gem_userptr_blits@process-exit-mmap-busy@wc.html
* igt@gem_userptr_blits@process-exit-mmap@gtt:
- shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#1699]) +3 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl7/igt@gem_userptr_blits@process-exit-mmap@gtt.html
* igt@gem_userptr_blits@set-cache-level:
- shard-iclb: NOTRUN -> [FAIL][21] ([i915#3324])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb7/igt@gem_userptr_blits@set-cache-level.html
* igt@gen9_exec_parse@batch-zero-length:
- shard-iclb: NOTRUN -> [SKIP][22] ([fdo#112306])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb7/igt@gen9_exec_parse@batch-zero-length.html
* igt@gen9_exec_parse@bb-large:
- shard-kbl: NOTRUN -> [FAIL][23] ([i915#3296])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl3/igt@gen9_exec_parse@bb-large.html
* igt@i915_hangman@engine-error@vecs0:
- shard-kbl: NOTRUN -> [SKIP][24] ([fdo#109271]) +129 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl3/igt@i915_hangman@engine-error@vecs0.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][25] -> [FAIL][26] ([i915#454])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#1937])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-iclb: NOTRUN -> [SKIP][28] ([fdo#110892])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb7/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-skl: [PASS][29] -> [INCOMPLETE][30] ([i915#198])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-skl6/igt@i915_suspend@fence-restore-tiled2untiled.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-skl8/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][31] ([fdo#110725] / [fdo#111614])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb7/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_joiner@invalid-modeset:
- shard-apl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#2705])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl8/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_chamelium@dp-mode-timings:
- shard-apl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +29 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl8/igt@kms_chamelium@dp-mode-timings.html
* igt@kms_chamelium@vga-hpd:
- shard-snb: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +4 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-snb6/igt@kms_chamelium@vga-hpd.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +9 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl7/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_color_chamelium@pipe-d-ctm-max:
- shard-iclb: NOTRUN -> [SKIP][36] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb7/igt@kms_color_chamelium@pipe-d-ctm-max.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][37] ([i915#1319]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl2/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@uevent:
- shard-iclb: NOTRUN -> [SKIP][38] ([fdo#109300] / [fdo#111066])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb7/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][39] -> [DMESG-WARN][40] ([i915#180]) +4 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: [PASS][41] -> [FAIL][42] ([i915#54])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-skl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109274] / [fdo#109278])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb7/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: NOTRUN -> [DMESG-WARN][44] ([i915#180]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip@plain-flip-ts-check@b-edp1:
- shard-skl: [PASS][45] -> [FAIL][46] ([i915#2122])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-skl2/igt@kms_flip@plain-flip-ts-check@b-edp1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-skl1/igt@kms_flip@plain-flip-ts-check@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#2672])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109280]) +7 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#533]) +4 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-kbl: NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#533]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl3/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][51] ([fdo#108145] / [i915#265]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][52] ([i915#265])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][53] ([fdo#108145] / [i915#265]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl3/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-apl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#2733])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
- shard-kbl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#2733])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl2/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#658]) +7 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#658]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl3/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-iclb: NOTRUN -> [SKIP][58] ([i915#658])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: NOTRUN -> [SKIP][59] ([fdo#109441])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb7/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][60] -> [SKIP][61] ([fdo#109441]) +2 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb4/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_writeback@writeback-fb-id:
- shard-iclb: NOTRUN -> [SKIP][62] ([i915#2437])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb7/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-kbl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#2437]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl3/igt@kms_writeback@writeback-pixel-formats.html
- shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#2437])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl6/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271]) +293 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl8/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html
* igt@perf@blocking:
- shard-skl: [PASS][66] -> [FAIL][67] ([i915#1542])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-skl2/igt@perf@blocking.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-skl1/igt@perf@blocking.html
* igt@perf@gen12-unprivileged-single-ctx-counters:
- shard-skl: NOTRUN -> [SKIP][68] ([fdo#109271]) +7 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-skl6/igt@perf@gen12-unprivileged-single-ctx-counters.html
* igt@prime_nv_pcopy@test3_5:
- shard-iclb: NOTRUN -> [SKIP][69] ([fdo#109291]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb7/igt@prime_nv_pcopy@test3_5.html
* igt@sysfs_clients@fair-3:
- shard-kbl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#2994])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl3/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@pidname:
- shard-iclb: NOTRUN -> [SKIP][71] ([i915#2994])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb7/igt@sysfs_clients@pidname.html
* igt@sysfs_clients@sema-50:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#2994]) +3 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl8/igt@sysfs_clients@sema-50.html
#### Possible fixes ####
* igt@gem_eio@unwedge-stress:
- shard-iclb: [TIMEOUT][73] ([i915#2369] / [i915#2481] / [i915#3070]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-iclb2/igt@gem_eio@unwedge-stress.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb4/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [FAIL][75] ([i915#2846]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-kbl6/igt@gem_exec_fair@basic-deadline.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl7/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_whisper@basic-contexts-priority:
- shard-iclb: [INCOMPLETE][77] ([i915#1895]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-iclb1/igt@gem_exec_whisper@basic-contexts-priority.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb7/igt@gem_exec_whisper@basic-contexts-priority.html
* igt@gem_exec_whisper@basic-contexts-priority-all:
- shard-glk: [DMESG-WARN][79] ([i915#118] / [i915#95]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-glk3/igt@gem_exec_whisper@basic-contexts-priority-all.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-glk4/igt@gem_exec_whisper@basic-contexts-priority-all.html
* igt@gem_mmap_gtt@big-copy:
- shard-glk: [FAIL][81] ([i915#307]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-glk5/igt@gem_mmap_gtt@big-copy.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-glk3/igt@gem_mmap_gtt@big-copy.html
* igt@gem_mmap_gtt@cpuset-medium-copy:
- shard-iclb: [FAIL][83] ([i915#307]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-iclb6/igt@gem_mmap_gtt@cpuset-medium-copy.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb2/igt@gem_mmap_gtt@cpuset-medium-copy.html
* igt@gem_vm_create@destroy-race:
- shard-tglb: [TIMEOUT][85] ([i915#2795]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-tglb3/igt@gem_vm_create@destroy-race.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-tglb5/igt@gem_vm_create@destroy-race.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][87] ([i915#180]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-apl6/igt@gem_workarounds@suspend-resume-context.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [FAIL][89] ([i915#2346]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled:
- shard-glk: [FAIL][91] ([i915#52] / [i915#54]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-glk3/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-glk4/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][93] ([i915#180]) -> [PASS][94] +6 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][95] ([i915#1188]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-skl5/igt@kms_hdr@bpc-switch-suspend.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][97] ([fdo#108145] / [i915#265]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [SKIP][99] ([fdo#109441]) -> [PASS][100] +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-iclb6/igt@kms_psr@psr2_dpms.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb2/igt@kms_psr@psr2_dpms.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][101] ([i915#180] / [i915#295]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf@polling-small-buf:
- shard-skl: [FAIL][103] ([i915#1722]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-skl7/igt@perf@polling-small-buf.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-skl4/igt@perf@polling-small-buf.html
#### Warnings ####
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-iclb: [SKIP][105] ([i915#658]) -> [SKIP][106] ([i915#2920]) +2 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-iclb6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3:
- shard-iclb: [SKIP][107] ([i915#2920]) -> [SKIP][108] ([i915#658]) +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#602]) -> ([FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2722] / [i915#3002] / [i915#602])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-kbl3/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-kbl4/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-kbl1/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-kbl4/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-kbl4/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-kbl1/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-kbl1/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-kbl1/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl4/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl7/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl1/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl4/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl1/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl2/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl1/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-kbl1/igt@runner@aborted.html
- shard-apl: ([FAIL][125], [FAIL][126], [FAIL][127]) ([fdo#109271] / [i915#180] / [i915#3002]) -> ([FAIL][128], [FAIL][129]) ([i915#180] / [i915#3002])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-apl6/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-apl1/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-apl6/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl6/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-apl2/igt@runner@aborted.html
- shard-skl: ([FAIL][130], [FAIL][131], [FAIL][132]) ([i915#2029] / [i915#3002]) -> ([FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136]) ([i915#1436] / [i915#1814] / [i915#2029] / [i915#3002])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-skl2/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-skl8/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9962/shard-skl5/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-skl2/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-skl6/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-skl2/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/shard-skl1/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#110892]: https://bugs.freedesktop.org/show_bug.cgi?id=110892
[fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112306]: https://bugs.freedesktop.org/show_bug.cgi?id=112306
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1699]: https://gitlab.freedesktop.org/drm/intel/issues/1699
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1895]: https://gitlab.freedesktop.org/drm/intel/issues/1895
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2481]: https://gitlab.freedesktop.org/drm/intel/issues/2481
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2733]: https://gitlab.freedesktop.org/drm/intel/issues/2733
[i915#2795]: https://gitlab.freedesktop.org/drm/intel/issues/2795
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#307]: https://gitlab.freedesktop.org/drm/intel/issues/307
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3296]: https://gitlab.freedesktop.org/drm/intel/issues/3296
[i915#3323]: https://gitlab.freedesktop
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19918/index.html
[-- Attachment #1.2: Type: text/html, Size: 37707 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 01/12] drm/i915/display: use DISPLAY_VER() on remaining users
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 01/12] drm/i915/display: use DISPLAY_VER() on remaining users Lucas De Marchi
@ 2021-04-13 9:24 ` Jani Nikula
0 siblings, 0 replies; 39+ messages in thread
From: Jani Nikula @ 2021-04-13 9:24 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On Mon, 12 Apr 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Commit 989634fb49ad ("drm/i915/audio: set HDA link parameters in driver")
> added INTEL_GEN() in the display code, where it should actually be using
> DISPLAY_VER(). Switch to the new macro.
>
> Cc: Kai Vehmanen <kai.vehmanen@linux.intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index 9671c8f6e892..9fe3a25710b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -1309,7 +1309,7 @@ static void i915_audio_component_init(struct drm_i915_private *dev_priv)
> if (DISPLAY_VER(dev_priv) >= 9) {
> aud_freq_init = intel_de_read(dev_priv, AUD_FREQ_CNTRL);
>
> - if (INTEL_GEN(dev_priv) >= 12)
> + if (DISPLAY_VER(dev_priv) >= 12)
> aud_freq = AUD_FREQ_GEN12;
> else
> aud_freq = aud_freq_init;
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 02/12] drm/i915: rename display.version to display.ver
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 02/12] drm/i915: rename display.version to display.ver Lucas De Marchi
@ 2021-04-13 9:25 ` Jani Nikula
0 siblings, 0 replies; 39+ messages in thread
From: Jani Nikula @ 2021-04-13 9:25 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On Mon, 12 Apr 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> The macro we use to check is called DISPLAY_VER(). While using this
> macro and the new ones being added in following changes I made the
> mistake multiple times when mixing both "ver" and "version". Although
> it's usually better to prefer the complete name, the shorhand
> DISPLAY_VER() / GRAPHICS_VER / MEDIA_VER are clear and cause less
> visual polution.
>
> Another issue is when copying the variable to other places.
> "display.version" would be copied to a "display_version" variable which
> is long and would make people abbreviate as "version", or "display_ver".
> In the first case it's not always clear what version refers to, and in
> the second case it just hints it should be the name in the first place.
>
> So, in the same way use used "gen" rather than "generation", use "ver"
> instead of "version".
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_pci.c | 4 ++--
> drivers/gpu/drm/i915/intel_device_info.h | 2 +-
> 3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 69e43bf91a15..8c62bb2abd31 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1237,7 +1237,7 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
> #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
> #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
>
> -#define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.version)
> +#define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
> #define IS_DISPLAY_RANGE(i915, from, until) \
> (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
> #define IS_DISPLAY_VER(i915, v) (DISPLAY_VER(i915) == (v))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 480553746794..ce5cbeaf036d 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -36,7 +36,7 @@
> #include "i915_selftest.h"
>
> #define PLATFORM(x) .platform = (x)
> -#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1), .display.version = (x)
> +#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1), .display.ver = (x)
>
> #define I845_PIPE_OFFSETS \
> .pipe_offsets = { \
> @@ -723,7 +723,7 @@ static const struct intel_device_info bxt_info = {
> static const struct intel_device_info glk_info = {
> GEN9_LP_FEATURES,
> PLATFORM(INTEL_GEMINILAKE),
> - .display.version = 10,
> + .display.ver = 10,
> .ddb_size = 1024,
> GLK_COLORS,
> };
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 2f442d418a15..b16c75927a12 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -189,7 +189,7 @@ struct intel_device_info {
> #undef DEFINE_FLAG
>
> struct {
> - u8 version;
> + u8 ver;
>
> #define DEFINE_FLAG(name) u8 name:1
> DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 04/12] drm/i915: add macros for graphics and media versions
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 04/12] drm/i915: add macros for graphics and media versions Lucas De Marchi
@ 2021-04-13 9:33 ` Jani Nikula
0 siblings, 0 replies; 39+ messages in thread
From: Jani Nikula @ 2021-04-13 9:33 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On Mon, 12 Apr 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Like it was done in
> commit 01eb15c9165e ("drm/i915: Add DISPLAY_VER() and related macros")
> add the correspondent macros for graphics and media. Going forward we
> will prefer checking the versions for the specific IPs (graphics, media
> and display) rather than grouping everything under a "gen" version.
>
> For consistency and to make the maintenance easier, it'd be preferred
> not to mix the *GEN* macros with the new ones. For older platforms we
> can simply consider that the previous "gen" number will extend to all
> 3 IPs. Then we can start replacing its use in the driver. Right now this
> replacement is not done and only the infrastructure is put in place.
> We also leave gen and gen_mask inside struct intel_device_info while
> it's still being used throughout the code.
>
> v2: Repurpose IS_{GRAPHICS,MEDIA}_VER() macros to work with a range
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 15 ++++++++++++++-
> drivers/gpu/drm/i915/i915_pci.c | 7 ++++++-
> drivers/gpu/drm/i915/intel_device_info.h | 3 +++
> 3 files changed, 23 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 907c66efb469..cb59eb0f6c5b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1234,9 +1234,22 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
> #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
> #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
>
> -#define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
> #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
>
> +/*
> + * Deprecated: this will be replaced by individual IP checks:
> + * GRAPHICS_VER(), MEDIA_VER and DISPLAY_VER()
Nitpick, MEDIA_VER() with braces.
Otherwise,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> + */
> +#define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
> +
> +#define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics_ver)
> +#define IS_GRAPHICS_VER(i915, from, until) \
> + (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
> +
> +#define MEDIA_VER(i915) (INTEL_INFO(i915)->media_ver)
> +#define IS_MEDIA_VER(i915, from, until) \
> + (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
> +
> #define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
> #define IS_DISPLAY_VER(i915, from, until) \
> (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index ce5cbeaf036d..97ab73276334 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -36,7 +36,12 @@
> #include "i915_selftest.h"
>
> #define PLATFORM(x) .platform = (x)
> -#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1), .display.ver = (x)
> +#define GEN(x) \
> + .gen_mask = BIT((x) - 1), \
> + .gen = (x), \
> + .graphics_ver = (x), \
> + .media_ver = (x), \
> + .display.ver = (x)
>
> #define I845_PIPE_OFFSETS \
> .pipe_offsets = { \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index b16c75927a12..405883a8cc84 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -162,6 +162,9 @@ enum intel_ppgtt_type {
> struct intel_device_info {
> u16 gen_mask;
>
> + u8 graphics_ver;
> + u8 media_ver;
> +
> u8 gen;
> u8 gt; /* GT number, 0 if undefined */
> intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 03/12] drm/i915/display: rename display version macros
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 03/12] drm/i915/display: rename display version macros Lucas De Marchi
@ 2021-04-13 9:35 ` Jani Nikula
0 siblings, 0 replies; 39+ messages in thread
From: Jani Nikula @ 2021-04-13 9:35 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On Mon, 12 Apr 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> While converting the rest of the driver to use GRAPHICS_VER() and
> MEDIA_VER(), following what was done for display, some discussions went
> back on what we did for display:
>
> 1) Why is the == comparison special that deserves a separate
> macro instead of just getting the version and comparing directly
> like is done for >, >=, <=?
>
> 2) IS_DISPLAY_RANGE() is weird in that it omits the "_VER" for
> brevity. If we remove the current users of IS_DISPLAY_VER(), we
> could actually repurpose it for a range check
>
> With (1) there could be an advantage if we used gen_mask since multiple
> conditionals be combined by the compiler in a single and instruction and
> check the result. However a) INTEL_GEN() doesn't use the mask since it
> would make the code bigger everywhere else and b) in the cases it made
> sense, it also made sense to convert to the _RANGE() variant.
>
> So here we repurpose IS_DISPLAY_VER() to work with a [ from, to ] range
> like was the IS_DISPLAY_RANGE() and convert the current IS_DISPLAY_VER()
> users to use == and != operators. Aside from the definition changes,
> this was done by the following semantic patch:
>
> @@ expression dev_priv, E1; @@
> - !IS_DISPLAY_VER(dev_priv, E1)
> + DISPLAY_VER(dev_priv) != E1
>
> @@ expression dev_priv, E1; @@
> - IS_DISPLAY_VER(dev_priv, E1)
> + DISPLAY_VER(dev_priv) == E1
>
> @@ expression dev_priv, from, until; @@
> - IS_DISPLAY_RANGE(dev_priv, from, until)
> + IS_DISPLAY_VER(dev_priv, from, until)
>
Thanks for summing up the discussion in a delightfully clear commit
message!
I like the change.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
> drivers/gpu/drm/i915/display/icl_dsi.c | 4 +-
> drivers/gpu/drm/i915/display/intel_atomic.c | 2 +-
> drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
> drivers/gpu/drm/i915/display/intel_bios.c | 4 +-
> drivers/gpu/drm/i915/display/intel_bw.c | 8 +--
> drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +++---
> drivers/gpu/drm/i915/display/intel_color.c | 6 +-
> drivers/gpu/drm/i915/display/intel_crt.c | 6 +-
> drivers/gpu/drm/i915/display/intel_crtc.c | 4 +-
> drivers/gpu/drm/i915/display/intel_csr.c | 2 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 26 ++++-----
> .../drm/i915/display/intel_ddi_buf_trans.c | 8 +--
> drivers/gpu/drm/i915/display/intel_display.c | 56 +++++++++----------
> .../drm/i915/display/intel_display_power.c | 26 ++++-----
> drivers/gpu/drm/i915/display/intel_dp.c | 8 +--
> drivers/gpu/drm/i915/display/intel_dpll.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
> drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
> drivers/gpu/drm/i915/display/intel_fbc.c | 20 +++----
> .../drm/i915/display/intel_fifo_underrun.c | 4 +-
> drivers/gpu/drm/i915/display/intel_gmbus.c | 4 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +-
> drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
> drivers/gpu/drm/i915/display/intel_overlay.c | 10 ++--
> drivers/gpu/drm/i915/display/intel_panel.c | 8 +--
> drivers/gpu/drm/i915/display/intel_pipe_crc.c | 4 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 4 +-
> drivers/gpu/drm/i915/display/intel_tc.c | 6 +-
> drivers/gpu/drm/i915/display/intel_tv.c | 6 +-
> .../drm/i915/display/skl_universal_plane.c | 8 +--
> drivers/gpu/drm/i915/i915_drv.h | 3 +-
> drivers/gpu/drm/i915/i915_irq.c | 10 ++--
> drivers/gpu/drm/i915/intel_pm.c | 48 ++++++++--------
> 35 files changed, 165 insertions(+), 166 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 456374ddf37a..80da0e3571a4 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -144,7 +144,7 @@ static bool i9xx_plane_has_windowing(struct intel_plane *plane)
> return i9xx_plane == PLANE_B;
> else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
> return false;
> - else if (IS_DISPLAY_VER(dev_priv, 4))
> + else if (DISPLAY_VER(dev_priv) == 4)
> return i9xx_plane == PLANE_C;
> else
> return i9xx_plane == PLANE_B ||
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 9282978060b0..37e2d93d064c 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -592,7 +592,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
> * a value '0' inside TA_PARAM_REGISTERS otherwise
> * leave all fields at HW default values.
> */
> - if (IS_DISPLAY_VER(dev_priv, 11)) {
> + if (DISPLAY_VER(dev_priv) == 11) {
> if (afe_clk(encoder, crtc_state) <= 800000) {
> for_each_dsi_port(port, intel_dsi->ports) {
> tmp = intel_de_read(dev_priv,
> @@ -1158,7 +1158,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> gen11_dsi_configure_transcoder(encoder, crtc_state);
>
> /* Step 4l: Gate DDI clocks */
> - if (IS_DISPLAY_VER(dev_priv, 11))
> + if (DISPLAY_VER(dev_priv) == 11)
> gen11_dsi_gate_clocks(encoder);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 4fa389fce8cb..45feaaddab26 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -332,7 +332,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
> plane_state->hw.fb->format->is_yuv &&
> plane_state->hw.fb->format->num_planes > 1) {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> - if (IS_DISPLAY_VER(dev_priv, 9)) {
> + if (DISPLAY_VER(dev_priv) == 9) {
> mode = SKL_PS_SCALER_MODE_NV12;
> } else if (icl_is_hdr_plane(dev_priv, plane->id)) {
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index 9fe3a25710b8..b40e929a167e 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -591,7 +591,7 @@ static void enable_audio_dsc_wa(struct intel_encoder *encoder,
>
> val = intel_de_read(i915, AUD_CONFIG_BE);
>
> - if (IS_DISPLAY_VER(i915, 11))
> + if (DISPLAY_VER(i915) == 11)
> val |= HBLANK_EARLY_ENABLE_ICL(pipe);
> else if (DISPLAY_VER(i915) >= 12)
> val |= HBLANK_EARLY_ENABLE_TGL(pipe);
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index ea4837d485a1..befab891a6b9 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -610,7 +610,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *i915)
> * Only parse SDVO mappings on gens that could have SDVO. This isn't
> * accurate and doesn't have to be, as long as it's not too strict.
> */
> - if (!IS_DISPLAY_RANGE(i915, 3, 7)) {
> + if (!IS_DISPLAY_VER(i915, 3, 7)) {
> drm_dbg_kms(&i915->drm, "Skipping SDVO device mapping\n");
> return;
> }
> @@ -1659,7 +1659,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
> } else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) {
> ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
> n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);
> - } else if (HAS_PCH_TGP(i915) && IS_DISPLAY_VER(i915, 9)) {
> + } else if (HAS_PCH_TGP(i915) && DISPLAY_VER(i915) == 9) {
> ddc_pin_map = gen9bc_tgp_ddc_pin_map;
> n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map);
> } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 584ab5ce4106..20dbc3759d27 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -77,7 +77,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
>
> qi->num_points = dram_info->num_qgv_points;
>
> - if (IS_DISPLAY_VER(dev_priv, 12))
> + if (DISPLAY_VER(dev_priv) == 12)
> switch (dram_info->type) {
> case INTEL_DRAM_DDR4:
> qi->t_bl = 4;
> @@ -89,7 +89,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
> qi->t_bl = 16;
> break;
> }
> - else if (IS_DISPLAY_VER(dev_priv, 11))
> + else if (DISPLAY_VER(dev_priv) == 11)
> qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
>
> if (drm_WARN_ON(&dev_priv->drm,
> @@ -271,9 +271,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
> icl_get_bw_info(dev_priv, &adls_sa_info);
> else if (IS_ROCKETLAKE(dev_priv))
> icl_get_bw_info(dev_priv, &rkl_sa_info);
> - else if (IS_DISPLAY_VER(dev_priv, 12))
> + else if (DISPLAY_VER(dev_priv) == 12)
> icl_get_bw_info(dev_priv, &tgl_sa_info);
> - else if (IS_DISPLAY_VER(dev_priv, 11))
> + else if (DISPLAY_VER(dev_priv) == 11)
> icl_get_bw_info(dev_priv, &icl_sa_info);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 489acf6b5cf1..1f0bd23bb883 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1801,7 +1801,7 @@ void intel_cdclk_init_hw(struct drm_i915_private *i915)
> {
> if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
> bxt_cdclk_init_hw(i915);
> - else if (IS_DISPLAY_VER(i915, 9))
> + else if (DISPLAY_VER(i915) == 9)
> skl_cdclk_init_hw(i915);
> }
>
> @@ -1816,7 +1816,7 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
> {
> if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
> bxt_cdclk_uninit_hw(i915);
> - else if (IS_DISPLAY_VER(i915, 9))
> + else if (DISPLAY_VER(i915) == 9)
> skl_cdclk_uninit_hw(i915);
> }
>
> @@ -2004,7 +2004,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
>
> if (DISPLAY_VER(dev_priv) >= 10)
> return DIV_ROUND_UP(pixel_rate, 2);
> - else if (IS_DISPLAY_VER(dev_priv, 9) ||
> + else if (DISPLAY_VER(dev_priv) == 9 ||
> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> return pixel_rate;
> else if (IS_CHERRYVIEW(dev_priv))
> @@ -2052,10 +2052,10 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> crtc_state->has_audio &&
> crtc_state->port_clock >= 540000 &&
> crtc_state->lane_count == 4) {
> - if (IS_DISPLAY_VER(dev_priv, 10)) {
> + if (DISPLAY_VER(dev_priv) == 10) {
> /* Display WA #1145: glk,cnl */
> min_cdclk = max(316800, min_cdclk);
> - } else if (IS_DISPLAY_VER(dev_priv, 9) || IS_BROADWELL(dev_priv)) {
> + } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) {
> /* Display WA #1144: skl,bxt */
> min_cdclk = max(432000, min_cdclk);
> }
> @@ -2594,7 +2594,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>
> if (DISPLAY_VER(dev_priv) >= 10)
> return 2 * max_cdclk_freq;
> - else if (IS_DISPLAY_VER(dev_priv, 9) ||
> + else if (DISPLAY_VER(dev_priv) == 9 ||
> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> return max_cdclk_freq;
> else if (IS_CHERRYVIEW(dev_priv))
> @@ -2631,7 +2631,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> dev_priv->max_cdclk_freq = 316800;
> } else if (IS_BROXTON(dev_priv)) {
> dev_priv->max_cdclk_freq = 624000;
> - } else if (IS_DISPLAY_VER(dev_priv, 9)) {
> + } else if (DISPLAY_VER(dev_priv) == 9) {
> u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> int max_cdclk, vco;
>
> @@ -2889,7 +2889,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> dev_priv->cdclk.table = glk_cdclk_table;
> else
> dev_priv->cdclk.table = bxt_cdclk_table;
> - } else if (IS_DISPLAY_VER(dev_priv, 9)) {
> + } else if (DISPLAY_VER(dev_priv) == 9) {
> dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> dev_priv->display.set_cdclk = skl_set_cdclk;
> dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
> @@ -2912,7 +2912,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>
> if (DISPLAY_VER(dev_priv) >= 10 || IS_BROXTON(dev_priv))
> dev_priv->display.get_cdclk = bxt_get_cdclk;
> - else if (IS_DISPLAY_VER(dev_priv, 9))
> + else if (DISPLAY_VER(dev_priv) == 9)
> dev_priv->display.get_cdclk = skl_get_cdclk;
> else if (IS_BROADWELL(dev_priv))
> dev_priv->display.get_cdclk = bdw_get_cdclk;
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index c75d7124d57a..5fae69879adf 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -225,7 +225,7 @@ static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
> */
> return crtc_state->limited_color_range &&
> (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
> - IS_DISPLAY_RANGE(dev_priv, 9, 10));
> + IS_DISPLAY_VER(dev_priv, 9, 10));
> }
>
> static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
> @@ -1711,7 +1711,7 @@ int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_stat
> } else {
> if (DISPLAY_VER(dev_priv) >= 11)
> return icl_gamma_precision(crtc_state);
> - else if (IS_DISPLAY_VER(dev_priv, 10))
> + else if (DISPLAY_VER(dev_priv) == 10)
> return glk_gamma_precision(crtc_state);
> else if (IS_IRONLAKE(dev_priv))
> return ilk_gamma_precision(crtc_state);
> @@ -2136,7 +2136,7 @@ void intel_color_init(struct intel_crtc *crtc)
> if (DISPLAY_VER(dev_priv) >= 11) {
> dev_priv->display.load_luts = icl_load_luts;
> dev_priv->display.read_luts = icl_read_luts;
> - } else if (IS_DISPLAY_VER(dev_priv, 10)) {
> + } else if (DISPLAY_VER(dev_priv) == 10) {
> dev_priv->display.load_luts = glk_load_luts;
> dev_priv->display.read_luts = glk_read_luts;
> } else if (DISPLAY_VER(dev_priv) >= 8) {
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index 580d652c3276..c85092eaa5c2 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -356,7 +356,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
> * DAC limit supposedly 355 MHz.
> */
> max_clock = 270000;
> - else if (IS_DISPLAY_RANGE(dev_priv, 3, 4))
> + else if (IS_DISPLAY_VER(dev_priv, 3, 4))
> max_clock = 400000;
> else
> max_clock = 350000;
> @@ -711,7 +711,7 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
> /* Set the border color to purple. */
> intel_uncore_write(uncore, bclrpat_reg, 0x500050);
>
> - if (!IS_DISPLAY_VER(dev_priv, 2)) {
> + if (DISPLAY_VER(dev_priv) != 2) {
> u32 pipeconf = intel_uncore_read(uncore, pipeconf_reg);
> intel_uncore_write(uncore,
> pipeconf_reg,
> @@ -1047,7 +1047,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
> else
> crt->base.pipe_mask = ~0;
>
> - if (IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> connector->interlace_allowed = 0;
> else
> connector->interlace_allowed = 1;
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 39358076c05b..95ff1707b4bd 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -302,11 +302,11 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
> if (IS_CHERRYVIEW(dev_priv) ||
> IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
> funcs = &g4x_crtc_funcs;
> - else if (IS_DISPLAY_VER(dev_priv, 4))
> + else if (DISPLAY_VER(dev_priv) == 4)
> funcs = &i965_crtc_funcs;
> else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
> funcs = &i915gm_crtc_funcs;
> - else if (IS_DISPLAY_VER(dev_priv, 3))
> + else if (DISPLAY_VER(dev_priv) == 3)
> funcs = &i915_crtc_funcs;
> else
> funcs = &i8xx_crtc_funcs;
> diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
> index e54521d7b931..26a3c6787e9e 100644
> --- a/drivers/gpu/drm/i915/display/intel_csr.c
> +++ b/drivers/gpu/drm/i915/display/intel_csr.c
> @@ -709,7 +709,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
> csr->fw_path = TGL_CSR_PATH;
> csr->required_version = TGL_CSR_VERSION_REQUIRED;
> csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
> - } else if (IS_DISPLAY_VER(dev_priv, 11)) {
> + } else if (DISPLAY_VER(dev_priv) == 11) {
> csr->fw_path = ICL_CSR_PATH;
> csr->required_version = ICL_CSR_VERSION_REQUIRED;
> csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index deef24da00b5..6bb2d2bb7239 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -113,7 +113,7 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
> &n_entries);
>
> /* If we're boosting the current, set bit 31 of trans1 */
> - if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv) &&
> + if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
> intel_bios_encoder_dp_boost_level(encoder->devdata))
> iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
>
> @@ -147,7 +147,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
> level = n_entries - 1;
>
> /* If we're boosting the current, set bit 31 of trans1 */
> - if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv) &&
> + if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
> intel_bios_encoder_hdmi_boost_level(encoder->devdata))
> iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
>
> @@ -473,7 +473,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
> temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
> }
>
> - if (IS_DISPLAY_RANGE(dev_priv, 8, 10) &&
> + if (IS_DISPLAY_VER(dev_priv, 8, 10) &&
> crtc_state->master_transcoder != INVALID_TRANSCODER) {
> u8 master_select =
> bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
> @@ -548,7 +548,7 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
>
> ctl &= ~TRANS_DDI_FUNC_ENABLE;
>
> - if (IS_DISPLAY_RANGE(dev_priv, 8, 10))
> + if (IS_DISPLAY_VER(dev_priv, 8, 10))
> ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
> TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
>
> @@ -978,7 +978,7 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
> tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
> else
> tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
> - } else if (IS_DISPLAY_VER(dev_priv, 11)) {
> + } else if (DISPLAY_VER(dev_priv) == 11) {
> if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
> jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
> else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
> @@ -1557,7 +1557,7 @@ hsw_set_signal_levels(struct intel_dp *intel_dp,
> intel_dp->DP &= ~DDI_BUF_EMP_MASK;
> intel_dp->DP |= signal_levels;
>
> - if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv))
> + if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
> skl_ddi_set_iboost(encoder, crtc_state, level);
>
> intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> @@ -3094,7 +3094,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
>
> if (DISPLAY_VER(dev_priv) >= 12)
> tgl_ddi_vswing_sequence(encoder, crtc_state, level);
> - else if (IS_DISPLAY_VER(dev_priv, 11))
> + else if (DISPLAY_VER(dev_priv) == 11)
> icl_ddi_vswing_sequence(encoder, crtc_state, level);
> else if (IS_CANNONLAKE(dev_priv))
> cnl_ddi_vswing_sequence(encoder, crtc_state, level);
> @@ -3103,11 +3103,11 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
> else
> intel_prepare_hdmi_ddi_buffers(encoder, level);
>
> - if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv))
> + if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
> skl_ddi_set_iboost(encoder, crtc_state, level);
>
> /* Display WA #1143: skl,kbl,cfl */
> - if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) {
> + if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
> /*
> * For some reason these chicken bits have been
> * stuffed into a transcoder register, event though
> @@ -4590,7 +4590,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
> /* BXT/GLK have fixed PLL->port mapping */
> encoder->get_config = bxt_ddi_get_config;
> - } else if (IS_DISPLAY_VER(dev_priv, 9)) {
> + } else if (DISPLAY_VER(dev_priv) == 9) {
> encoder->enable_clock = skl_ddi_enable_clock;
> encoder->disable_clock = skl_ddi_disable_clock;
> encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
> @@ -4610,11 +4610,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
> else if (IS_JSL_EHL(dev_priv))
> encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
> - else if (IS_DISPLAY_VER(dev_priv, 11))
> + else if (DISPLAY_VER(dev_priv) == 11)
> encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
> - else if (IS_DISPLAY_VER(dev_priv, 10))
> + else if (DISPLAY_VER(dev_priv) == 10)
> encoder->hpd_pin = cnl_hpd_pin(dev_priv, port);
> - else if (IS_DISPLAY_VER(dev_priv, 9))
> + else if (DISPLAY_VER(dev_priv) == 9)
> encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
> else
> encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index fdd25861edd5..58d6417b8f3e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -881,7 +881,7 @@ intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) {
> + if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
> const struct ddi_buf_trans *ddi_translations =
> skl_get_buf_trans_edp(encoder, n_entries);
> *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
> @@ -919,7 +919,7 @@ intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) {
> + if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
> return skl_get_buf_trans_hdmi(dev_priv, n_entries);
> } else if (IS_BROADWELL(dev_priv)) {
> *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
> @@ -1361,7 +1361,7 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder,
> else
> tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries);
> *default_entry = n_entries - 1;
> - } else if (IS_DISPLAY_VER(dev_priv, 11)) {
> + } else if (DISPLAY_VER(dev_priv) == 11) {
> if (intel_phy_is_combo(dev_priv, phy))
> icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
> else
> @@ -1373,7 +1373,7 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder,
> } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
> bxt_get_buf_trans_hdmi(encoder, &n_entries);
> *default_entry = n_entries - 1;
> - } else if (IS_DISPLAY_VER(dev_priv, 9)) {
> + } else if (DISPLAY_VER(dev_priv) == 9) {
> intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
> *default_entry = 8;
> } else if (IS_BROADWELL(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 411b46c012f8..fababa82b4af 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -230,7 +230,7 @@ static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
> u32 line1, line2;
> u32 line_mask;
>
> - if (IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> line_mask = DSL_LINEMASK_GEN2;
> else
> line_mask = DSL_LINEMASK_GEN3;
> @@ -874,7 +874,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> case DRM_FORMAT_MOD_LINEAR:
> return intel_tile_size(dev_priv);
> case I915_FORMAT_MOD_X_TILED:
> - if (IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> return 128;
> else
> return 512;
> @@ -889,7 +889,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> return 64;
> fallthrough;
> case I915_FORMAT_MOD_Y_TILED:
> - if (IS_DISPLAY_VER(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
> + if (DISPLAY_VER(dev_priv) == 2 || HAS_128_BYTE_Y_TILING(dev_priv))
> return 128;
> else
> return 512;
> @@ -1406,7 +1406,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
> * require the entire fb to accommodate that to avoid
> * potential runtime errors at plane configuration time.
> */
> - if (IS_DISPLAY_VER(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
> + if (DISPLAY_VER(dev_priv) == 9 && color_plane == 0 && fb->width > 3840)
> tile_width *= 4;
> /*
> * The main surface pitch must be padded to a multiple of four
> @@ -1608,7 +1608,7 @@ static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
> * Gen2 reports pipe underruns whenever all planes are disabled.
> * So disable underrun reporting before all the planes get disabled.
> */
> - if (IS_DISPLAY_VER(dev_priv, 2) && !crtc_state->active_planes)
> + if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
> intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
>
> intel_disable_plane(plane, crtc_state);
> @@ -2471,7 +2471,7 @@ static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
> return false;
>
> /* WA Display #0827: Gen9:all */
> - if (IS_DISPLAY_VER(dev_priv, 9))
> + if (DISPLAY_VER(dev_priv) == 9)
> return true;
>
> return false;
> @@ -2482,7 +2482,7 @@ static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> /* Wa_2006604312:icl,ehl */
> - if (crtc_state->scaler_state.scaler_users > 0 && IS_DISPLAY_VER(dev_priv, 11))
> + if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
> return true;
>
> return false;
> @@ -2682,7 +2682,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
> * chance of catching underruns with the intermediate watermarks
> * vs. the old plane configuration.
> */
> - if (IS_DISPLAY_VER(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
> + if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>
> /*
> @@ -3201,7 +3201,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> crtc->active = true;
>
> /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
> - psl_clkgate_wa = IS_DISPLAY_VER(dev_priv, 10) &&
> + psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
> new_crtc_state->pch_pfit.enabled;
> if (psl_clkgate_wa)
> glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
> @@ -3655,7 +3655,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
>
> crtc->active = true;
>
> - if (!IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) != 2)
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>
> intel_encoders_pre_enable(state, crtc);
> @@ -3680,7 +3680,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
> intel_encoders_enable(state, crtc);
>
> /* prevents spurious underruns */
> - if (IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> intel_wait_for_vblank(dev_priv, pipe);
> }
>
> @@ -3711,7 +3711,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
> * On gen2 planes are double buffered but the pipe isn't, so we must
> * wait for planes to fully turn off before disabling the pipe.
> */
> - if (IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> intel_wait_for_vblank(dev_priv, pipe);
>
> intel_encoders_disable(state, crtc);
> @@ -3735,7 +3735,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
>
> intel_encoders_post_pll_disable(state, crtc);
>
> - if (!IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) != 2)
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>
> if (!dev_priv->display.initial_watermarks)
> @@ -4302,7 +4302,7 @@ static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
> * Strictly speaking some registers are available before
> * gen7, but we only support DRRS on gen7+
> */
> - return IS_DISPLAY_VER(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
> + return DISPLAY_VER(dev_priv) == 7 || IS_CHERRYVIEW(dev_priv);
> }
>
> static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
> @@ -4449,7 +4449,7 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> - if (IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> return false;
>
> if (DISPLAY_VER(dev_priv) >= 9 ||
> @@ -5644,7 +5644,7 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
> * ivb/hsw (since we don't use the higher upscaling modes which
> * differentiates them) so just WARN about this case for now.
> */
> - drm_WARN_ON(&dev_priv->drm, IS_DISPLAY_VER(dev_priv, 7) &&
> + drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 &&
> (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
> }
>
> @@ -6327,7 +6327,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
> return dev_priv->vbt.lvds_ssc_freq;
> else if (HAS_PCH_SPLIT(dev_priv))
> return 120000;
> - else if (!IS_DISPLAY_VER(dev_priv, 2))
> + else if (DISPLAY_VER(dev_priv) != 2)
> return 96000;
> else
> return 48000;
> @@ -6360,7 +6360,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
> }
>
> - if (!IS_DISPLAY_VER(dev_priv, 2)) {
> + if (DISPLAY_VER(dev_priv) != 2) {
> if (IS_PINEVIEW(dev_priv))
> clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
> DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
> @@ -8788,7 +8788,7 @@ intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
> * However if queried just before the start of vblank we'll get an
> * answer that's slightly in the future.
> */
> - if (IS_DISPLAY_VER(dev_priv, 2)) {
> + if (DISPLAY_VER(dev_priv) == 2) {
> int vtotal;
>
> vtotal = adjusted_mode.crtc_vtotal;
> @@ -9665,7 +9665,7 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - if (!IS_DISPLAY_VER(dev_priv, 2) || crtc_state->active_planes)
> + if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
> intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
>
> if (crtc_state->has_pch_encoder) {
> @@ -10283,7 +10283,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> * chance of catching underruns with the intermediate watermarks
> * vs. the new plane configuration.
> */
> - if (IS_DISPLAY_VER(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
> + if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
>
> if (dev_priv->display.optimize_watermarks)
> @@ -10862,7 +10862,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> intel_ddi_init(dev_priv, PORT_C);
> intel_ddi_init(dev_priv, PORT_D);
> icl_dsi_init(dev_priv);
> - } else if (IS_DISPLAY_VER(dev_priv, 11)) {
> + } else if (DISPLAY_VER(dev_priv) == 11) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> intel_ddi_init(dev_priv, PORT_C);
> @@ -10903,7 +10903,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> */
> found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
> /* WaIgnoreDDIAStrap: skl */
> - if (found || IS_DISPLAY_VER(dev_priv, 9))
> + if (found || DISPLAY_VER(dev_priv) == 9)
> intel_ddi_init(dev_priv, PORT_A);
>
> /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
> @@ -10928,7 +10928,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> /*
> * On SKL we don't have a way to detect DDI-E so we rely on VBT.
> */
> - if (IS_DISPLAY_VER(dev_priv, 9) &&
> + if (DISPLAY_VER(dev_priv) == 9 &&
> intel_bios_is_port_present(dev_priv, PORT_E))
> intel_ddi_init(dev_priv, PORT_E);
>
> @@ -11019,7 +11019,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> } else if (IS_PINEVIEW(dev_priv)) {
> intel_lvds_init(dev_priv);
> intel_crt_init(dev_priv);
> - } else if (IS_DISPLAY_RANGE(dev_priv, 3, 4)) {
> + } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
> bool found = false;
>
> if (IS_MOBILE(dev_priv))
> @@ -11063,7 +11063,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
>
> if (SUPPORTS_TV(dev_priv))
> intel_tv_init(dev_priv);
> - } else if (IS_DISPLAY_VER(dev_priv, 2)) {
> + } else if (DISPLAY_VER(dev_priv) == 2) {
> if (IS_I85X(dev_priv))
> intel_lvds_init(dev_priv);
>
> @@ -11734,7 +11734,7 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
> } else if (DISPLAY_VER(i915) >= 4) {
> mode_config->max_width = 8192;
> mode_config->max_height = 8192;
> - } else if (IS_DISPLAY_VER(i915, 3)) {
> + } else if (DISPLAY_VER(i915) == 3) {
> mode_config->max_width = 4096;
> mode_config->max_height = 4096;
> } else {
> @@ -12627,7 +12627,7 @@ static void intel_early_display_was(struct drm_i915_private *dev_priv)
> * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
> * Also known as Wa_14010480278.
> */
> - if (IS_DISPLAY_RANGE(dev_priv, 10, 12))
> + if (IS_DISPLAY_VER(dev_priv, 10, 12))
> intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
> intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index ad30947c58a3..0af1dee1ac95 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -550,7 +550,7 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
> if (drm_WARN_ON(&dev_priv->drm, !dig_port))
> return;
>
> - if (IS_DISPLAY_VER(dev_priv, 11) && dig_port->tc_legacy_port)
> + if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port)
> return;
>
> drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
> @@ -619,7 +619,7 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
> * exit sequence.
> */
> timeout_expected = is_tbt;
> - if (IS_DISPLAY_VER(dev_priv, 11) && dig_port->tc_legacy_port) {
> + if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port) {
> icl_tc_cold_exit(dev_priv);
> timeout_expected = true;
> }
> @@ -709,7 +709,7 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
> * BIOS's own request bits, which are forced-on for these power wells
> * when exiting DC5/6.
> */
> - if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv) &&
> + if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
> (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
> val |= intel_de_read(dev_priv, regs->bios);
>
> @@ -807,7 +807,7 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
> if (DISPLAY_VER(dev_priv) >= 12)
> mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
> | DC_STATE_EN_DC9;
> - else if (IS_DISPLAY_VER(dev_priv, 11))
> + else if (DISPLAY_VER(dev_priv) == 11)
> mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
> else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> mask |= DC_STATE_EN_DC9;
> @@ -1066,7 +1066,7 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
> drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n");
>
> /* Wa Display #1183: skl,kbl,cfl */
> - if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv))
> + if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
> intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1,
> intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
>
> @@ -1093,7 +1093,7 @@ static void skl_enable_dc6(struct drm_i915_private *dev_priv)
> drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n");
>
> /* Wa Display #1183: skl,kbl,cfl */
> - if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv))
> + if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
> intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1,
> intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
>
> @@ -4694,9 +4694,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
> } else if (IS_ROCKETLAKE(dev_priv)) {
> err = set_power_wells(power_domains, rkl_power_wells);
> - } else if (IS_DISPLAY_VER(dev_priv, 12)) {
> + } else if (DISPLAY_VER(dev_priv) == 12) {
> err = set_power_wells(power_domains, tgl_power_wells);
> - } else if (IS_DISPLAY_VER(dev_priv, 11)) {
> + } else if (DISPLAY_VER(dev_priv) == 11) {
> err = set_power_wells(power_domains, icl_power_wells);
> } else if (IS_CNL_WITH_PORT_F(dev_priv)) {
> err = set_power_wells(power_domains, cnl_power_wells);
> @@ -4708,7 +4708,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> err = set_power_wells(power_domains, glk_power_wells);
> } else if (IS_BROXTON(dev_priv)) {
> err = set_power_wells(power_domains, bxt_power_wells);
> - } else if (IS_DISPLAY_VER(dev_priv, 9)) {
> + } else if (DISPLAY_VER(dev_priv) == 9) {
> err = set_power_wells(power_domains, skl_power_wells);
> } else if (IS_CHERRYVIEW(dev_priv)) {
> err = set_power_wells(power_domains, chv_power_wells);
> @@ -4853,7 +4853,7 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
> * expect us to program the abox_ctl0 register as well, even though
> * we don't have to program other instance-0 registers like BW_BUDDY.
> */
> - if (IS_DISPLAY_VER(dev_priv, 12))
> + if (DISPLAY_VER(dev_priv) == 12)
> abox_regs |= BIT(0);
>
> for_each_set_bit(i, &abox_regs, sizeof(abox_regs))
> @@ -5450,7 +5450,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> intel_csr_load_program(dev_priv);
>
> /* Wa_14011508470 */
> - if (IS_DISPLAY_VER(dev_priv, 12)) {
> + if (DISPLAY_VER(dev_priv) == 12) {
> val = DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM |
> DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR;
> intel_uncore_rmw(&dev_priv->uncore, GEN11_CHICKEN_DCPR_2, 0, val);
> @@ -5665,7 +5665,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
> cnl_display_core_init(i915, resume);
> } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
> bxt_display_core_init(i915, resume);
> - } else if (IS_DISPLAY_VER(i915, 9)) {
> + } else if (DISPLAY_VER(i915) == 9) {
> skl_display_core_init(i915, resume);
> } else if (IS_CHERRYVIEW(i915)) {
> mutex_lock(&power_domains->lock);
> @@ -5826,7 +5826,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
> cnl_display_core_uninit(i915);
> else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
> bxt_display_core_uninit(i915);
> - else if (IS_DISPLAY_VER(i915, 9))
> + else if (DISPLAY_VER(i915) == 9)
> skl_display_core_uninit(i915);
>
> power_domains->display_core_suspended = true;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 6750949aa261..5ee953aaa00c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -215,7 +215,7 @@ bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> return DISPLAY_VER(dev_priv) >= 12 ||
> - (IS_DISPLAY_VER(dev_priv, 11) &&
> + (DISPLAY_VER(dev_priv) == 11 &&
> encoder->port != PORT_A);
> }
>
> @@ -295,7 +295,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
> source_rates = cnl_rates;
> size = ARRAY_SIZE(cnl_rates);
> - if (IS_DISPLAY_VER(dev_priv, 10))
> + if (DISPLAY_VER(dev_priv) == 10)
> max_rate = cnl_max_source_rate(intel_dp);
> else if (IS_JSL_EHL(dev_priv))
> max_rate = ehl_max_source_rate(intel_dp);
> @@ -304,7 +304,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
> source_rates = bxt_rates;
> size = ARRAY_SIZE(bxt_rates);
> - } else if (IS_DISPLAY_VER(dev_priv, 9)) {
> + } else if (DISPLAY_VER(dev_priv) == 9) {
> source_rates = skl_rates;
> size = ARRAY_SIZE(skl_rates);
> } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
> @@ -916,7 +916,7 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
> if (DISPLAY_VER(dev_priv) >= 12)
> return true;
>
> - if (IS_DISPLAY_VER(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
> + if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
> return true;
>
> return false;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 158f271299a4..9114953f57f1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1356,7 +1356,7 @@ intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
> dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
> else if (IS_PINEVIEW(dev_priv))
> dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
> - else if (!IS_DISPLAY_VER(dev_priv, 2))
> + else if (DISPLAY_VER(dev_priv) != 2)
> dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
> else
> dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index e32de7c848e9..e1c916640768 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4443,7 +4443,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
> dpll_mgr = &cnl_pll_mgr;
> else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> dpll_mgr = &bxt_pll_mgr;
> - else if (IS_DISPLAY_VER(dev_priv, 9))
> + else if (DISPLAY_VER(dev_priv) == 9)
> dpll_mgr = &skl_pll_mgr;
> else if (HAS_DDI(dev_priv))
> dpll_mgr = &hsw_pll_mgr;
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index fca41ac5b8e1..0ec9ad7220a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -84,7 +84,7 @@ int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
>
> unsigned int intel_tile_size(const struct drm_i915_private *i915)
> {
> - return IS_DISPLAY_VER(i915, 2) ? 2048 : 4096;
> + return DISPLAY_VER(i915) == 2 ? 2048 : 4096;
> }
>
> unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 04d9c7d22b04..a6bf18835d36 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -67,7 +67,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
> int lines;
>
> intel_fbc_get_plane_source_size(cache, NULL, &lines);
> - if (IS_DISPLAY_VER(dev_priv, 7))
> + if (DISPLAY_VER(dev_priv) == 7)
> lines = min(lines, 2048);
> else if (DISPLAY_VER(dev_priv) >= 8)
> lines = min(lines, 2560);
> @@ -109,7 +109,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
> cfb_pitch = params->fb.stride;
>
> /* FBC_CTL wants 32B or 64B units */
> - if (IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> cfb_pitch = (cfb_pitch / 32) - 1;
> else
> cfb_pitch = (cfb_pitch / 64) - 1;
> @@ -118,7 +118,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
> for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
> intel_de_write(dev_priv, FBC_TAG(i), 0);
>
> - if (IS_DISPLAY_VER(dev_priv, 4)) {
> + if (DISPLAY_VER(dev_priv) == 4) {
> u32 fbc_ctl2;
>
> /* Set it up... */
> @@ -302,7 +302,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
> int threshold = dev_priv->fbc.threshold;
>
> /* Display WA #0529: skl, kbl, bxt. */
> - if (IS_DISPLAY_VER(dev_priv, 9)) {
> + if (DISPLAY_VER(dev_priv) == 9) {
> u32 val = intel_de_read(dev_priv, CHICKEN_MISC_4);
>
> val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
> @@ -445,7 +445,7 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv,
> * reserved range size, so it always assumes the maximum (8mb) is used.
> * If we enable FBC using a CFB on that memory range we'll get FIFO
> * underruns, even if that range is not reserved by the BIOS. */
> - if (IS_BROADWELL(dev_priv) || (IS_DISPLAY_VER(dev_priv, 9) &&
> + if (IS_BROADWELL(dev_priv) || (DISPLAY_VER(dev_priv) == 9 &&
> !IS_BROXTON(dev_priv)))
> end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
> else
> @@ -591,14 +591,14 @@ static bool stride_is_valid(struct drm_i915_private *dev_priv,
> if (stride < 512)
> return false;
>
> - if (IS_DISPLAY_VER(dev_priv, 2) || IS_DISPLAY_VER(dev_priv, 3))
> + if (DISPLAY_VER(dev_priv) == 2 || DISPLAY_VER(dev_priv) == 3)
> return stride == 4096 || stride == 8192;
>
> - if (IS_DISPLAY_VER(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048)
> + if (DISPLAY_VER(dev_priv) == 4 && !IS_G4X(dev_priv) && stride < 2048)
> return false;
>
> /* Display WA #1105: skl,bxt,kbl,cfl,glk */
> - if (IS_DISPLAY_VER(dev_priv, 9) &&
> + if (DISPLAY_VER(dev_priv) == 9 &&
> modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
> return false;
>
> @@ -618,7 +618,7 @@ static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
> case DRM_FORMAT_XRGB1555:
> case DRM_FORMAT_RGB565:
> /* 16bpp not supported on gen2 */
> - if (IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> return false;
> /* WaFbcOnly1to1Ratio:ctg */
> if (IS_G4X(dev_priv))
> @@ -760,7 +760,7 @@ static u16 intel_fbc_gen9_wa_cfb_stride(struct drm_i915_private *dev_priv)
> struct intel_fbc *fbc = &dev_priv->fbc;
> struct intel_fbc_state_cache *cache = &fbc->state_cache;
>
> - if ((IS_DISPLAY_VER(dev_priv, 9)) &&
> + if ((DISPLAY_VER(dev_priv) == 9) &&
> cache->fb.modifier != I915_FORMAT_MOD_X_TILED)
> return DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8;
> else
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> index 9605a1064366..0fce9fd6e0a9 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> @@ -271,7 +271,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
> i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
> else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
> ilk_set_fifo_underrun_reporting(dev, pipe, enable);
> - else if (IS_DISPLAY_VER(dev_priv, 7))
> + else if (DISPLAY_VER(dev_priv) == 7)
> ivb_set_fifo_underrun_reporting(dev, pipe, enable, old);
> else if (DISPLAY_VER(dev_priv) >= 8)
> bdw_set_fifo_underrun_reporting(dev, pipe, enable);
> @@ -432,7 +432,7 @@ void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
>
> if (HAS_GMCH(dev_priv))
> i9xx_check_fifo_underruns(crtc);
> - else if (IS_DISPLAY_VER(dev_priv, 7))
> + else if (DISPLAY_VER(dev_priv) == 7)
> ivb_check_fifo_underruns(crtc);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index 2ea6adc3bd3e..17ab3cb81e02 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -109,7 +109,7 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
> return &gmbus_pins_cnp[pin];
> else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> return &gmbus_pins_bxt[pin];
> - else if (IS_DISPLAY_VER(dev_priv, 9))
> + else if (DISPLAY_VER(dev_priv) == 9)
> return &gmbus_pins_skl[pin];
> else if (IS_BROADWELL(dev_priv))
> return &gmbus_pins_bdw[pin];
> @@ -130,7 +130,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
> size = ARRAY_SIZE(gmbus_pins_cnp);
> else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_bxt);
> - else if (IS_DISPLAY_VER(dev_priv, 9))
> + else if (DISPLAY_VER(dev_priv) == 9)
> size = ARRAY_SIZE(gmbus_pins_skl);
> else if (IS_BROADWELL(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_bdw);
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 75050a040577..d254fe67ab7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -291,7 +291,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
> * process from other platforms. These platforms use the GT Driver
> * Mailbox interface.
> */
> - if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) {
> + if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
> ret = sandybridge_pcode_write(dev_priv,
> SKL_PCODE_LOAD_HDCP_KEYS, 1);
> if (ret) {
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index f2d1fef8bd9d..47a8f0a1c5e2 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1978,7 +1978,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
>
> /* Display Wa_1405510057:icl,ehl */
> if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
> - bpc == 10 && IS_DISPLAY_VER(dev_priv, 11) &&
> + bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
> (adjusted_mode->crtc_hblank_end -
> adjusted_mode->crtc_hblank_start) % 8 == 2)
> return false;
> @@ -2715,7 +2715,7 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
> ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
> else if (IS_ROCKETLAKE(dev_priv))
> ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
> - else if (IS_DISPLAY_VER(dev_priv, 9) && HAS_PCH_TGP(dev_priv))
> + else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
> ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
> else if (HAS_PCH_MCC(dev_priv))
> ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
> index f31a368f34c5..dd12d15f47c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -280,7 +280,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
> * special lvds dither control bit on pch-split platforms, dithering is
> * only controlled through the PIPECONF reg.
> */
> - if (IS_DISPLAY_VER(dev_priv, 4)) {
> + if (DISPLAY_VER(dev_priv) == 4) {
> /*
> * Bspec wording suggests that LVDS port dithering only exists
> * for 18bpp panels.
> diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
> index e477b6114a60..d1255911a327 100644
> --- a/drivers/gpu/drm/i915/display/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/display/intel_overlay.c
> @@ -550,7 +550,7 @@ static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 widt
> {
> u32 sw;
>
> - if (IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> sw = ALIGN((offset & 31) + width, 32);
> else
> sw = ALIGN((offset & 63) + width, 64);
> @@ -818,7 +818,7 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay,
> oconfig |= OCONF_CC_OUT_8BIT;
> if (crtc_state->gamma_enable)
> oconfig |= OCONF_GAMMA2_ENABLE;
> - if (IS_DISPLAY_VER(dev_priv, 4))
> + if (DISPLAY_VER(dev_priv) == 4)
> oconfig |= OCONF_CSC_MODE_BT709;
> oconfig |= pipe == 0 ?
> OCONF_PIPE_A : OCONF_PIPE_B;
> @@ -1052,7 +1052,7 @@ static int check_overlay_src(struct drm_i915_private *dev_priv,
>
> if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
> return -EINVAL;
> - if (IS_DISPLAY_VER(dev_priv, 4) && rec->stride_Y < 512)
> + if (DISPLAY_VER(dev_priv) == 4 && rec->stride_Y < 512)
> return -EINVAL;
>
> tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
> @@ -1279,7 +1279,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
> attrs->contrast = overlay->contrast;
> attrs->saturation = overlay->saturation;
>
> - if (!IS_DISPLAY_VER(dev_priv, 2)) {
> + if (DISPLAY_VER(dev_priv) != 2) {
> attrs->gamma0 = intel_de_read(dev_priv, OGAMC0);
> attrs->gamma1 = intel_de_read(dev_priv, OGAMC1);
> attrs->gamma2 = intel_de_read(dev_priv, OGAMC2);
> @@ -1303,7 +1303,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
> update_reg_attrs(overlay, overlay->regs);
>
> if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
> - if (IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> goto out_unlock;
>
> if (overlay->active) {
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
> index 2fcbb2ba2d78..551fcaa77c2c 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -667,7 +667,7 @@ static void i9xx_set_backlight(const struct drm_connector_state *conn_state, u32
> pci_write_config_byte(to_pci_dev(dev_priv->drm.dev), LBPC, lbpc);
> }
>
> - if (IS_DISPLAY_VER(dev_priv, 4)) {
> + if (DISPLAY_VER(dev_priv) == 4) {
> mask = BACKLIGHT_DUTY_CYCLE_MASK;
> } else {
> level <<= 1;
> @@ -1040,7 +1040,7 @@ static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state,
> * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2
> * that has backlight.
> */
> - if (IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> intel_de_write(dev_priv, BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);
> }
>
> @@ -1728,7 +1728,7 @@ static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unu
>
> ctl = intel_de_read(dev_priv, BLC_PWM_CTL);
>
> - if (IS_DISPLAY_VER(dev_priv, 2) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
> + if (DISPLAY_VER(dev_priv) == 2 || IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
> panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE;
>
> if (IS_PINEVIEW(dev_priv))
> @@ -2178,7 +2178,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
> } else {
> panel->backlight.pwm_funcs = &vlv_pwm_funcs;
> }
> - } else if (IS_DISPLAY_VER(dev_priv, 4)) {
> + } else if (DISPLAY_VER(dev_priv) == 4) {
> panel->backlight.pwm_funcs = &i965_pwm_funcs;
> } else {
> panel->backlight.pwm_funcs = &i9xx_pwm_funcs;
> diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> index 7c8e0d76207f..0f6de96e6d43 100644
> --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> @@ -409,7 +409,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
> enum pipe pipe,
> enum intel_pipe_crc_source *source, u32 *val)
> {
> - if (IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> return i8xx_pipe_crc_ctl_reg(source, val);
> else if (DISPLAY_VER(dev_priv) < 5)
> return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
> @@ -539,7 +539,7 @@ static int
> intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
> const enum intel_pipe_crc_source source)
> {
> - if (IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> return i8xx_crc_source_valid(dev_priv, source);
> else if (DISPLAY_VER(dev_priv) < 5)
> return i9xx_crc_source_valid(dev_priv, source);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index bf8e4ede2a6c..85301e894378 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -782,7 +782,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> psr_max_h = 4096;
> psr_max_v = 2304;
> max_bpp = 24;
> - } else if (IS_DISPLAY_VER(dev_priv, 9)) {
> + } else if (DISPLAY_VER(dev_priv) == 9) {
> psr_max_h = 3640;
> psr_max_v = 2304;
> max_bpp = 24;
> @@ -922,7 +922,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> hsw_psr_setup_aux(intel_dp);
>
> - if (intel_dp->psr.psr2_enabled && IS_DISPLAY_VER(dev_priv, 9)) {
> + if (intel_dp->psr.psr2_enabled && DISPLAY_VER(dev_priv) == 9) {
> i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
> u32 chicken = intel_de_read(dev_priv, reg);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 71b8edafb1c3..88085486ee59 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -28,7 +28,7 @@ tc_cold_get_power_domain(struct intel_digital_port *dig_port)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>
> - if (IS_DISPLAY_VER(i915, 11))
> + if (DISPLAY_VER(i915) == 11)
> return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> else
> return POWER_DOMAIN_TC_COLD_OFF;
> @@ -40,7 +40,7 @@ tc_cold_block(struct intel_digital_port *dig_port)
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> enum intel_display_power_domain domain;
>
> - if (IS_DISPLAY_VER(i915, 11) && !dig_port->tc_legacy_port)
> + if (DISPLAY_VER(i915) == 11 && !dig_port->tc_legacy_port)
> return 0;
>
> domain = tc_cold_get_power_domain(dig_port);
> @@ -71,7 +71,7 @@ assert_tc_cold_blocked(struct intel_digital_port *dig_port)
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> bool enabled;
>
> - if (IS_DISPLAY_VER(i915, 11) && !dig_port->tc_legacy_port)
> + if (DISPLAY_VER(i915) == 11 && !dig_port->tc_legacy_port)
> return;
>
> enabled = intel_display_power_is_enabled(i915,
> diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
> index e558f121ec4e..2c5c77693474 100644
> --- a/drivers/gpu/drm/i915/display/intel_tv.c
> +++ b/drivers/gpu/drm/i915/display/intel_tv.c
> @@ -1165,7 +1165,7 @@ intel_tv_get_config(struct intel_encoder *encoder,
> static bool intel_tv_source_too_wide(struct drm_i915_private *dev_priv,
> int hdisplay)
> {
> - return IS_DISPLAY_VER(dev_priv, 3) && hdisplay > 1024;
> + return DISPLAY_VER(dev_priv) == 3 && hdisplay > 1024;
> }
>
> static bool intel_tv_vert_scaling(const struct drm_display_mode *tv_mode,
> @@ -1789,7 +1789,7 @@ intel_tv_get_modes(struct drm_connector *connector)
> continue;
>
> /* no vertical scaling with wide sources on gen3 */
> - if (IS_DISPLAY_VER(dev_priv, 3) && input->w > 1024 &&
> + if (DISPLAY_VER(dev_priv) == 3 && input->w > 1024 &&
> input->h > intel_tv_mode_vdisplay(tv_mode))
> continue;
>
> @@ -1978,7 +1978,7 @@ intel_tv_init(struct drm_i915_private *dev_priv)
> /* Create TV properties then attach current values */
> for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
> /* 1080p50/1080p60 not supported on gen3 */
> - if (IS_DISPLAY_VER(dev_priv, 3) &&
> + if (DISPLAY_VER(dev_priv) == 3 &&
> tv_modes[i].oversample == 1)
> break;
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 098636c811a8..8a8e3b5e6ef0 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1208,7 +1208,7 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s
> * than the cursor ending less than 4 pixels from the left edge of the
> * screen may cause FIFO underflow and display corruption.
> */
> - if (IS_DISPLAY_VER(dev_priv, 10) &&
> + if (DISPLAY_VER(dev_priv) == 10 &&
> (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
> drm_dbg_kms(&dev_priv->drm,
> "requested plane X %s position %d invalid (valid range %d-%d)\n",
> @@ -1695,7 +1695,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> return false;
>
> - if (IS_DISPLAY_VER(dev_priv, 9) && pipe == PIPE_C)
> + if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C)
> return false;
>
> if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
> @@ -2007,8 +2007,8 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> plane->check_plane = skl_plane_check;
>
> if (plane_id == PLANE_PRIMARY) {
> - plane->need_async_flip_disable_wa = IS_DISPLAY_RANGE(dev_priv,
> - 9, 10);
> + plane->need_async_flip_disable_wa = IS_DISPLAY_VER(dev_priv,
> + 9, 10);
> plane->async_flip = skl_plane_async_flip;
> plane->enable_flip_done = skl_plane_enable_flip_done;
> plane->disable_flip_done = skl_plane_disable_flip_done;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8c62bb2abd31..907c66efb469 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1238,9 +1238,8 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
> #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
>
> #define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
> -#define IS_DISPLAY_RANGE(i915, from, until) \
> +#define IS_DISPLAY_VER(i915, from, until) \
> (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
> -#define IS_DISPLAY_VER(i915, v) (DISPLAY_VER(i915) == (v))
>
> #define REVID_FOREVER 0xff
> #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 920327bdcb10..798ecc718e3f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -806,7 +806,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
> if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> vtotal /= 2;
>
> - if (IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
> else
> position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
> @@ -857,7 +857,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
> int vbl_start, vbl_end, hsync_start, htotal, vtotal;
> unsigned long irqflags;
> bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 ||
> - IS_G4X(dev_priv) || IS_DISPLAY_VER(dev_priv, 2) ||
> + IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) == 2 ||
> crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
>
> if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
> @@ -2077,7 +2077,7 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
> intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);
> }
>
> - if (IS_DISPLAY_VER(dev_priv, 5) && de_iir & DE_PCU_EVENT)
> + if (DISPLAY_VER(dev_priv) == 5 && de_iir & DE_PCU_EVENT)
> gen5_rps_irq_handler(&dev_priv->gt.rps);
> }
>
> @@ -2287,10 +2287,10 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
> GEN9_AUX_CHANNEL_C |
> GEN9_AUX_CHANNEL_D;
>
> - if (IS_CNL_WITH_PORT_F(dev_priv) || IS_DISPLAY_VER(dev_priv, 11))
> + if (IS_CNL_WITH_PORT_F(dev_priv) || DISPLAY_VER(dev_priv) == 11)
> mask |= CNL_AUX_CHANNEL_F;
>
> - if (IS_DISPLAY_VER(dev_priv, 11))
> + if (DISPLAY_VER(dev_priv) == 11)
> mask |= ICL_AUX_CHANNEL_E;
>
> return mask;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3f6d8b502a61..eaf4c072ade0 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2339,7 +2339,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>
> if (IS_I945GM(dev_priv))
> wm_info = &i945_wm_info;
> - else if (!IS_DISPLAY_VER(dev_priv, 2))
> + else if (DISPLAY_VER(dev_priv) != 2)
> wm_info = &i915_wm_info;
> else
> wm_info = &i830_a_wm_info;
> @@ -2353,7 +2353,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> crtc->base.primary->state->fb;
> int cpp;
>
> - if (IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> cpp = 4;
> else
> cpp = fb->format->cpp[0];
> @@ -2368,7 +2368,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> planea_wm = wm_info->max_wm;
> }
>
> - if (IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> wm_info = &i830_bc_wm_info;
>
> fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
> @@ -2380,7 +2380,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> crtc->base.primary->state->fb;
> int cpp;
>
> - if (IS_DISPLAY_VER(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> cpp = 4;
> else
> cpp = fb->format->cpp[0];
> @@ -2967,7 +2967,7 @@ static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
> u16 wm[5])
> {
> /* ILK sprite LP0 latency is 1300 ns */
> - if (IS_DISPLAY_VER(dev_priv, 5))
> + if (DISPLAY_VER(dev_priv) == 5)
> wm[0] = 13;
> }
>
> @@ -2975,7 +2975,7 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
> u16 wm[5])
> {
> /* ILK cursor LP0 latency is 1300 ns */
> - if (IS_DISPLAY_VER(dev_priv, 5))
> + if (DISPLAY_VER(dev_priv) == 5)
> wm[0] = 13;
> }
>
> @@ -3105,7 +3105,7 @@ static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
> intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
> intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
>
> - if (IS_DISPLAY_VER(dev_priv, 6)) {
> + if (DISPLAY_VER(dev_priv) == 6) {
> snb_wm_latency_quirk(dev_priv);
> snb_wm_lp3_irq_quirk(dev_priv);
> }
> @@ -3354,7 +3354,7 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv,
> * What we should check here is whether FBC can be
> * enabled sometime later.
> */
> - if (IS_DISPLAY_VER(dev_priv, 5) && !merged->fbc_wm_enabled &&
> + if (DISPLAY_VER(dev_priv) == 5 && !merged->fbc_wm_enabled &&
> intel_fbc_is_active(dev_priv)) {
> for (level = 2; level <= max_level; level++) {
> struct intel_wm_level *wm = &merged->wm[level];
> @@ -3654,7 +3654,7 @@ u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
> */
> static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
> {
> - return IS_DISPLAY_VER(dev_priv, 9);
> + return DISPLAY_VER(dev_priv) == 9;
> }
>
> static bool
> @@ -3680,13 +3680,13 @@ skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
> }
>
> drm_dbg(&dev_priv->drm, "Couldn't read SAGV block time!\n");
> - } else if (IS_DISPLAY_VER(dev_priv, 11)) {
> + } else if (DISPLAY_VER(dev_priv) == 11) {
> dev_priv->sagv_block_time_us = 10;
> return;
> - } else if (IS_DISPLAY_VER(dev_priv, 10)) {
> + } else if (DISPLAY_VER(dev_priv) == 10) {
> dev_priv->sagv_block_time_us = 20;
> return;
> - } else if (IS_DISPLAY_VER(dev_priv, 9)) {
> + } else if (DISPLAY_VER(dev_priv) == 9) {
> dev_priv->sagv_block_time_us = 30;
> return;
> } else {
> @@ -4613,9 +4613,9 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes)
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> - if (IS_DISPLAY_VER(dev_priv, 12))
> + if (DISPLAY_VER(dev_priv) == 12)
> return tgl_compute_dbuf_slices(pipe, active_pipes);
> - else if (IS_DISPLAY_VER(dev_priv, 11))
> + else if (DISPLAY_VER(dev_priv) == 11)
> return icl_compute_dbuf_slices(pipe, active_pipes);
> /*
> * For anything else just return one slice yet.
> @@ -4986,7 +4986,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> * Wa_1408961008:icl, ehl
> * Underruns with WM1+ disabled
> */
> - if (IS_DISPLAY_VER(dev_priv, 11) &&
> + if (DISPLAY_VER(dev_priv) == 11 &&
> level == 1 && wm->wm[0].enable) {
> wm->wm[level].blocks = wm->wm[0].blocks;
> wm->wm[level].lines = wm->wm[0].lines;
> @@ -5245,7 +5245,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
> selected_result = method2;
> } else if (latency >= wp->linetime_us) {
> - if (IS_DISPLAY_VER(dev_priv, 9))
> + if (DISPLAY_VER(dev_priv) == 9)
> selected_result = min_fixed16(method1, method2);
> else
> selected_result = method2;
> @@ -5258,7 +5258,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> lines = div_round_up_fixed16(selected_result,
> wp->plane_blocks_per_line);
>
> - if (IS_DISPLAY_VER(dev_priv, 9)) {
> + if (DISPLAY_VER(dev_priv) == 9) {
> /* Display WA #1125: skl,bxt,kbl */
> if (level == 0 && wp->rc_surface)
> blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
> @@ -5375,7 +5375,7 @@ static void skl_compute_transition_wm(struct drm_i915_private *dev_priv,
> * WaDisableTWM:skl,kbl,cfl,bxt
> * Transition WM are not recommended by HW team for GEN9
> */
> - if (IS_DISPLAY_VER(dev_priv, 9))
> + if (DISPLAY_VER(dev_priv) == 9)
> return;
>
> if (DISPLAY_VER(dev_priv) >= 11)
> @@ -5384,7 +5384,7 @@ static void skl_compute_transition_wm(struct drm_i915_private *dev_priv,
> trans_min = 14;
>
> /* Display WA #1140: glk,cnl */
> - if (IS_DISPLAY_VER(dev_priv, 10))
> + if (DISPLAY_VER(dev_priv) == 10)
> trans_amount = 0;
> else
> trans_amount = 10; /* This is configurable amount */
> @@ -7694,9 +7694,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> ilk_setup_wm_latency(dev_priv);
>
> - if ((IS_DISPLAY_VER(dev_priv, 5) && dev_priv->wm.pri_latency[1] &&
> + if ((DISPLAY_VER(dev_priv) == 5 && dev_priv->wm.pri_latency[1] &&
> dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
> - (!IS_DISPLAY_VER(dev_priv, 5) && dev_priv->wm.pri_latency[0] &&
> + (DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
> dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
> dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
> dev_priv->display.compute_intermediate_wm =
> @@ -7739,12 +7739,12 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
> dev_priv->display.update_wm = NULL;
> } else
> dev_priv->display.update_wm = pnv_update_wm;
> - } else if (IS_DISPLAY_VER(dev_priv, 4)) {
> + } else if (DISPLAY_VER(dev_priv) == 4) {
> dev_priv->display.update_wm = i965_update_wm;
> - } else if (IS_DISPLAY_VER(dev_priv, 3)) {
> + } else if (DISPLAY_VER(dev_priv) == 3) {
> dev_priv->display.update_wm = i9xx_update_wm;
> dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
> - } else if (IS_DISPLAY_VER(dev_priv, 2)) {
> + } else if (DISPLAY_VER(dev_priv) == 2) {
> if (INTEL_NUM_PIPES(dev_priv) == 1) {
> dev_priv->display.update_wm = i845_update_wm;
> dev_priv->display.get_fifo_size = i845_get_fifo_size;
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 05/12] drm/i915/gt: replace gen use in intel_engine_cs
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 05/12] drm/i915/gt: replace gen use in intel_engine_cs Lucas De Marchi
@ 2021-04-13 9:36 ` Jani Nikula
0 siblings, 0 replies; 39+ messages in thread
From: Jani Nikula @ 2021-04-13 9:36 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On Mon, 12 Apr 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Start using the new fields graphics_version for the previous gen checks.
> Here we rename the "gen" field and replace the comparisons using it to
> start using the new GRAPHICS_VER(). Other uses of INTEL_GEN() were left
> as is for automatic conversion later.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 40 ++++++++++----------
> drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 18 ++++-----
> 2 files changed, 29 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index efe935f80c1a..6dbdbde00f14 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -45,9 +45,9 @@ struct engine_info {
> unsigned int hw_id;
> u8 class;
> u8 instance;
> - /* mmio bases table *must* be sorted in reverse gen order */
> + /* mmio bases table *must* be sorted in reverse graphics_ver order */
> struct engine_mmio_base {
> - u32 gen : 8;
> + u32 graphics_ver : 8;
> u32 base : 24;
> } mmio_bases[MAX_MMIO_BASES];
> };
> @@ -58,7 +58,7 @@ static const struct engine_info intel_engines[] = {
> .class = RENDER_CLASS,
> .instance = 0,
> .mmio_bases = {
> - { .gen = 1, .base = RENDER_RING_BASE }
> + { .graphics_ver = 1, .base = RENDER_RING_BASE }
> },
> },
> [BCS0] = {
> @@ -66,7 +66,7 @@ static const struct engine_info intel_engines[] = {
> .class = COPY_ENGINE_CLASS,
> .instance = 0,
> .mmio_bases = {
> - { .gen = 6, .base = BLT_RING_BASE }
> + { .graphics_ver = 6, .base = BLT_RING_BASE }
> },
> },
> [VCS0] = {
> @@ -74,9 +74,9 @@ static const struct engine_info intel_engines[] = {
> .class = VIDEO_DECODE_CLASS,
> .instance = 0,
> .mmio_bases = {
> - { .gen = 11, .base = GEN11_BSD_RING_BASE },
> - { .gen = 6, .base = GEN6_BSD_RING_BASE },
> - { .gen = 4, .base = BSD_RING_BASE }
> + { .graphics_ver = 11, .base = GEN11_BSD_RING_BASE },
> + { .graphics_ver = 6, .base = GEN6_BSD_RING_BASE },
> + { .graphics_ver = 4, .base = BSD_RING_BASE }
> },
> },
> [VCS1] = {
> @@ -84,8 +84,8 @@ static const struct engine_info intel_engines[] = {
> .class = VIDEO_DECODE_CLASS,
> .instance = 1,
> .mmio_bases = {
> - { .gen = 11, .base = GEN11_BSD2_RING_BASE },
> - { .gen = 8, .base = GEN8_BSD2_RING_BASE }
> + { .graphics_ver = 11, .base = GEN11_BSD2_RING_BASE },
> + { .graphics_ver = 8, .base = GEN8_BSD2_RING_BASE }
> },
> },
> [VCS2] = {
> @@ -93,7 +93,7 @@ static const struct engine_info intel_engines[] = {
> .class = VIDEO_DECODE_CLASS,
> .instance = 2,
> .mmio_bases = {
> - { .gen = 11, .base = GEN11_BSD3_RING_BASE }
> + { .graphics_ver = 11, .base = GEN11_BSD3_RING_BASE }
> },
> },
> [VCS3] = {
> @@ -101,7 +101,7 @@ static const struct engine_info intel_engines[] = {
> .class = VIDEO_DECODE_CLASS,
> .instance = 3,
> .mmio_bases = {
> - { .gen = 11, .base = GEN11_BSD4_RING_BASE }
> + { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE }
> },
> },
> [VECS0] = {
> @@ -109,8 +109,8 @@ static const struct engine_info intel_engines[] = {
> .class = VIDEO_ENHANCEMENT_CLASS,
> .instance = 0,
> .mmio_bases = {
> - { .gen = 11, .base = GEN11_VEBOX_RING_BASE },
> - { .gen = 7, .base = VEBOX_RING_BASE }
> + { .graphics_ver = 11, .base = GEN11_VEBOX_RING_BASE },
> + { .graphics_ver = 7, .base = VEBOX_RING_BASE }
> },
> },
> [VECS1] = {
> @@ -118,7 +118,7 @@ static const struct engine_info intel_engines[] = {
> .class = VIDEO_ENHANCEMENT_CLASS,
> .instance = 1,
> .mmio_bases = {
> - { .gen = 11, .base = GEN11_VEBOX2_RING_BASE }
> + { .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE }
> },
> },
> };
> @@ -146,9 +146,9 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
>
> switch (class) {
> case RENDER_CLASS:
> - switch (INTEL_GEN(gt->i915)) {
> + switch (GRAPHICS_VER(gt->i915)) {
> default:
> - MISSING_CASE(INTEL_GEN(gt->i915));
> + MISSING_CASE(GRAPHICS_VER(gt->i915));
> return DEFAULT_LR_CONTEXT_RENDER_SIZE;
> case 12:
> case 11:
> @@ -184,8 +184,8 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
> */
> cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
> drm_dbg(>->i915->drm,
> - "gen%d CXT_SIZE = %d bytes [0x%08x]\n",
> - INTEL_GEN(gt->i915), cxt_size * 64,
> + "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n",
> + GRAPHICS_VER(gt->i915), cxt_size * 64,
> cxt_size - 1);
> return round_up(cxt_size * 64, PAGE_SIZE);
> case 3:
> @@ -201,7 +201,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
> case VIDEO_DECODE_CLASS:
> case VIDEO_ENHANCEMENT_CLASS:
> case COPY_ENGINE_CLASS:
> - if (INTEL_GEN(gt->i915) < 8)
> + if (GRAPHICS_VER(gt->i915) < 8)
> return 0;
> return GEN8_LR_CONTEXT_OTHER_SIZE;
> }
> @@ -213,7 +213,7 @@ static u32 __engine_mmio_base(struct drm_i915_private *i915,
> int i;
>
> for (i = 0; i < MAX_MMIO_BASES; i++)
> - if (INTEL_GEN(i915) >= bases[i].gen)
> + if (GRAPHICS_VER(i915) >= bases[i].graphics_ver)
> break;
>
> GEM_BUG_ON(i == MAX_MMIO_BASES);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> index b32814a1f20b..3453eb77c498 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> @@ -376,34 +376,34 @@ static int intel_mmio_bases_check(void *arg)
> u8 prev = U8_MAX;
>
> for (j = 0; j < MAX_MMIO_BASES; j++) {
> - u8 gen = info->mmio_bases[j].gen;
> + u8 ver = info->mmio_bases[j].graphics_ver;
> u32 base = info->mmio_bases[j].base;
>
> - if (gen >= prev) {
> - pr_err("%s(%s, class:%d, instance:%d): mmio base for gen %x is before the one for gen %x\n",
> + if (ver >= prev) {
> + pr_err("%s(%s, class:%d, instance:%d): mmio base for graphics ver %u is before the one for ver %u\n",
> __func__,
> intel_engine_class_repr(info->class),
> info->class, info->instance,
> - prev, gen);
> + prev, ver);
> return -EINVAL;
> }
>
> - if (gen == 0)
> + if (ver == 0)
> break;
>
> if (!base) {
> - pr_err("%s(%s, class:%d, instance:%d): invalid mmio base (%x) for gen %x at entry %u\n",
> + pr_err("%s(%s, class:%d, instance:%d): invalid mmio base (%x) for graphics ver %u at entry %u\n",
> __func__,
> intel_engine_class_repr(info->class),
> info->class, info->instance,
> - base, gen, j);
> + base, ver, j);
> return -EINVAL;
> }
>
> - prev = gen;
> + prev = ver;
> }
>
> - pr_debug("%s: min gen supported for %s%d is %d\n",
> + pr_debug("%s: min graphics version supported for %s%d is %u\n",
> __func__,
> intel_engine_class_repr(info->class),
> info->instance,
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 06/12] drm/i915/selftests: replace unused mask with simple version
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 06/12] drm/i915/selftests: replace unused mask with simple version Lucas De Marchi
@ 2021-04-13 9:36 ` Jani Nikula
0 siblings, 0 replies; 39+ messages in thread
From: Jani Nikula @ 2021-04-13 9:36 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On Mon, 12 Apr 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Since its introduction 2 years ago, we never used the mask to span more
> than one gen. Replace gen_mask a single number and start using the new
> GRAPHICS_VER().
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/gt/selftest_workarounds.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> index 19850489a3fc..64937ec3f2dc 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> @@ -927,7 +927,7 @@ static int scrub_whitelisted_registers(struct intel_context *ce)
>
> struct regmask {
> i915_reg_t reg;
> - unsigned long gen_mask;
> + u8 graphics_ver;
> };
>
> static bool find_reg(struct drm_i915_private *i915,
> @@ -938,7 +938,7 @@ static bool find_reg(struct drm_i915_private *i915,
> u32 offset = i915_mmio_reg_offset(reg);
>
> while (count--) {
> - if (INTEL_INFO(i915)->gen_mask & tbl->gen_mask &&
> + if (GRAPHICS_VER(i915) == tbl->graphics_ver &&
> i915_mmio_reg_offset(tbl->reg) == offset)
> return true;
> tbl++;
> @@ -951,8 +951,8 @@ static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)
> {
> /* Alas, we must pardon some whitelists. Mistakes already made */
> static const struct regmask pardon[] = {
> - { GEN9_CTX_PREEMPT_REG, INTEL_GEN_MASK(9, 9) },
> - { GEN8_L3SQCREG4, INTEL_GEN_MASK(9, 9) },
> + { GEN9_CTX_PREEMPT_REG, 9 },
> + { GEN8_L3SQCREG4, 9 },
> };
>
> return find_reg(i915, reg, pardon, ARRAY_SIZE(pardon));
> @@ -974,7 +974,7 @@ static bool writeonly_reg(struct drm_i915_private *i915, i915_reg_t reg)
> {
> /* Some registers do not seem to behave and our writes unreadable */
> static const struct regmask wo[] = {
> - { GEN9_SLICE_COMMON_ECO_CHICKEN1, INTEL_GEN_MASK(9, 9) },
> + { GEN9_SLICE_COMMON_ECO_CHICKEN1, 9 },
> };
>
> return find_reg(i915, reg, wo, ARRAY_SIZE(wo));
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 07/12] drm/i915/selftests: eliminate use of gen_mask
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 07/12] drm/i915/selftests: eliminate use of gen_mask Lucas De Marchi
@ 2021-04-13 9:38 ` Jani Nikula
0 siblings, 0 replies; 39+ messages in thread
From: Jani Nikula @ 2021-04-13 9:38 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On Mon, 12 Apr 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Remove the remaining uses of INTEL_GEN_MASK() and the correspondent
> gen_mask in struct intel_device_info. This will allow the removal of
> gen_mask later since it's incompatible with the new per-IP versioning
> scheme.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 8 +++++---
> drivers/gpu/drm/i915/selftests/intel_uncore.c | 8 +++++---
> 2 files changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 661b50191f2b..ed5abe7be498 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -2008,12 +2008,14 @@ void intel_uncore_fini_mmio(struct intel_uncore *uncore)
> static const struct reg_whitelist {
> i915_reg_t offset_ldw;
> i915_reg_t offset_udw;
> - u16 gen_mask;
> + u8 min_graphics_ver;
> + u8 max_graphics_ver;
> u8 size;
> } reg_read_whitelist[] = { {
> .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
> .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
> - .gen_mask = INTEL_GEN_MASK(4, 12),
> + .min_graphics_ver = 4,
> + .max_graphics_ver = 12,
> .size = 8
> } };
>
> @@ -2038,7 +2040,7 @@ int i915_reg_read_ioctl(struct drm_device *dev,
> GEM_BUG_ON(entry->size > 8);
> GEM_BUG_ON(entry_offset & (entry->size - 1));
>
> - if (INTEL_INFO(i915)->gen_mask & entry->gen_mask &&
> + if (IS_GRAPHICS_VER(i915, entry->min_graphics_ver, entry->max_graphics_ver) &&
> entry_offset == (reg->offset & -entry->size))
> break;
> entry++;
> diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> index 0e4e6be0101d..f76c9bcec735 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> @@ -125,17 +125,19 @@ static int live_forcewake_ops(void *arg)
> {
> static const struct reg {
> const char *name;
> + u8 min_graphics_ver;
> + u8 max_graphics_ver;
> unsigned long platforms;
> unsigned int offset;
> } registers[] = {
> {
> "RING_START",
> - INTEL_GEN_MASK(6, 7),
> + 6, 7,
> 0x38,
> },
> {
> "RING_MI_MODE",
> - INTEL_GEN_MASK(8, BITS_PER_LONG),
> + 8, U8_MAX,
Makes me wonder if we should add VER_MAX. Can be done later if needed.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 0x9c,
> }
> };
> @@ -170,7 +172,7 @@ static int live_forcewake_ops(void *arg)
>
> /* We have to pick carefully to get the exact behaviour we need */
> for (r = registers; r->name; r++)
> - if (r->platforms & INTEL_INFO(gt->i915)->gen_mask)
> + if (IS_GRAPHICS_VER(gt->i915, r->min_graphics_ver, r->max_graphics_ver))
> break;
> if (!r->name) {
> pr_debug("Forcewaked register not known for %s; skipping\n",
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 08/12] drm/i915: finish removal of gen_mask
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 08/12] drm/i915: finish removal " Lucas De Marchi
@ 2021-04-13 9:40 ` Jani Nikula
2021-04-14 11:38 ` Tvrtko Ursulin
1 sibling, 0 replies; 39+ messages in thread
From: Jani Nikula @ 2021-04-13 9:40 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On Mon, 12 Apr 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Now that it's not used anywhere, remove it from struct
> intel_device_info. To allow a period in which code will be converted to
> the new macro, keep IS_GEN_RANGE() around, just redefining it to use
> the new fields. The size advantage from IS_GEN_RANGE() using a mask is
> not that big as it has pretty limited use througout the driver:
>
> text data bss dec hex filename
> 2758497 95965 6496 2860958 2ba79e drivers/gpu/drm/i915/i915.ko.old
> 2758586 95953 6496 2861035 2ba7eb drivers/gpu/drm/i915/i915.ko.new
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 --
> drivers/gpu/drm/i915/i915_drv.h | 13 ++++---------
> drivers/gpu/drm/i915/i915_pci.c | 1 -
> drivers/gpu/drm/i915/intel_device_info.h | 2 --
> 4 files changed, 4 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 305557e1942a..825b45cb3543 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -768,8 +768,6 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
> memcpy(device_info, match_info, sizeof(*device_info));
> RUNTIME_INFO(i915)->device_id = pdev->device;
>
> - BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
> -
> return i915;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cb59eb0f6c5b..b984a340b21f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1241,6 +1241,10 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
> * GRAPHICS_VER(), MEDIA_VER and DISPLAY_VER()
> */
> #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
> +/*
> + * Deprecated: use IS_GRAPHICS_VER()
> + */
Nitpick, I think this should also mention IS_MEDIA_VER() and
DISPLAY_VER() to not have people blindly use IS_GRAPHICS_VER().
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> +#define IS_GEN_RANGE(dev_priv, s, e) IS_GRAPHICS_VER(dev_priv, (s), (e))
>
> #define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics_ver)
> #define IS_GRAPHICS_VER(i915, from, until) \
> @@ -1257,15 +1261,6 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
> #define REVID_FOREVER 0xff
> #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
>
> -#define INTEL_GEN_MASK(s, e) ( \
> - BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
> - BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
> - GENMASK((e) - 1, (s) - 1))
> -
> -/* Returns true if Gen is in inclusive range [Start, End] */
> -#define IS_GEN_RANGE(dev_priv, s, e) \
> - (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
> -
> #define IS_GEN(dev_priv, n) \
> (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
> INTEL_INFO(dev_priv)->gen == (n))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 97ab73276334..3b9cd1af0f28 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -37,7 +37,6 @@
>
> #define PLATFORM(x) .platform = (x)
> #define GEN(x) \
> - .gen_mask = BIT((x) - 1), \
> .gen = (x), \
> .graphics_ver = (x), \
> .media_ver = (x), \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 405883a8cc84..b8f7b996f140 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -160,8 +160,6 @@ enum intel_ppgtt_type {
> func(supports_tv);
>
> struct intel_device_info {
> - u16 gen_mask;
> -
> u8 graphics_ver;
> u8 media_ver;
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 09/12] drm/i915: eliminate remaining uses of intel_device_info->gen
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 09/12] drm/i915: eliminate remaining uses of intel_device_info->gen Lucas De Marchi
@ 2021-04-13 9:43 ` Jani Nikula
0 siblings, 0 replies; 39+ messages in thread
From: Jani Nikula @ 2021-04-13 9:43 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On Mon, 12 Apr 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Replace gen with the new graphics_ver value and use GRAPHICS_VER()
> in those places.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 22 +++++++++----------
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> 3 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 5964e67c7d36..297143511f99 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -274,7 +274,7 @@ struct i915_execbuffer {
> struct drm_mm_node node; /** temporary GTT binding */
> unsigned long vaddr; /** Current kmap address */
> unsigned long page; /** Currently mapped page index */
> - unsigned int gen; /** Cached value of INTEL_GEN */
> + unsigned int graphics_ver; /** Cached value of GRAPHICS_VER */
Is this unsigned int for efficiency or what? *shrug*
> bool use_64bit_reloc : 1;
> bool has_llc : 1;
> bool has_fence : 1;
> @@ -1049,10 +1049,10 @@ static void reloc_cache_init(struct reloc_cache *cache,
> cache->page = -1;
> cache->vaddr = 0;
> /* Must be a variable in the struct to allow GCC to unroll. */
> - cache->gen = INTEL_GEN(i915);
> + cache->graphics_ver = GRAPHICS_VER(i915);
> cache->has_llc = HAS_LLC(i915);
> cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
> - cache->has_fence = cache->gen < 4;
> + cache->has_fence = cache->graphics_ver < 4;
> cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
> cache->node.flags = 0;
> reloc_cache_clear(cache);
> @@ -1402,7 +1402,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
>
> err = eb->engine->emit_bb_start(rq,
> batch->node.start, PAGE_SIZE,
> - cache->gen > 5 ? 0 : I915_DISPATCH_SECURE);
> + cache->graphics_ver > 5 ? 0 : I915_DISPATCH_SECURE);
> if (err)
> goto skip_request;
>
> @@ -1503,14 +1503,14 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb,
> u64 offset,
> u64 target_addr)
> {
> - const unsigned int gen = eb->reloc_cache.gen;
> + const unsigned int ver = eb->reloc_cache.graphics_ver;
Nitpick, I think I'd like to use the more specific name throughout, also
for local variables, i.e. graphics_ver, media_ver, or display_ver.
Does not need to be changed in this patch though.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> unsigned int len;
> u32 *batch;
> u64 addr;
>
> - if (gen >= 8)
> + if (ver >= 8)
> len = offset & 7 ? 8 : 5;
> - else if (gen >= 4)
> + else if (ver >= 4)
> len = 4;
> else
> len = 3;
> @@ -1522,7 +1522,7 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb,
> return false;
>
> addr = gen8_canonical_addr(vma->node.start + offset);
> - if (gen >= 8) {
> + if (ver >= 8) {
> if (offset & 7) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4;
> *batch++ = lower_32_bits(addr);
> @@ -1542,7 +1542,7 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb,
> *batch++ = lower_32_bits(target_addr);
> *batch++ = upper_32_bits(target_addr);
> }
> - } else if (gen >= 6) {
> + } else if (ver >= 6) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4;
> *batch++ = 0;
> *batch++ = addr;
> @@ -1552,12 +1552,12 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb,
> *batch++ = 0;
> *batch++ = vma_phys_addr(vma, offset);
> *batch++ = target_addr;
> - } else if (gen >= 4) {
> + } else if (ver >= 4) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *batch++ = 0;
> *batch++ = addr;
> *batch++ = target_addr;
> - } else if (gen >= 3 &&
> + } else if (ver >= 3 &&
> !(IS_I915G(eb->i915) || IS_I915GM(eb->i915))) {
> *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
> *batch++ = addr;
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 825b45cb3543..e477d278ca73 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -794,7 +794,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> return PTR_ERR(i915);
>
> /* Disable nuclear pageflip by default on pre-ILK */
> - if (!i915->params.nuclear_pageflip && match_info->gen < 5)
> + if (!i915->params.nuclear_pageflip && match_info->graphics_ver < 5)
> i915->drm.driver_features &= ~DRIVER_ATOMIC;
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index de02207f6ec6..b58bc7bff65e 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -95,7 +95,7 @@ static const char *iommu_name(void)
> void intel_device_info_print_static(const struct intel_device_info *info,
> struct drm_printer *p)
> {
> - drm_printf(p, "gen: %d\n", info->gen);
> + drm_printf(p, "graphics_ver: %u\n", info->graphics_ver);
> drm_printf(p, "gt: %d\n", info->gt);
> drm_printf(p, "iommu: %s\n", iommu_name());
> drm_printf(p, "memory-regions: %x\n", info->memory_regions);
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 10/12] drm/i915: finish removal of gen from intel_device_info
2021-04-13 5:10 ` [Intel-gfx] [PATCH v2 10/12] drm/i915: finish removal of gen from intel_device_info Lucas De Marchi
@ 2021-04-13 9:45 ` Jani Nikula
0 siblings, 0 replies; 39+ messages in thread
From: Jani Nikula @ 2021-04-13 9:45 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On Mon, 12 Apr 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Now that it's not being used anymore, finish its removal. Like for
> gen_mask, we replace INTEL_GEN() and IS_GEN() macros to use the new
> field.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 10 +++++-----
> drivers/gpu/drm/i915/i915_pci.c | 1 -
> drivers/gpu/drm/i915/intel_device_info.h | 1 -
> drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
> 4 files changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b984a340b21f..549ce0ce5bde 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1240,11 +1240,15 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
> * Deprecated: this will be replaced by individual IP checks:
> * GRAPHICS_VER(), MEDIA_VER and DISPLAY_VER()
> */
> -#define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
> +#define INTEL_GEN(dev_priv) GRAPHICS_VER(dev_priv)
> /*
> * Deprecated: use IS_GRAPHICS_VER()
> */
> #define IS_GEN_RANGE(dev_priv, s, e) IS_GRAPHICS_VER(dev_priv, (s), (e))
> +/*
> + * Deprecated: use GRAPHICS_VER()
> + */
Nitpick, also mention media and display variants here.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> +#define IS_GEN(dev_priv, n) (GRAPHICS_VER(dev_priv) == (n))
>
> #define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics_ver)
> #define IS_GRAPHICS_VER(i915, from, until) \
> @@ -1261,10 +1265,6 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
> #define REVID_FOREVER 0xff
> #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
>
> -#define IS_GEN(dev_priv, n) \
> - (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
> - INTEL_INFO(dev_priv)->gen == (n))
> -
> #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
>
> /*
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 3b9cd1af0f28..1453c1436f31 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -37,7 +37,6 @@
>
> #define PLATFORM(x) .platform = (x)
> #define GEN(x) \
> - .gen = (x), \
> .graphics_ver = (x), \
> .media_ver = (x), \
> .display.ver = (x)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index b8f7b996f140..8ab4fa6c7fdd 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -163,7 +163,6 @@ struct intel_device_info {
> u8 graphics_ver;
> u8 media_ver;
>
> - u8 gen;
> u8 gt; /* GT number, 0 if undefined */
> intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
>
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index 0188f877cab2..2ffc763fe90d 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -162,7 +162,7 @@ struct drm_i915_private *mock_gem_device(void)
> /* Using the global GTT may ask questions about KMS users, so prepare */
> drm_mode_config_init(&i915->drm);
>
> - mkwrite_device_info(i915)->gen = -1;
> + mkwrite_device_info(i915)->graphics_ver = -1;
>
> mkwrite_device_info(i915)->page_sizes =
> I915_GTT_PAGE_SIZE_4K |
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 11/12] drm/i915: add media and display versions to device_info print
2021-04-13 5:10 ` [Intel-gfx] [PATCH v2 11/12] drm/i915: add media and display versions to device_info print Lucas De Marchi
@ 2021-04-13 9:46 ` Jani Nikula
0 siblings, 0 replies; 39+ messages in thread
From: Jani Nikula @ 2021-04-13 9:46 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On Mon, 12 Apr 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Since we are now converting from a single gen version to graphics_ver,
> media_ver and display_ver, add the last 2 when printing the device info.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index b58bc7bff65e..6a351a709417 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -96,6 +96,8 @@ void intel_device_info_print_static(const struct intel_device_info *info,
> struct drm_printer *p)
> {
> drm_printf(p, "graphics_ver: %u\n", info->graphics_ver);
> + drm_printf(p, "media_ver: %u\n", info->media_ver);
> + drm_printf(p, "display_ver: %u\n", info->display.ver);
> drm_printf(p, "gt: %d\n", info->gt);
> drm_printf(p, "iommu: %s\n", iommu_name());
> drm_printf(p, "memory-regions: %x\n", info->memory_regions);
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 12/12] drm/i915: split dgfx features from gen 12
2021-04-13 5:10 ` [Intel-gfx] [PATCH v2 12/12] drm/i915: split dgfx features from gen 12 Lucas De Marchi
@ 2021-04-13 9:47 ` Jani Nikula
0 siblings, 0 replies; 39+ messages in thread
From: Jani Nikula @ 2021-04-13 9:47 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On Mon, 12 Apr 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Make them independent so we can use DGFX_FEATURES more generically.
> For future platforms that do not use the GEN nomenclature we will define
> graphics, media and display separately, so we avoid setting graphics_ver
> with the GEN() macro.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_pci.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 1453c1436f31..44e7b94db63d 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -907,8 +907,7 @@ static const struct intel_device_info rkl_info = {
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
> };
>
> -#define GEN12_DGFX_FEATURES \
> - GEN12_FEATURES, \
> +#define DGFX_FEATURES \
> .memory_regions = REGION_SMEM | REGION_LMEM, \
> .has_master_unit_irq = 1, \
> .has_llc = 0, \
> @@ -916,7 +915,8 @@ static const struct intel_device_info rkl_info = {
> .is_dgfx = 1
>
> static const struct intel_device_info dg1_info __maybe_unused = {
> - GEN12_DGFX_FEATURES,
> + GEN12_FEATURES,
> + DGFX_FEATURES,
> PLATFORM(INTEL_DG1),
> .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> .require_force_probe = 1,
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
` (16 preceding siblings ...)
2021-04-13 7:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2021-04-13 10:03 ` Jani Nikula
2021-04-14 8:08 ` Jani Nikula
17 siblings, 1 reply; 39+ messages in thread
From: Jani Nikula @ 2021-04-13 10:03 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On Mon, 12 Apr 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Like was done for the display part that parted ways with INTEL_GEN(),
> replacing with DISPLAY_VER(), do a similar conversion for the rest of
> the driver.
>
> v1.1: Remove .ko that was incorrectly added as part of patch 11, making it
> very big and not going through the mailing list. Sorry for those in CC
> who received it.
>
> v2:
> - Add "drm/i915/display: rename display version macros" to rename
> macro and repurpose it: s/IS_DISPLAY_RANGE/IS_DISPLAY_VER/ and convert
> the current users of IS_DISPLAY_VER to use direct comparison
> - Group display patches to easily apply independently
I like the direction here. Even as the version checks diversify, we
manage to simplify and reduce the macros.
I think we're going to have to queueu this via a topic branch, and merge
that to both drm-intel-next and drm-intel-gt-next. The next time the
branches can sync up is just too far away at this point, and the
conflicts may be really nasty to solve later.
That does mean having to solve the conflict with 70bfb30743d5
("drm/i915/display: Eliminate IS_GEN9_{BC,LP}") which is in din but not
dign. The topic branch would be based on:
$ git merge-base drm-intel/drm-intel-next drm-intel/drm-intel-gt-next
9c0fed84d5750e1eea6c664e073ffa2534a17743
There are two (crappy?) ideas to make that easier. 1) revert
70bfb30743d5 from din and add it to the topic branch instead, 2) don't
revert it but cherry-pick it to the topic branch also.
Cc: Joonas and Daniel for their input on this as well.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver
2021-04-13 10:03 ` [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Jani Nikula
@ 2021-04-14 8:08 ` Jani Nikula
2021-04-14 10:06 ` Jani Nikula
0 siblings, 1 reply; 39+ messages in thread
From: Jani Nikula @ 2021-04-14 8:08 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On Tue, 13 Apr 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Mon, 12 Apr 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> Like was done for the display part that parted ways with INTEL_GEN(),
>> replacing with DISPLAY_VER(), do a similar conversion for the rest of
>> the driver.
>>
>> v1.1: Remove .ko that was incorrectly added as part of patch 11, making it
>> very big and not going through the mailing list. Sorry for those in CC
>> who received it.
>>
>> v2:
>> - Add "drm/i915/display: rename display version macros" to rename
>> macro and repurpose it: s/IS_DISPLAY_RANGE/IS_DISPLAY_VER/ and convert
>> the current users of IS_DISPLAY_VER to use direct comparison
>> - Group display patches to easily apply independently
>
> I like the direction here. Even as the version checks diversify, we
> manage to simplify and reduce the macros.
>
> I think we're going to have to queueu this via a topic branch, and merge
> that to both drm-intel-next and drm-intel-gt-next. The next time the
> branches can sync up is just too far away at this point, and the
> conflicts may be really nasty to solve later.
>
> That does mean having to solve the conflict with 70bfb30743d5
> ("drm/i915/display: Eliminate IS_GEN9_{BC,LP}") which is in din but not
> dign. The topic branch would be based on:
>
> $ git merge-base drm-intel/drm-intel-next drm-intel/drm-intel-gt-next
> 9c0fed84d5750e1eea6c664e073ffa2534a17743
>
> There are two (crappy?) ideas to make that easier. 1) revert
> 70bfb30743d5 from din and add it to the topic branch instead, 2) don't
> revert it but cherry-pick it to the topic branch also.
>
> Cc: Joonas and Daniel for their input on this as well.
I've created the topic branch topic/intel-gen-to-ver where the series
should be applied.
However, for the reasons above, it does not apply as-is, and the merge
will conflict slightly.
Also, I think Ville's fixes [1] should land on the topic branch *first*
because they need to be propagated to drm-intel-next-fixes.
BR,
Jani.
[1] https://lore.kernel.org/intel-gfx/20210412054607.18133-1-ville.syrjala@linux.intel.com/
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver
2021-04-14 8:08 ` Jani Nikula
@ 2021-04-14 10:06 ` Jani Nikula
2021-04-14 11:17 ` Joonas Lahtinen
0 siblings, 1 reply; 39+ messages in thread
From: Jani Nikula @ 2021-04-14 10:06 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On Wed, 14 Apr 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Tue, 13 Apr 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>> On Mon, 12 Apr 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>>> Like was done for the display part that parted ways with INTEL_GEN(),
>>> replacing with DISPLAY_VER(), do a similar conversion for the rest of
>>> the driver.
>>>
>>> v1.1: Remove .ko that was incorrectly added as part of patch 11, making it
>>> very big and not going through the mailing list. Sorry for those in CC
>>> who received it.
>>>
>>> v2:
>>> - Add "drm/i915/display: rename display version macros" to rename
>>> macro and repurpose it: s/IS_DISPLAY_RANGE/IS_DISPLAY_VER/ and convert
>>> the current users of IS_DISPLAY_VER to use direct comparison
>>> - Group display patches to easily apply independently
>>
>> I like the direction here. Even as the version checks diversify, we
>> manage to simplify and reduce the macros.
>>
>> I think we're going to have to queueu this via a topic branch, and merge
>> that to both drm-intel-next and drm-intel-gt-next. The next time the
>> branches can sync up is just too far away at this point, and the
>> conflicts may be really nasty to solve later.
>>
>> That does mean having to solve the conflict with 70bfb30743d5
>> ("drm/i915/display: Eliminate IS_GEN9_{BC,LP}") which is in din but not
>> dign. The topic branch would be based on:
>>
>> $ git merge-base drm-intel/drm-intel-next drm-intel/drm-intel-gt-next
>> 9c0fed84d5750e1eea6c664e073ffa2534a17743
>>
>> There are two (crappy?) ideas to make that easier. 1) revert
>> 70bfb30743d5 from din and add it to the topic branch instead, 2) don't
>> revert it but cherry-pick it to the topic branch also.
>>
>> Cc: Joonas and Daniel for their input on this as well.
>
> I've created the topic branch topic/intel-gen-to-ver where the series
> should be applied.
>
> However, for the reasons above, it does not apply as-is, and the merge
> will conflict slightly.
>
> Also, I think Ville's fixes [1] should land on the topic branch *first*
> because they need to be propagated to drm-intel-next-fixes.
I went ahead and:
* Created the topic branch topic/intel-gen-to-ver with the merge-base
mentioned above.
* Cherry-picked 70bfb30743d5 on the topic branch to avoid major
conflicts, as suggested by Daniel on IRC.
* Reviewed and applied Ville's series [1] on the topic branch.
* Reviewed and applied this series on the topic branch.
- There were a couple of tiny conflicts between patch 3 and Ville's
series, and I fixed the conflicts while applying.
- I also fixed my comment nitpicks while applying.
- I usually refrain from doing any changes while applying, but in this
case I considered the changes very small, and did not want to delay
this any further.
Please chime in now if you have issues with this series! Explicit acks
would be much appreciated; they can be added to the topic merge commit.
I hope to send the pull request and get this merged by Thursday, to
avoid creating more conflicts.
BR,
Jani.
>
>
> [1] https://lore.kernel.org/intel-gfx/20210412054607.18133-1-ville.syrjala@linux.intel.com/
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver
2021-04-14 10:06 ` Jani Nikula
@ 2021-04-14 11:17 ` Joonas Lahtinen
0 siblings, 0 replies; 39+ messages in thread
From: Joonas Lahtinen @ 2021-04-14 11:17 UTC (permalink / raw)
To: Jani Nikula, Lucas De Marchi, intel-gfx
+ Tvrtko
Quoting Jani Nikula (2021-04-14 13:06:42)
> On Wed, 14 Apr 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > On Tue, 13 Apr 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> >> On Mon, 12 Apr 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> >>> Like was done for the display part that parted ways with INTEL_GEN(),
> >>> replacing with DISPLAY_VER(), do a similar conversion for the rest of
> >>> the driver.
> >>>
> >>> v1.1: Remove .ko that was incorrectly added as part of patch 11, making it
> >>> very big and not going through the mailing list. Sorry for those in CC
> >>> who received it.
> >>>
> >>> v2:
> >>> - Add "drm/i915/display: rename display version macros" to rename
> >>> macro and repurpose it: s/IS_DISPLAY_RANGE/IS_DISPLAY_VER/ and convert
> >>> the current users of IS_DISPLAY_VER to use direct comparison
> >>> - Group display patches to easily apply independently
> >>
> >> I like the direction here. Even as the version checks diversify, we
> >> manage to simplify and reduce the macros.
> >>
> >> I think we're going to have to queueu this via a topic branch, and merge
> >> that to both drm-intel-next and drm-intel-gt-next. The next time the
> >> branches can sync up is just too far away at this point, and the
> >> conflicts may be really nasty to solve later.
> >>
> >> That does mean having to solve the conflict with 70bfb30743d5
> >> ("drm/i915/display: Eliminate IS_GEN9_{BC,LP}") which is in din but not
> >> dign. The topic branch would be based on:
> >>
> >> $ git merge-base drm-intel/drm-intel-next drm-intel/drm-intel-gt-next
> >> 9c0fed84d5750e1eea6c664e073ffa2534a17743
> >>
> >> There are two (crappy?) ideas to make that easier. 1) revert
> >> 70bfb30743d5 from din and add it to the topic branch instead, 2) don't
> >> revert it but cherry-pick it to the topic branch also.
> >>
> >> Cc: Joonas and Daniel for their input on this as well.
> >
> > I've created the topic branch topic/intel-gen-to-ver where the series
> > should be applied.
> >
> > However, for the reasons above, it does not apply as-is, and the merge
> > will conflict slightly.
> >
> > Also, I think Ville's fixes [1] should land on the topic branch *first*
> > because they need to be propagated to drm-intel-next-fixes.
>
> I went ahead and:
>
> * Created the topic branch topic/intel-gen-to-ver with the merge-base
> mentioned above.
>
> * Cherry-picked 70bfb30743d5 on the topic branch to avoid major
> conflicts, as suggested by Daniel on IRC.
>
> * Reviewed and applied Ville's series [1] on the topic branch.
>
> * Reviewed and applied this series on the topic branch.
>
> - There were a couple of tiny conflicts between patch 3 and Ville's
> series, and I fixed the conflicts while applying.
>
> - I also fixed my comment nitpicks while applying.
>
> - I usually refrain from doing any changes while applying, but in this
> case I considered the changes very small, and did not want to delay
> this any further.
>
> Please chime in now if you have issues with this series! Explicit acks
> would be much appreciated; they can be added to the topic merge commit.
I think GT_VER() would be preferred over the more ambiguous GRAPHICS_VER()
and would better align with the attempt to consolidate the naming
difference between display and GT.
The GPU as whole is referred to as Intel Graphics, so otherwise will be
easy to draw wrong conclusions for 3rd parties looking at the code.
With GT_VER() or something else more distinctive this is:
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
>
> I hope to send the pull request and get this merged by Thursday, to
> avoid creating more conflicts.
>
>
> BR,
> Jani.
>
> >
> >
> > [1] https://lore.kernel.org/intel-gfx/20210412054607.18133-1-ville.syrjala@linux.intel.com/
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 08/12] drm/i915: finish removal of gen_mask
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 08/12] drm/i915: finish removal " Lucas De Marchi
2021-04-13 9:40 ` Jani Nikula
@ 2021-04-14 11:38 ` Tvrtko Ursulin
2021-04-14 13:13 ` Jani Nikula
2021-04-14 17:41 ` Lucas De Marchi
1 sibling, 2 replies; 39+ messages in thread
From: Tvrtko Ursulin @ 2021-04-14 11:38 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On 13/04/2021 06:09, Lucas De Marchi wrote:
> Now that it's not used anywhere, remove it from struct
> intel_device_info. To allow a period in which code will be converted to
> the new macro, keep IS_GEN_RANGE() around, just redefining it to use
> the new fields. The size advantage from IS_GEN_RANGE() using a mask is
> not that big as it has pretty limited use througout the driver:
>
> text data bss dec hex filename
> 2758497 95965 6496 2860958 2ba79e drivers/gpu/drm/i915/i915.ko.old
> 2758586 95953 6496 2861035 2ba7eb drivers/gpu/drm/i915/i915.ko.new
This delta refers to this patch - I mean this point in the series?
Asking because it may not be 100% representative since some of the
previous patches have already removed some gen mask usages.
While I am here, I am a bit fond of the mask approach and wonder if
using it for all (gt/media/whatelse) new fields would still make sense.
Presence of the range check helpers suggests that it might, but I
haven't looked at how prevalent their usage ends up after the series is
done. So just in principle, I don't see why not still go with masks
since that guarantees elegant check at each range check site. It would
be all hidden in the macro implementation so easy.
Also for historical reference, another reason why I went for masks
everywhere approach is that at some point we had a feature request to
allow compiling out platforms/gens. I *think* that was much easier to do
with masking and in experiments back then I was able for instance to
build just for Gen9+ and drop like 30% of the binary size.
Oh I found the branch now.. The reason for IS_GEN(p, v) was also in that
series. I don't know if I ever RFC-ed or trybotted it.. google suggests
no and I neither can find it in my mailboxes. I could send out the old
patches for reference? But to be honest I have no idea if this feature
request (targeted driver builds) will ever resurface..
Regards,
Tvrtko
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 --
> drivers/gpu/drm/i915/i915_drv.h | 13 ++++---------
> drivers/gpu/drm/i915/i915_pci.c | 1 -
> drivers/gpu/drm/i915/intel_device_info.h | 2 --
> 4 files changed, 4 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 305557e1942a..825b45cb3543 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -768,8 +768,6 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
> memcpy(device_info, match_info, sizeof(*device_info));
> RUNTIME_INFO(i915)->device_id = pdev->device;
>
> - BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
> -
> return i915;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cb59eb0f6c5b..b984a340b21f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1241,6 +1241,10 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
> * GRAPHICS_VER(), MEDIA_VER and DISPLAY_VER()
> */
> #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
> +/*
> + * Deprecated: use IS_GRAPHICS_VER()
> + */
> +#define IS_GEN_RANGE(dev_priv, s, e) IS_GRAPHICS_VER(dev_priv, (s), (e))
>
> #define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics_ver)
> #define IS_GRAPHICS_VER(i915, from, until) \
> @@ -1257,15 +1261,6 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
> #define REVID_FOREVER 0xff
> #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
>
> -#define INTEL_GEN_MASK(s, e) ( \
> - BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
> - BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
> - GENMASK((e) - 1, (s) - 1))
> -
> -/* Returns true if Gen is in inclusive range [Start, End] */
> -#define IS_GEN_RANGE(dev_priv, s, e) \
> - (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
> -
> #define IS_GEN(dev_priv, n) \
> (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
> INTEL_INFO(dev_priv)->gen == (n))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 97ab73276334..3b9cd1af0f28 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -37,7 +37,6 @@
>
> #define PLATFORM(x) .platform = (x)
> #define GEN(x) \
> - .gen_mask = BIT((x) - 1), \
> .gen = (x), \
> .graphics_ver = (x), \
> .media_ver = (x), \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 405883a8cc84..b8f7b996f140 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -160,8 +160,6 @@ enum intel_ppgtt_type {
> func(supports_tv);
>
> struct intel_device_info {
> - u16 gen_mask;
> -
> u8 graphics_ver;
> u8 media_ver;
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 08/12] drm/i915: finish removal of gen_mask
2021-04-14 11:38 ` Tvrtko Ursulin
@ 2021-04-14 13:13 ` Jani Nikula
2021-04-14 13:46 ` Tvrtko Ursulin
2021-04-14 17:41 ` Lucas De Marchi
1 sibling, 1 reply; 39+ messages in thread
From: Jani Nikula @ 2021-04-14 13:13 UTC (permalink / raw)
To: Tvrtko Ursulin, Lucas De Marchi, intel-gfx
On Wed, 14 Apr 2021, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> On 13/04/2021 06:09, Lucas De Marchi wrote:
>> Now that it's not used anywhere, remove it from struct
>> intel_device_info. To allow a period in which code will be converted to
>> the new macro, keep IS_GEN_RANGE() around, just redefining it to use
>> the new fields. The size advantage from IS_GEN_RANGE() using a mask is
>> not that big as it has pretty limited use througout the driver:
>>
>> text data bss dec hex filename
>> 2758497 95965 6496 2860958 2ba79e drivers/gpu/drm/i915/i915.ko.old
>> 2758586 95953 6496 2861035 2ba7eb drivers/gpu/drm/i915/i915.ko.new
>
> This delta refers to this patch - I mean this point in the series?
> Asking because it may not be 100% representative since some of the
> previous patches have already removed some gen mask usages.
>
> While I am here, I am a bit fond of the mask approach and wonder if
> using it for all (gt/media/whatelse) new fields would still make sense.
>
> Presence of the range check helpers suggests that it might, but I
> haven't looked at how prevalent their usage ends up after the series is
> done. So just in principle, I don't see why not still go with masks
> since that guarantees elegant check at each range check site. It would
> be all hidden in the macro implementation so easy.
>
> Also for historical reference, another reason why I went for masks
> everywhere approach is that at some point we had a feature request to
> allow compiling out platforms/gens. I *think* that was much easier to do
> with masking and in experiments back then I was able for instance to
> build just for Gen9+ and drop like 30% of the binary size.
>
> Oh I found the branch now.. The reason for IS_GEN(p, v) was also in that
> series. I don't know if I ever RFC-ed or trybotted it.. google suggests
> no and I neither can find it in my mailboxes. I could send out the old
> patches for reference? But to be honest I have no idea if this feature
> request (targeted driver builds) will ever resurface..
I completely agreed with the direction of using the masks way back when,
especially with the goal of the conditional/targeted compilation.
I think the question now is whether we want to keep maintaining them
just for the sake of the masks. Keeping them means having three masks
instead of one. And we wouldn't be using most of the benefits with them,
we'd mostly just get the downsides.
Having the masks per se is not such a big deal, but they're also not
such a big deal to add back later on if needed. It's the codebase all
over that's the hard part. And arguably it's not getting that much
different with the series at hand; the direct uses of INTEL_GEN() and
DISPLAY_VER() vastly outnumber IS_GEN(), IS_GEN_RANGE() and
IS_DISPLAY_RANGE() which could benefit from the mask.
We'd still be retaining the range macros as IS_GRAPHICS_VER(),
IS_MEDIA_VER() and IS_DISPLAY_VER(), although more for clarity than for
any other reason.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 08/12] drm/i915: finish removal of gen_mask
2021-04-14 13:13 ` Jani Nikula
@ 2021-04-14 13:46 ` Tvrtko Ursulin
2021-04-15 10:22 ` Jani Nikula
0 siblings, 1 reply; 39+ messages in thread
From: Tvrtko Ursulin @ 2021-04-14 13:46 UTC (permalink / raw)
To: Jani Nikula, Lucas De Marchi, intel-gfx
On 14/04/2021 14:13, Jani Nikula wrote:
> On Wed, 14 Apr 2021, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>> On 13/04/2021 06:09, Lucas De Marchi wrote:
>>> Now that it's not used anywhere, remove it from struct
>>> intel_device_info. To allow a period in which code will be converted to
>>> the new macro, keep IS_GEN_RANGE() around, just redefining it to use
>>> the new fields. The size advantage from IS_GEN_RANGE() using a mask is
>>> not that big as it has pretty limited use througout the driver:
>>>
>>> text data bss dec hex filename
>>> 2758497 95965 6496 2860958 2ba79e drivers/gpu/drm/i915/i915.ko.old
>>> 2758586 95953 6496 2861035 2ba7eb drivers/gpu/drm/i915/i915.ko.new
>>
>> This delta refers to this patch - I mean this point in the series?
>> Asking because it may not be 100% representative since some of the
>> previous patches have already removed some gen mask usages.
>>
>> While I am here, I am a bit fond of the mask approach and wonder if
>> using it for all (gt/media/whatelse) new fields would still make sense.
>>
>> Presence of the range check helpers suggests that it might, but I
>> haven't looked at how prevalent their usage ends up after the series is
>> done. So just in principle, I don't see why not still go with masks
>> since that guarantees elegant check at each range check site. It would
>> be all hidden in the macro implementation so easy.
>>
>> Also for historical reference, another reason why I went for masks
>> everywhere approach is that at some point we had a feature request to
>> allow compiling out platforms/gens. I *think* that was much easier to do
>> with masking and in experiments back then I was able for instance to
>> build just for Gen9+ and drop like 30% of the binary size.
>>
>> Oh I found the branch now.. The reason for IS_GEN(p, v) was also in that
>> series. I don't know if I ever RFC-ed or trybotted it.. google suggests
>> no and I neither can find it in my mailboxes. I could send out the old
>> patches for reference? But to be honest I have no idea if this feature
>> request (targeted driver builds) will ever resurface..
>
> I completely agreed with the direction of using the masks way back when,
> especially with the goal of the conditional/targeted compilation.
>
> I think the question now is whether we want to keep maintaining them
> just for the sake of the masks. Keeping them means having three masks
> instead of one. And we wouldn't be using most of the benefits with them,
> we'd mostly just get the downsides.
>
> Having the masks per se is not such a big deal, but they're also not
> such a big deal to add back later on if needed. It's the codebase all
> over that's the hard part. And arguably it's not getting that much
> different with the series at hand; the direct uses of INTEL_GEN() and
> DISPLAY_VER() vastly outnumber IS_GEN(), IS_GEN_RANGE() and
> IS_DISPLAY_RANGE() which could benefit from the mask.
>
> We'd still be retaining the range macros as IS_GRAPHICS_VER(),
> IS_MEDIA_VER() and IS_DISPLAY_VER(), although more for clarity than for
> any other reason.
Adding masks later would not a big deal, but another cycle of changing
"xxx_VER == n" to "IS_xxx_VER(n)" is a churn which could presumably be
avoided.
It is moot yes, but I don't see a clear case for doing the reversal as
part of this series. With a disclaimer that I only glanced over the
commit messages today for the first time.
So I think from me its neither ack or nack, at least since I don't
understand the attractiveness of using the "ver == n" and numerical
range check forms everywhere. As said, if we are churning I'd rather go
the other direction. But that's a soft objection only so feel free to
proceed.
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 08/12] drm/i915: finish removal of gen_mask
2021-04-14 11:38 ` Tvrtko Ursulin
2021-04-14 13:13 ` Jani Nikula
@ 2021-04-14 17:41 ` Lucas De Marchi
1 sibling, 0 replies; 39+ messages in thread
From: Lucas De Marchi @ 2021-04-14 17:41 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
On Wed, Apr 14, 2021 at 12:38:44PM +0100, Tvrtko Ursulin wrote:
>
>On 13/04/2021 06:09, Lucas De Marchi wrote:
>>Now that it's not used anywhere, remove it from struct
>>intel_device_info. To allow a period in which code will be converted to
>>the new macro, keep IS_GEN_RANGE() around, just redefining it to use
>>the new fields. The size advantage from IS_GEN_RANGE() using a mask is
>>not that big as it has pretty limited use througout the driver:
>>
>> text data bss dec hex filename
>>2758497 95965 6496 2860958 2ba79e drivers/gpu/drm/i915/i915.ko.old
>>2758586 95953 6496 2861035 2ba7eb drivers/gpu/drm/i915/i915.ko.new
>
>This delta refers to this patch - I mean this point in the series?
>Asking because it may not be 100% representative since some of the
>previous patches have already removed some gen mask usages.
yes, it doesn't consider the other patches. These numbers are also for
v1, not v2, as I didn't update the commit mesage.
I don't think the numbers will be too different though.
>
>While I am here, I am a bit fond of the mask approach and wonder if
>using it for all (gt/media/whatelse) new fields would still make
>sense.
>
>Presence of the range check helpers suggests that it might, but I
>haven't looked at how prevalent their usage ends up after the series
>is done. So just in principle, I don't see why not still go with masks
>since that guarantees elegant check at each range check site. It would
>be all hidden in the macro implementation so easy.
>
>Also for historical reference, another reason why I went for masks
>everywhere approach is that at some point we had a feature request to
>allow compiling out platforms/gens. I *think* that was much easier to
>do with masking and in experiments back then I was able for instance
>to build just for Gen9+ and drop like 30% of the binary size.
>
>Oh I found the branch now.. The reason for IS_GEN(p, v) was also in
>that series. I don't know if I ever RFC-ed or trybotted it.. google
>suggests no and I neither can find it in my mailboxes. I could send
>out the old patches for reference? But to be honest I have no idea if
>this feature request (targeted driver builds) will ever resurface..
At the time I also liked having the macros. Looking back and checking if
we really took advantage of it, I lean towards a "no". Even when and if
we are interested in compiling out some platforms, I think a better
code split would be deserved rather relying on this.
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v2 08/12] drm/i915: finish removal of gen_mask
2021-04-14 13:46 ` Tvrtko Ursulin
@ 2021-04-15 10:22 ` Jani Nikula
0 siblings, 0 replies; 39+ messages in thread
From: Jani Nikula @ 2021-04-15 10:22 UTC (permalink / raw)
To: Tvrtko Ursulin, Lucas De Marchi, intel-gfx
On Wed, 14 Apr 2021, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> On 14/04/2021 14:13, Jani Nikula wrote:
>> On Wed, 14 Apr 2021, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>>> On 13/04/2021 06:09, Lucas De Marchi wrote:
>>>> Now that it's not used anywhere, remove it from struct
>>>> intel_device_info. To allow a period in which code will be converted to
>>>> the new macro, keep IS_GEN_RANGE() around, just redefining it to use
>>>> the new fields. The size advantage from IS_GEN_RANGE() using a mask is
>>>> not that big as it has pretty limited use througout the driver:
>>>>
>>>> text data bss dec hex filename
>>>> 2758497 95965 6496 2860958 2ba79e drivers/gpu/drm/i915/i915.ko.old
>>>> 2758586 95953 6496 2861035 2ba7eb drivers/gpu/drm/i915/i915.ko.new
>>>
>>> This delta refers to this patch - I mean this point in the series?
>>> Asking because it may not be 100% representative since some of the
>>> previous patches have already removed some gen mask usages.
>>>
>>> While I am here, I am a bit fond of the mask approach and wonder if
>>> using it for all (gt/media/whatelse) new fields would still make sense.
>>>
>>> Presence of the range check helpers suggests that it might, but I
>>> haven't looked at how prevalent their usage ends up after the series is
>>> done. So just in principle, I don't see why not still go with masks
>>> since that guarantees elegant check at each range check site. It would
>>> be all hidden in the macro implementation so easy.
>>>
>>> Also for historical reference, another reason why I went for masks
>>> everywhere approach is that at some point we had a feature request to
>>> allow compiling out platforms/gens. I *think* that was much easier to do
>>> with masking and in experiments back then I was able for instance to
>>> build just for Gen9+ and drop like 30% of the binary size.
>>>
>>> Oh I found the branch now.. The reason for IS_GEN(p, v) was also in that
>>> series. I don't know if I ever RFC-ed or trybotted it.. google suggests
>>> no and I neither can find it in my mailboxes. I could send out the old
>>> patches for reference? But to be honest I have no idea if this feature
>>> request (targeted driver builds) will ever resurface..
>>
>> I completely agreed with the direction of using the masks way back when,
>> especially with the goal of the conditional/targeted compilation.
>>
>> I think the question now is whether we want to keep maintaining them
>> just for the sake of the masks. Keeping them means having three masks
>> instead of one. And we wouldn't be using most of the benefits with them,
>> we'd mostly just get the downsides.
>>
>> Having the masks per se is not such a big deal, but they're also not
>> such a big deal to add back later on if needed. It's the codebase all
>> over that's the hard part. And arguably it's not getting that much
>> different with the series at hand; the direct uses of INTEL_GEN() and
>> DISPLAY_VER() vastly outnumber IS_GEN(), IS_GEN_RANGE() and
>> IS_DISPLAY_RANGE() which could benefit from the mask.
>>
>> We'd still be retaining the range macros as IS_GRAPHICS_VER(),
>> IS_MEDIA_VER() and IS_DISPLAY_VER(), although more for clarity than for
>> any other reason.
>
> Adding masks later would not a big deal, but another cycle of changing
> "xxx_VER == n" to "IS_xxx_VER(n)" is a churn which could presumably be
> avoided.
Direct xxx_VER <, >, <= and >= already exist all over the place, and
their numbers trump the == cases. Seems confusing to treat ==
differently.
> It is moot yes, but I don't see a clear case for doing the reversal as
> part of this series. With a disclaimer that I only glanced over the
> commit messages today for the first time.
So I wanted to keep using the range check macros for a couple of
reasons. Having (VER >= x && VER <= y) gets long, it needs braces, and
we use a bunch of negation !(VER >= x && VER <= y) vs. VER < x || VER >
y. !IS_GEN_RANGE() has more clarity.
Now, adding IS_GRAPHICS_VER_RANGE() gets long. Dropping the VER for
IS_GRAPHICS_RANGE() gets confusing ("what graphics range?"). Now, if we
use == for specific version check, we can repurpose IS_GRAPHICS_VER() to
do the ranges.
> So I think from me its neither ack or nack, at least since I don't
> understand the attractiveness of using the "ver == n" and numerical
> range check forms everywhere. As said, if we are churning I'd rather go
> the other direction. But that's a soft objection only so feel free to
> proceed.
Thanks, noted. However, unless stronger objections arise, I think we're
going to go with the patches at hand.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2021-04-15 10:23 UTC | newest]
Thread overview: 39+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-13 5:09 [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Lucas De Marchi
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 01/12] drm/i915/display: use DISPLAY_VER() on remaining users Lucas De Marchi
2021-04-13 9:24 ` Jani Nikula
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 02/12] drm/i915: rename display.version to display.ver Lucas De Marchi
2021-04-13 9:25 ` Jani Nikula
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 03/12] drm/i915/display: rename display version macros Lucas De Marchi
2021-04-13 9:35 ` Jani Nikula
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 04/12] drm/i915: add macros for graphics and media versions Lucas De Marchi
2021-04-13 9:33 ` Jani Nikula
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 05/12] drm/i915/gt: replace gen use in intel_engine_cs Lucas De Marchi
2021-04-13 9:36 ` Jani Nikula
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 06/12] drm/i915/selftests: replace unused mask with simple version Lucas De Marchi
2021-04-13 9:36 ` Jani Nikula
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 07/12] drm/i915/selftests: eliminate use of gen_mask Lucas De Marchi
2021-04-13 9:38 ` Jani Nikula
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 08/12] drm/i915: finish removal " Lucas De Marchi
2021-04-13 9:40 ` Jani Nikula
2021-04-14 11:38 ` Tvrtko Ursulin
2021-04-14 13:13 ` Jani Nikula
2021-04-14 13:46 ` Tvrtko Ursulin
2021-04-15 10:22 ` Jani Nikula
2021-04-14 17:41 ` Lucas De Marchi
2021-04-13 5:09 ` [Intel-gfx] [PATCH v2 09/12] drm/i915: eliminate remaining uses of intel_device_info->gen Lucas De Marchi
2021-04-13 9:43 ` Jani Nikula
2021-04-13 5:10 ` [Intel-gfx] [PATCH v2 10/12] drm/i915: finish removal of gen from intel_device_info Lucas De Marchi
2021-04-13 9:45 ` Jani Nikula
2021-04-13 5:10 ` [Intel-gfx] [PATCH v2 11/12] drm/i915: add media and display versions to device_info print Lucas De Marchi
2021-04-13 9:46 ` Jani Nikula
2021-04-13 5:10 ` [Intel-gfx] [PATCH v2 12/12] drm/i915: split dgfx features from gen 12 Lucas De Marchi
2021-04-13 9:47 ` Jani Nikula
2021-04-13 5:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Extend GEN renames to the rest of the driver (rev3) Patchwork
2021-04-13 5:45 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-04-13 5:48 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-04-13 6:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-04-13 7:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-04-13 10:03 ` [Intel-gfx] [PATCH v2 00/12] drm/i915: Extend GEN renames to the rest of the driver Jani Nikula
2021-04-14 8:08 ` Jani Nikula
2021-04-14 10:06 ` Jani Nikula
2021-04-14 11:17 ` Joonas Lahtinen
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