* [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables
@ 2021-04-14 15:51 Imre Deak
2021-04-14 15:51 ` [Intel-gfx] [PATCH 01/11] drm/i915: Pass intel_framebuffer instad of drm_framebuffer to intel_fill_fb_info() Imre Deak
` (14 more replies)
0 siblings, 15 replies; 24+ messages in thread
From: Imre Deak @ 2021-04-14 15:51 UTC (permalink / raw)
To: intel-gfx
Alder Lake-P adds a new Display Page Table hardware structure, mapping
tiled framebuffer pages to the display engine, reducing the address
space required in GGTT for these framebuffers.
This patchset adds support for this taking a minimum set of dependency
patches from the ADL_P enabling patchset at
https://patchwork.freedesktop.org/series/87897/
Clinton Taylor (2):
drm/i915/adl_p: Add PCI Devices IDs
drm/i915/adl_p: ADL_P device info enabling
Imre Deak (4):
drm/i915: Pass intel_framebuffer instad of drm_framebuffer to
intel_fill_fb_info()
drm/i915/adl_p: Disable support for 90/270 FB rotation
drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs
drm/i915/adl_p: Enable remapping to pad DPT FB strides to POT
José Roberto de Souza (2):
drm/i915/xelpd: Fallback to plane stride limitations when using DPT
drm/i915/adl_p: Add stride restriction when using DPT
Juha-Pekka Heikkilä (1):
drm/i915/xelpd: Support 128k plane stride
Matt Roper (1):
drm/i915/xelpd: add XE_LPD display characteristics
Ville Syrjälä (1):
drm/i915/xelpd: First stab at DPT support
arch/x86/kernel/early-quirks.c | 1 +
.../gpu/drm/i915/display/intel_atomic_plane.c | 7 +-
drivers/gpu/drm/i915/display/intel_display.c | 381 ++++++++++++++++--
drivers/gpu/drm/i915/display/intel_display.h | 1 +
.../drm/i915/display/intel_display_types.h | 25 +-
drivers/gpu/drm/i915/display/intel_fb.c | 92 +++--
drivers/gpu/drm/i915/display/intel_fb.h | 5 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 6 +-
.../drm/i915/display/skl_universal_plane.c | 68 +++-
drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 7 +
drivers/gpu/drm/i915/gt/intel_ggtt.c | 7 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 5 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 22 +
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
include/drm/i915_pciids.h | 21 +
18 files changed, 567 insertions(+), 86 deletions(-)
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 01/11] drm/i915: Pass intel_framebuffer instad of drm_framebuffer to intel_fill_fb_info()
2021-04-14 15:51 [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
@ 2021-04-14 15:51 ` Imre Deak
2021-04-14 15:51 ` [Intel-gfx] [PATCH 02/11] drm/i915/xelpd: add XE_LPD display characteristics Imre Deak
` (13 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Imre Deak @ 2021-04-14 15:51 UTC (permalink / raw)
To: intel-gfx
Make one step to pass intel_framebuffer to all intel_fb functions.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_fb.c | 63 ++++++++++----------
drivers/gpu/drm/i915/display/intel_fb.h | 3 +-
3 files changed, 34 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9c13d0ac022bc..dd92c97eb8ca0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11255,7 +11255,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
fb->obj[i] = &obj->base;
}
- ret = intel_fill_fb_info(dev_priv, fb);
+ ret = intel_fill_fb_info(dev_priv, intel_fb);
if (ret)
goto err;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 0ec9ad7220a14..1b690b21310de 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -171,17 +171,17 @@ void intel_fb_plane_get_subsampling(int *hsub, int *vsub,
*vsub = 32;
}
-static void intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
+static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_plane, int *w, int *h)
{
- int main_plane = is_ccs_plane(fb, color_plane) ?
- skl_ccs_to_main_plane(fb, color_plane) : 0;
+ int main_plane = is_ccs_plane(&fb->base, color_plane) ?
+ skl_ccs_to_main_plane(&fb->base, color_plane) : 0;
int main_hsub, main_vsub;
int hsub, vsub;
- intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane);
- intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
- *w = fb->width / main_hsub / hsub;
- *h = fb->height / main_vsub / vsub;
+ intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, &fb->base, main_plane);
+ intel_fb_plane_get_subsampling(&hsub, &vsub, &fb->base, color_plane);
+ *w = fb->base.width / main_hsub / hsub;
+ *h = fb->base.height / main_vsub / vsub;
}
static u32 intel_adjust_tile_offset(int *x, int *y,
@@ -743,19 +743,18 @@ static void intel_fb_view_init(struct intel_fb_view *view, enum i915_ggtt_view_t
view->gtt.type = view_type;
}
-int intel_fill_fb_info(struct drm_i915_private *i915, struct drm_framebuffer *fb)
+int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb)
{
- struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
- struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+ struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base);
u32 gtt_offset_rotated = 0;
u32 gtt_offset_remapped = 0;
unsigned int max_size = 0;
- int i, num_planes = fb->format->num_planes;
+ int i, num_planes = fb->base.format->num_planes;
unsigned int tile_size = intel_tile_size(i915);
- intel_fb_view_init(&intel_fb->normal_view, I915_GGTT_VIEW_NORMAL);
- intel_fb_view_init(&intel_fb->rotated_view, I915_GGTT_VIEW_ROTATED);
- intel_fb_view_init(&intel_fb->remapped_view, I915_GGTT_VIEW_REMAPPED);
+ intel_fb_view_init(&fb->normal_view, I915_GGTT_VIEW_NORMAL);
+ intel_fb_view_init(&fb->rotated_view, I915_GGTT_VIEW_ROTATED);
+ intel_fb_view_init(&fb->remapped_view, I915_GGTT_VIEW_REMAPPED);
for (i = 0; i < num_planes; i++) {
struct fb_plane_view_dims view_dims;
@@ -770,45 +769,45 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct drm_framebuffer *fb
* is consumed by the driver and not passed to DE. Skip the
* arithmetic related to alignment and offset calculation.
*/
- if (is_gen12_ccs_cc_plane(fb, i)) {
- if (IS_ALIGNED(fb->offsets[i], PAGE_SIZE))
+ if (is_gen12_ccs_cc_plane(&fb->base, i)) {
+ if (IS_ALIGNED(fb->base.offsets[i], PAGE_SIZE))
continue;
else
return -EINVAL;
}
- cpp = fb->format->cpp[i];
- intel_fb_plane_dims(&width, &height, fb, i);
+ cpp = fb->base.format->cpp[i];
+ intel_fb_plane_dims(fb, i, &width, &height);
- ret = convert_plane_offset_to_xy(intel_fb, i, width, &x, &y);
+ ret = convert_plane_offset_to_xy(fb, i, width, &x, &y);
if (ret)
return ret;
- init_plane_view_dims(intel_fb, i, width, height, &view_dims);
+ init_plane_view_dims(fb, i, width, height, &view_dims);
/*
* First pixel of the framebuffer from
* the start of the normal gtt mapping.
*/
- intel_fb->normal_view.color_plane[i].x = x;
- intel_fb->normal_view.color_plane[i].y = y;
- intel_fb->normal_view.color_plane[i].stride = intel_fb->base.pitches[i];
+ fb->normal_view.color_plane[i].x = x;
+ fb->normal_view.color_plane[i].y = y;
+ fb->normal_view.color_plane[i].stride = fb->base.pitches[i];
- offset = calc_plane_aligned_offset(intel_fb, i, &x, &y);
+ offset = calc_plane_aligned_offset(fb, i, &x, &y);
/* Y or Yf modifiers required for 90/270 rotation */
- if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
- fb->modifier == I915_FORMAT_MOD_Yf_TILED)
- gtt_offset_rotated += calc_plane_remap_info(intel_fb, i, &view_dims,
+ if (fb->base.modifier == I915_FORMAT_MOD_Y_TILED ||
+ fb->base.modifier == I915_FORMAT_MOD_Yf_TILED)
+ gtt_offset_rotated += calc_plane_remap_info(fb, i, &view_dims,
offset, gtt_offset_rotated, x, y,
- &intel_fb->rotated_view);
+ &fb->rotated_view);
- if (intel_fb_needs_pot_stride_remap(intel_fb))
- gtt_offset_remapped += calc_plane_remap_info(intel_fb, i, &view_dims,
+ if (intel_fb_needs_pot_stride_remap(fb))
+ gtt_offset_remapped += calc_plane_remap_info(fb, i, &view_dims,
offset, gtt_offset_remapped, x, y,
- &intel_fb->remapped_view);
+ &fb->remapped_view);
- size = calc_plane_normal_size(intel_fb, i, &view_dims, x, y);
+ size = calc_plane_normal_size(fb, i, &view_dims, x, y);
/* how many tiles in total needed in the bo */
max_size = max(max_size, offset + size);
}
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index 6acf792a8c44a..e0953d8855b6b 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -46,7 +46,8 @@ u32 intel_plane_compute_aligned_offset(int *x, int *y,
const struct intel_plane_state *state,
int color_plane);
-int intel_fill_fb_info(struct drm_i915_private *i915, struct drm_framebuffer *fb);
+
+int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb);
void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation,
struct intel_fb_view *view);
int intel_plane_compute_gtt(struct intel_plane_state *plane_state);
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 02/11] drm/i915/xelpd: add XE_LPD display characteristics
2021-04-14 15:51 [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
2021-04-14 15:51 ` [Intel-gfx] [PATCH 01/11] drm/i915: Pass intel_framebuffer instad of drm_framebuffer to intel_fill_fb_info() Imre Deak
@ 2021-04-14 15:51 ` Imre Deak
2021-05-05 23:55 ` Souza, Jose
2021-04-14 15:52 ` [Intel-gfx] [PATCH 03/11] drm/i915/adl_p: Add PCI Devices IDs Imre Deak
` (12 subsequent siblings)
14 siblings, 1 reply; 24+ messages in thread
From: Imre Deak @ 2021-04-14 15:51 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
Let's start preparing for upcoming platforms that will use an XE_LPD
design.
v2:
- Use the now-preferred "XE_LPD" term to refer to this design
- Utilize DISPLAY_VER() rather than a feature flag
- Drop unused mbus_size field (Lucas)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 44e7b94db63dc..40b58a6dc3193 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -939,6 +939,16 @@ static const struct intel_device_info adl_s_info = {
.dma_mask_size = 46,
};
+#define XE_LPD_FEATURES \
+ .display.ver = 13, \
+ .display.has_psr_hw_tracking = 0, \
+ .abox_mask = GENMASK(1, 0), \
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
+ .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
+ .ddb_size = 4096, \
+ .num_supported_dbuf_slices = 4
+
#undef GEN
#undef PLATFORM
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 03/11] drm/i915/adl_p: Add PCI Devices IDs
2021-04-14 15:51 [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
2021-04-14 15:51 ` [Intel-gfx] [PATCH 01/11] drm/i915: Pass intel_framebuffer instad of drm_framebuffer to intel_fill_fb_info() Imre Deak
2021-04-14 15:51 ` [Intel-gfx] [PATCH 02/11] drm/i915/xelpd: add XE_LPD display characteristics Imre Deak
@ 2021-04-14 15:52 ` Imre Deak
2021-04-14 15:52 ` [Intel-gfx] [PATCH 04/11] drm/i915/adl_p: ADL_P device info enabling Imre Deak
` (11 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Imre Deak @ 2021-04-14 15:52 UTC (permalink / raw)
To: intel-gfx
From: Clinton Taylor <Clinton.A.Taylor@intel.com>
Add 18 known PCI device IDs
Bspec: 55376
Cc: Caz Yokoyama <caz.yokoyama@intel.com>
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
include/drm/i915_pciids.h | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index ebd0dd1c35b33..2448be8c72f89 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -645,4 +645,25 @@
INTEL_VGA_DEVICE(0x4692, info), \
INTEL_VGA_DEVICE(0x4693, info)
+/* ADL-P */
+#define INTEL_ADLP_IDS(info) \
+ INTEL_VGA_DEVICE(0x46A0, info), \
+ INTEL_VGA_DEVICE(0x46A1, info), \
+ INTEL_VGA_DEVICE(0x46A2, info), \
+ INTEL_VGA_DEVICE(0x46A3, info), \
+ INTEL_VGA_DEVICE(0x46A6, info), \
+ INTEL_VGA_DEVICE(0x46A8, info), \
+ INTEL_VGA_DEVICE(0x46AA, info), \
+ INTEL_VGA_DEVICE(0x462A, info), \
+ INTEL_VGA_DEVICE(0x4626, info), \
+ INTEL_VGA_DEVICE(0x4628, info), \
+ INTEL_VGA_DEVICE(0x46B0, info), \
+ INTEL_VGA_DEVICE(0x46B1, info), \
+ INTEL_VGA_DEVICE(0x46B2, info), \
+ INTEL_VGA_DEVICE(0x46B3, info), \
+ INTEL_VGA_DEVICE(0x46C0, info), \
+ INTEL_VGA_DEVICE(0x46C1, info), \
+ INTEL_VGA_DEVICE(0x46C2, info), \
+ INTEL_VGA_DEVICE(0x46C3, info)
+
#endif /* _I915_PCIIDS_H */
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 04/11] drm/i915/adl_p: ADL_P device info enabling
2021-04-14 15:51 [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (2 preceding siblings ...)
2021-04-14 15:52 ` [Intel-gfx] [PATCH 03/11] drm/i915/adl_p: Add PCI Devices IDs Imre Deak
@ 2021-04-14 15:52 ` Imre Deak
2021-05-05 23:54 ` Souza, Jose
2021-04-14 15:52 ` [Intel-gfx] [PATCH 05/11] drm/i915/xelpd: First stab at DPT support Imre Deak
` (10 subsequent siblings)
14 siblings, 1 reply; 24+ messages in thread
From: Imre Deak @ 2021-04-14 15:52 UTC (permalink / raw)
To: intel-gfx
From: Clinton Taylor <Clinton.A.Taylor@intel.com>
Add ADL-P to the device_info table and support MACROS.
Bspec: 49185, 55372, 55373
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
5 files changed, 16 insertions(+)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 6edd1e2ee8afa..b553ffe9b9851 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -552,6 +552,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
INTEL_TGL_12_IDS(&gen11_early_ops),
INTEL_RKL_IDS(&gen11_early_ops),
INTEL_ADLS_IDS(&gen11_early_ops),
+ INTEL_ADLP_IDS(&gen11_early_ops),
};
struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e20294e9227a4..e5513e19beb5c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1392,6 +1392,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
+#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 40b58a6dc3193..2384198e41f85 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -949,6 +949,17 @@ static const struct intel_device_info adl_s_info = {
.ddb_size = 4096, \
.num_supported_dbuf_slices = 4
+static const struct intel_device_info adl_p_info = {
+ GEN12_FEATURES,
+ XE_LPD_FEATURES,
+ PLATFORM(INTEL_ALDERLAKE_P),
+ .require_force_probe = 1,
+ .platform_engine_mask =
+ BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+ .ppgtt_size = 48,
+ .dma_mask_size = 39,
+};
+
#undef GEN
#undef PLATFORM
@@ -1026,6 +1037,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_TGL_12_IDS(&tgl_info),
INTEL_RKL_IDS(&rkl_info),
INTEL_ADLS_IDS(&adl_s_info),
+ INTEL_ADLP_IDS(&adl_p_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 6a351a7094174..3b975ce1ff591 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -67,6 +67,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(ROCKETLAKE),
PLATFORM_NAME(DG1),
PLATFORM_NAME(ALDERLAKE_S),
+ PLATFORM_NAME(ALDERLAKE_P),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 8ab4fa6c7fdd7..edf68244be2bc 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -87,6 +87,7 @@ enum intel_platform {
INTEL_ROCKETLAKE,
INTEL_DG1,
INTEL_ALDERLAKE_S,
+ INTEL_ALDERLAKE_P,
INTEL_MAX_PLATFORMS
};
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 05/11] drm/i915/xelpd: First stab at DPT support
2021-04-14 15:51 [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (3 preceding siblings ...)
2021-04-14 15:52 ` [Intel-gfx] [PATCH 04/11] drm/i915/adl_p: ADL_P device info enabling Imre Deak
@ 2021-04-14 15:52 ` Imre Deak
2021-04-14 15:52 ` [Intel-gfx] [PATCH 06/11] drm/i915/xelpd: Fallback to plane stride limitations when using DPT Imre Deak
` (9 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Imre Deak @ 2021-04-14 15:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Wilson Chris P, Auld Matthew, Bommu Krishnaiah
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add support for DPT (display page table). DPT is a
slightly peculiar two level page table scheme used for
tiled scanout buffers (linear uses direct ggtt mapping
still). The plane surface address will point at a page
in the DPT which holds the PTEs for 512 actual pages.
Thus we require 1/512 of the ggttt address space
compared to a direct ggtt mapping.
We create a new DPT address space for each framebuffer and
track two vmas (one for the DPT, another for the ggtt).
TODO:
- Is the i915_address_space approaach sane?
- Maybe don't map the whole DPT to write the PTEs?
- Deal with remapping/rotation? Need to create a
separate DPT for each remapped/rotated plane I
guess. Or else we'd need to make the per-fb DPT
large enough to support potentially several
remapped/rotated vmas. How large should that be?
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Wilson Chris P <Chris.P.Wilson@intel.com>
Cc: Tang CQ <cq.tang@intel.com>
Cc: Auld Matthew <matthew.auld@intel.com>
Reviewed-by: Wilson Chris P <Chris.P.Wilson@intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 7 +-
drivers/gpu/drm/i915/display/intel_display.c | 347 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_display.h | 1 +
.../drm/i915/display/intel_display_types.h | 15 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 6 +-
.../drm/i915/display/skl_universal_plane.c | 19 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 7 +
drivers/gpu/drm/i915/gt/intel_ggtt.c | 7 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 5 +
9 files changed, 387 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index c3f2962aa1ebc..fc68c6ffd9d73 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -102,7 +102,8 @@ intel_plane_duplicate_state(struct drm_plane *plane)
__drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
- intel_state->vma = NULL;
+ intel_state->ggtt_vma = NULL;
+ intel_state->dpt_vma = NULL;
intel_state->flags = 0;
/* add reference to fb */
@@ -125,7 +126,9 @@ intel_plane_destroy_state(struct drm_plane *plane,
struct drm_plane_state *state)
{
struct intel_plane_state *plane_state = to_intel_plane_state(state);
- drm_WARN_ON(plane->dev, plane_state->vma);
+
+ drm_WARN_ON(plane->dev, plane_state->ggtt_vma);
+ drm_WARN_ON(plane->dev, plane_state->dpt_vma);
__drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
if (plane_state->hw.fb)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index dd92c97eb8ca0..00621ccea2c40 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -66,6 +66,7 @@
#include "gem/i915_gem_object.h"
#include "gt/intel_rps.h"
+#include "gt/gen8_ppgtt.h"
#include "g4x_dp.h"
#include "g4x_hdmi.h"
@@ -122,6 +123,171 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
static void intel_modeset_setup_hw_state(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx);
+struct i915_dpt {
+ struct i915_address_space vm;
+
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ void __iomem *iomem;
+};
+
+#define i915_is_dpt(vm) ((vm)->is_dpt)
+
+static inline struct i915_dpt *
+i915_vm_to_dpt(struct i915_address_space *vm)
+{
+ BUILD_BUG_ON(offsetof(struct i915_dpt, vm));
+ GEM_BUG_ON(!i915_is_dpt(vm));
+ return container_of(vm, struct i915_dpt, vm);
+}
+
+#define dpt_total_entries(dpt) ((dpt)->vm.total >> PAGE_SHIFT)
+
+static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
+{
+ writeq(pte, addr);
+}
+
+static void dpt_insert_page(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ enum i915_cache_level level,
+ u32 flags)
+{
+ struct i915_dpt *dpt = i915_vm_to_dpt(vm);
+ gen8_pte_t __iomem *base = dpt->iomem;
+
+ gen8_set_pte(base + offset / I915_GTT_PAGE_SIZE,
+ vm->pte_encode(addr, level, flags));
+}
+
+static void dpt_insert_entries(struct i915_address_space *vm,
+ struct i915_vma *vma,
+ enum i915_cache_level level,
+ u32 flags)
+{
+ struct i915_dpt *dpt = i915_vm_to_dpt(vm);
+ gen8_pte_t __iomem *base = dpt->iomem;
+ const gen8_pte_t pte_encode = vm->pte_encode(0, level, flags);
+ struct sgt_iter sgt_iter;
+ dma_addr_t addr;
+ int i;
+
+ /*
+ * Note that we ignore PTE_READ_ONLY here. The caller must be careful
+ * not to allow the user to override access to a read only page.
+ */
+
+ i = vma->node.start / I915_GTT_PAGE_SIZE;
+ for_each_sgt_daddr(addr, sgt_iter, vma->pages)
+ gen8_set_pte(&base[i++], pte_encode | addr);
+}
+
+static void dpt_clear_range(struct i915_address_space *vm,
+ u64 start, u64 length)
+{
+}
+
+static void dpt_bind_vma(struct i915_address_space *vm,
+ struct i915_vm_pt_stash *stash,
+ struct i915_vma *vma,
+ enum i915_cache_level cache_level,
+ u32 flags)
+{
+ struct drm_i915_gem_object *obj = vma->obj;
+ u32 pte_flags;
+
+ /* Applicable to VLV (gen8+ do not support RO in the GGTT) */
+ pte_flags = 0;
+ if (vma->vm->has_read_only && i915_gem_object_is_readonly(obj))
+ pte_flags |= PTE_READ_ONLY;
+
+ vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
+
+ vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
+
+ /*
+ * Without aliasing PPGTT there's no difference between
+ * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
+ * upgrade to both bound if we bind either to avoid double-binding.
+ */
+ atomic_or(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND, &vma->flags);
+}
+
+static void dpt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
+{
+ vm->clear_range(vm, vma->node.start, vma->size);
+}
+
+static void dpt_cleanup(struct i915_address_space *vm)
+{
+ struct i915_dpt *dpt = i915_vm_to_dpt(vm);
+
+ i915_gem_object_put(dpt->obj);
+}
+
+static struct i915_address_space *
+intel_dpt_create(struct drm_gem_object *obj)
+{
+ struct drm_i915_private *i915 = to_i915(obj->dev);
+ size_t size = DIV_ROUND_UP_ULL(obj->size, 512);
+ struct drm_i915_gem_object *dpt_obj;
+ struct i915_address_space *vm;
+ struct i915_dpt *dpt;
+ int ret;
+
+ size = round_up(size, 4096);
+
+ dpt_obj = i915_gem_object_create_stolen(i915, size);
+ if (IS_ERR(dpt_obj))
+ return ERR_CAST(dpt_obj);
+
+ ret = i915_gem_object_set_cache_level(dpt_obj, I915_CACHE_NONE);
+ if (ret) {
+ i915_gem_object_put(dpt_obj);
+ return ERR_PTR(ret);
+ }
+
+ dpt = kzalloc(sizeof(*dpt), GFP_KERNEL);
+ if (!dpt) {
+ i915_gem_object_put(dpt_obj);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ vm = &dpt->vm;
+
+ vm->gt = &i915->gt;
+ vm->i915 = i915;
+ vm->dma = &i915->drm.pdev->dev;
+ vm->total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
+ vm->is_dpt = true;
+
+ i915_address_space_init(vm, VM_CLASS_DPT);
+
+ vm->insert_page = dpt_insert_page;
+ vm->clear_range = dpt_clear_range;
+ vm->insert_entries = dpt_insert_entries;
+ vm->cleanup = dpt_cleanup;
+
+ vm->vma_ops.bind_vma = dpt_bind_vma;
+ vm->vma_ops.unbind_vma = dpt_unbind_vma;
+ vm->vma_ops.set_pages = ggtt_set_pages;
+ vm->vma_ops.clear_pages = clear_pages;
+
+ vm->pte_encode = gen8_ggtt_pte_encode;
+
+ dpt->obj = dpt_obj;
+
+ return &dpt->vm;
+}
+
+static void intel_dpt_destroy(struct i915_address_space *vm)
+{
+ struct i915_dpt *dpt = i915_vm_to_dpt(vm);
+
+ i915_vm_close(&dpt->vm);
+}
+
/* returns HPLL frequency in kHz */
int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
{
@@ -972,6 +1138,9 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
{
struct drm_i915_private *dev_priv = to_i915(fb->dev);
+ if (intel_fb_uses_dpt(fb))
+ return 512 * 4096;
+
/* AUX_DIST needs only 4K alignment */
if ((DISPLAY_VER(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
is_ccs_plane(fb, color_plane))
@@ -1016,6 +1185,62 @@ static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);
}
+static struct i915_vma *
+intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
+ const struct i915_ggtt_view *view,
+ bool uses_fence,
+ unsigned long *out_flags,
+ struct i915_address_space *vm)
+{
+ struct drm_device *dev = fb->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+ struct i915_vma *vma;
+ u32 alignment;
+ int ret;
+
+ if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
+ return ERR_PTR(-EINVAL);
+
+ alignment = 4096 * 512;
+
+ atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
+
+ ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
+ if (ret) {
+ vma = ERR_PTR(ret);
+ goto err;
+ }
+
+ vma = i915_vma_instance(obj, vm, view);
+ if (IS_ERR(vma))
+ goto err;
+
+ if (i915_vma_misplaced(vma, 0, alignment, 0)) {
+ ret = i915_vma_unbind(vma);
+ if (ret) {
+ vma = ERR_PTR(ret);
+ goto err;
+ }
+ }
+
+ ret = i915_vma_pin(vma, 0, alignment, PIN_GLOBAL);
+ if (ret) {
+ vma = ERR_PTR(ret);
+ goto err;
+ }
+
+ vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
+
+ i915_gem_object_flush_if_display(obj);
+
+ i915_vma_get(vma);
+err:
+ atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
+
+ return vma;
+}
+
struct i915_vma *
intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
bool phys_cursor,
@@ -1616,6 +1841,49 @@ static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
intel_wait_for_vblank(dev_priv, crtc->pipe);
}
+static struct i915_vma *intel_dpt_pin(struct i915_address_space *vm)
+{
+ struct drm_i915_private *i915 = vm->i915;
+ struct i915_dpt *dpt = i915_vm_to_dpt(vm);
+ intel_wakeref_t wakeref;
+ struct i915_vma *vma;
+ void __iomem *iomem;
+
+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+ atomic_inc(&i915->gpu_error.pending_fb_pin);
+
+ vma = i915_gem_object_ggtt_pin(dpt->obj, NULL, 0, 4096,
+ HAS_LMEM(i915) ? 0 : PIN_MAPPABLE);
+ if (IS_ERR(vma))
+ goto err;
+
+ iomem = i915_vma_pin_iomap(vma);
+ i915_vma_unpin(vma);
+ if (IS_ERR(iomem)) {
+ vma = iomem;
+ goto err;
+ }
+
+ dpt->vma = vma;
+ dpt->iomem = iomem;
+
+ i915_vma_get(vma);
+
+err:
+ atomic_dec(&i915->gpu_error.pending_fb_pin);
+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+
+ return vma;
+}
+
+static void intel_dpt_unpin(struct i915_address_space *vm)
+{
+ struct i915_dpt *dpt = i915_vm_to_dpt(vm);
+
+ i915_vma_unpin_iomap(dpt->vma);
+ i915_vma_put(dpt->vma);
+}
+
static void
intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
struct intel_initial_plane_config *plane_config)
@@ -1661,12 +1929,12 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
continue;
state = to_intel_plane_state(c->primary->state);
- if (!state->vma)
+ if (!state->ggtt_vma)
continue;
if (intel_plane_ggtt_offset(state) == plane_config->base) {
fb = state->hw.fb;
- vma = state->vma;
+ vma = state->ggtt_vma;
goto valid_fb;
}
}
@@ -1693,7 +1961,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
&intel_state->view);
__i915_vma_pin(vma);
- intel_state->vma = i915_vma_get(vma);
+ intel_state->ggtt_vma = i915_vma_get(vma);
if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
if (vma->fence)
intel_state->flags |= PLANE_HAS_FENCE;
@@ -10548,25 +10816,60 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state)
plane->id == PLANE_CURSOR &&
INTEL_INFO(dev_priv)->display.cursor_needs_physical;
- vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
- &plane_state->view.gtt,
- intel_plane_uses_fence(plane_state),
- &plane_state->flags);
- if (IS_ERR(vma))
- return PTR_ERR(vma);
-
- plane_state->vma = vma;
+ if (!intel_fb_uses_dpt(fb)) {
+ vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
+ &plane_state->view.gtt,
+ intel_plane_uses_fence(plane_state),
+ &plane_state->flags);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
+
+ plane_state->ggtt_vma = vma;
+ } else {
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+
+ vma = intel_dpt_pin(intel_fb->dpt_vm);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
+
+ plane_state->ggtt_vma = vma;
+
+ vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, false,
+ &plane_state->flags, intel_fb->dpt_vm);
+ if (IS_ERR(vma)) {
+ intel_dpt_unpin(intel_fb->dpt_vm);
+ plane_state->ggtt_vma = NULL;
+ return PTR_ERR(vma);
+ }
+
+ plane_state->dpt_vma = vma;
+
+ WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);
+ }
return 0;
}
void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
{
+ struct drm_framebuffer *fb = old_plane_state->hw.fb;
struct i915_vma *vma;
- vma = fetch_and_zero(&old_plane_state->vma);
- if (vma)
- intel_unpin_fb_vma(vma, old_plane_state->flags);
+ if (!intel_fb_uses_dpt(fb)) {
+ vma = fetch_and_zero(&old_plane_state->ggtt_vma);
+ if (vma)
+ intel_unpin_fb_vma(vma, old_plane_state->flags);
+ } else {
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+
+ vma = fetch_and_zero(&old_plane_state->dpt_vma);
+ if (vma)
+ intel_unpin_fb_vma(vma, old_plane_state->flags);
+
+ vma = fetch_and_zero(&old_plane_state->ggtt_vma);
+ if (vma)
+ intel_dpt_unpin(intel_fb->dpt_vm);
+ }
}
/**
@@ -11089,6 +11392,10 @@ static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
drm_framebuffer_cleanup(fb);
+
+ if (intel_fb_uses_dpt(fb))
+ intel_dpt_destroy(intel_fb->dpt_vm);
+
intel_frontbuffer_put(intel_fb->frontbuffer);
kfree(intel_fb);
@@ -11259,6 +11566,18 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
if (ret)
goto err;
+ if (intel_fb_uses_dpt(fb)) {
+ struct i915_address_space *vm;
+
+ vm = intel_dpt_create(&obj->base);
+ if (IS_ERR(vm)) {
+ ret = PTR_ERR(vm);
+ goto err;
+ }
+
+ intel_fb->dpt_vm = vm;
+ }
+
ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
if (ret) {
drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 105294ec2dcc9..a717d52eba0bf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -44,6 +44,7 @@ struct drm_mode_fb_cmd2;
struct drm_modeset_acquire_ctx;
struct drm_plane;
struct drm_plane_state;
+struct i915_address_space;
struct i915_ggtt_view;
struct intel_atomic_state;
struct intel_crtc;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e2e707c4dff56..3c73737f88da4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -129,6 +129,8 @@ struct intel_framebuffer {
struct intel_fb_view normal_view;
struct intel_fb_view rotated_view;
struct intel_fb_view remapped_view;
+
+ struct i915_address_space *dpt_vm;
};
struct intel_fbdev {
@@ -611,7 +613,8 @@ struct intel_plane_state {
enum drm_scaling_filter scaling_filter;
} hw;
- struct i915_vma *vma;
+ struct i915_vma *ggtt_vma;
+ struct i915_vma *dpt_vma;
unsigned long flags;
#define PLANE_HAS_FENCE BIT(0)
@@ -1973,9 +1976,15 @@ intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pip
intel_wait_for_vblank(dev_priv, pipe);
}
-static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
+static inline bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
{
- return i915_ggtt_offset(state->vma);
+ return fb && DISPLAY_VER(to_i915(fb->dev)) >= 13 &&
+ fb->modifier != DRM_FORMAT_MOD_LINEAR;
+}
+
+static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
+{
+ return i915_ggtt_offset(plane_state->ggtt_vma);
}
static inline struct intel_frontbuffer *
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 91dad8004c340..85a0e646884f5 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -736,11 +736,11 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
cache->fence_y_offset = intel_plane_fence_y_offset(plane_state);
drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
- !plane_state->vma->fence);
+ !plane_state->ggtt_vma->fence);
if (plane_state->flags & PLANE_HAS_FENCE &&
- plane_state->vma->fence)
- cache->fence_id = plane_state->vma->fence->id;
+ plane_state->ggtt_vma->fence)
+ cache->fence_id = plane_state->ggtt_vma->fence->id;
else
cache->fence_id = -1;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 75d3ca3dbb372..349a53cef0a94 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -933,6 +933,21 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
return plane_color_ctl;
}
+static u32 skl_surf_address(const struct intel_plane_state *plane_state,
+ int color_plane)
+{
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ u32 offset = plane_state->view.color_plane[color_plane].offset;
+
+ if (intel_fb_uses_dpt(fb)) {
+ WARN_ON(offset & 0x1fffff);
+ return offset >> 9;
+ } else {
+ WARN_ON(offset & 0xfff);
+ return offset;
+ }
+}
+
static void
skl_program_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -943,7 +958,7 @@ skl_program_plane(struct intel_plane *plane,
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
- u32 surf_addr = plane_state->view.color_plane[color_plane].offset;
+ u32 surf_addr = skl_surf_address(plane_state, color_plane);
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
int aux_plane = skl_main_to_aux_plane(fb, color_plane);
@@ -982,7 +997,7 @@ skl_program_plane(struct intel_plane *plane,
}
if (aux_plane) {
- aux_dist = plane_state->view.color_plane[aux_plane].offset - surf_addr;
+ aux_dist = skl_surf_address(plane_state, aux_plane) - surf_addr;
if (DISPLAY_VER(dev_priv) < 12)
aux_dist |= skl_plane_stride(plane_state, aux_plane);
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
index 76a08b9c1f5c8..b9028c2ad3c7d 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
@@ -6,8 +6,15 @@
#ifndef __GEN8_PPGTT_H__
#define __GEN8_PPGTT_H__
+#include <linux/kernel.h>
+
+struct i915_address_space;
struct intel_gt;
+enum i915_cache_level;
struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
+u64 gen8_ggtt_pte_encode(dma_addr_t addr,
+ enum i915_cache_level level,
+ u32 flags);
#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 670c1271e7d51..38742bf33fa37 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -18,6 +18,7 @@
#include "i915_vgpu.h"
#include "intel_gtt.h"
+#include "gen8_ppgtt.h"
static int
i915_get_ggtt_vma_pages(struct i915_vma *vma);
@@ -187,9 +188,9 @@ static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
intel_gtt_chipset_flush();
}
-static u64 gen8_ggtt_pte_encode(dma_addr_t addr,
- enum i915_cache_level level,
- u32 flags)
+u64 gen8_ggtt_pte_encode(dma_addr_t addr,
+ enum i915_cache_level level,
+ u32 flags)
{
gen8_pte_t pte = addr | _PAGE_PRESENT;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index e67e34e179131..79f565aeb8c09 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -245,6 +245,7 @@ struct i915_address_space {
struct dma_resv resv; /* reservation lock for all pd objects, and buffer pool */
#define VM_CLASS_GGTT 0
#define VM_CLASS_PPGTT 1
+#define VM_CLASS_DPT 2
struct drm_i915_gem_object *scratch[4];
/**
@@ -255,6 +256,9 @@ struct i915_address_space {
/* Global GTT */
bool is_ggtt:1;
+ /* Display page table */
+ bool is_dpt:1;
+
/* Some systems support read-only mappings for GGTT and/or PPGTT */
bool has_read_only:1;
@@ -351,6 +355,7 @@ struct i915_ppgtt {
};
#define i915_is_ggtt(vm) ((vm)->is_ggtt)
+#define i915_is_dpt(vm) ((vm)->is_dpt)
int __must_check
i915_vm_lock_objects(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww);
--
2.27.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 06/11] drm/i915/xelpd: Fallback to plane stride limitations when using DPT
2021-04-14 15:51 [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (4 preceding siblings ...)
2021-04-14 15:52 ` [Intel-gfx] [PATCH 05/11] drm/i915/xelpd: First stab at DPT support Imre Deak
@ 2021-04-14 15:52 ` Imre Deak
2021-04-14 15:52 ` [Intel-gfx] [PATCH 07/11] drm/i915/xelpd: Support 128k plane stride Imre Deak
` (8 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Imre Deak @ 2021-04-14 15:52 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
GTT remapping allow us to have planes with strides larger than HW
supports but DPT + GTT remapping is still not properly handled so
falling back to plane HW limitations for now.
This patch can be dropped when DPT + GTT remapping is correctly
handled but until then we need this limitation for all display13
platforms to avoid pipe faults.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++--------
.../gpu/drm/i915/display/intel_display_types.h | 8 ++++++--
2 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 00621ccea2c40..ce685a7ba6a1d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1588,14 +1588,13 @@ u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
*
* The new CCS hash mode makes remapping impossible
*/
- if (!is_ccs_modifier(modifier)) {
- if (DISPLAY_VER(dev_priv) >= 7)
- return 256*1024;
- else if (DISPLAY_VER(dev_priv) >= 4)
- return 128*1024;
- }
-
- return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
+ if (DISPLAY_VER(dev_priv) < 4 || is_ccs_modifier(modifier) ||
+ intel_modifier_uses_dpt(dev_priv, modifier))
+ return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
+ else if (DISPLAY_VER(dev_priv) >= 7)
+ return 256 * 1024;
+ else
+ return 128 * 1024;
}
static u32
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 3c73737f88da4..cdc8fcb8c2aa7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1976,10 +1976,14 @@ intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pip
intel_wait_for_vblank(dev_priv, pipe);
}
+static inline bool intel_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier)
+{
+ return DISPLAY_VER(i915) >= 13 && modifier != DRM_FORMAT_MOD_LINEAR;
+}
+
static inline bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
{
- return fb && DISPLAY_VER(to_i915(fb->dev)) >= 13 &&
- fb->modifier != DRM_FORMAT_MOD_LINEAR;
+ return fb && intel_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
}
static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
--
2.27.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 07/11] drm/i915/xelpd: Support 128k plane stride
2021-04-14 15:51 [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (5 preceding siblings ...)
2021-04-14 15:52 ` [Intel-gfx] [PATCH 06/11] drm/i915/xelpd: Fallback to plane stride limitations when using DPT Imre Deak
@ 2021-04-14 15:52 ` Imre Deak
2021-04-14 15:52 ` [Intel-gfx] [PATCH 08/11] drm/i915/adl_p: Add stride restriction when using DPT Imre Deak
` (7 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Imre Deak @ 2021-04-14 15:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Juha-Pekka Heikkilä
From: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
XE_LPD supports plane strides up to 128KB.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../drm/i915/display/skl_universal_plane.c | 46 +++++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 2 +
2 files changed, 39 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 349a53cef0a94..c5b9669d2aacf 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -481,17 +481,35 @@ skl_plane_max_stride(struct intel_plane *plane,
u32 pixel_format, u64 modifier,
unsigned int rotation)
{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
const struct drm_format_info *info = drm_format_info(pixel_format);
int cpp = info->cpp[0];
+ int max_horizontal_pixels = 8192;
+ int max_stride_bytes;
+
+ if (DISPLAY_VER(i915) >= 13) {
+ /*
+ * The stride in bytes must not exceed of the size
+ * of 128K bytes. For pixel formats of 64bpp will allow
+ * for a 16K pixel surface.
+ */
+ max_stride_bytes = 131072;
+ if (cpp == 8)
+ max_horizontal_pixels = 16384;
+ else
+ max_horizontal_pixels = 65536;
+ } else {
+ /*
+ * "The stride in bytes must not exceed the
+ * of the size of 8K pixels and 32K bytes."
+ */
+ max_stride_bytes = 32768;
+ }
- /*
- * "The stride in bytes must not exceed the
- * of the size of 8K pixels and 32K bytes."
- */
if (drm_rotation_90_or_270(rotation))
- return min(8192, 32768 / cpp);
+ return min(max_horizontal_pixels, max_stride_bytes / cpp);
else
- return min(8192 * cpp, 32768);
+ return min(max_horizontal_pixels * cpp, max_stride_bytes);
}
@@ -1451,7 +1469,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
}
}
- drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191);
+ if (DISPLAY_VER(dev_priv) >= 13)
+ drm_WARN_ON(&dev_priv->drm, x > 65535 || y > 65535);
+ else
+ drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191);
plane_state->view.color_plane[0].offset = offset;
plane_state->view.color_plane[0].x = x;
@@ -1525,7 +1546,10 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
}
}
- drm_WARN_ON(&i915->drm, x > 8191 || y > 8191);
+ if (DISPLAY_VER(i915) >= 13)
+ drm_WARN_ON(&i915->drm, x > 65535 || y > 65535);
+ else
+ drm_WARN_ON(&i915->drm, x > 8191 || y > 8191);
plane_state->view.color_plane[uv_plane].offset = offset;
plane_state->view.color_plane[uv_plane].x = x;
@@ -2238,7 +2262,11 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
- fb->pitches[0] = (val & 0x3ff) * stride_mult;
+
+ if (DISPLAY_VER(dev_priv) >= 13)
+ fb->pitches[0] = (val & PLANE_STRIDE_MASK_XELPD) * stride_mult;
+ else
+ fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
aligned_height = intel_fb_align_height(fb, 0, fb->height);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f80d656331f42..cdcb60b3fa063 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7210,6 +7210,8 @@ enum {
_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
#define PLANE_STRIDE(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
+#define PLANE_STRIDE_MASK REG_GENMASK(10, 0)
+#define PLANE_STRIDE_MASK_XELPD REG_GENMASK(11, 0)
#define _PLANE_POS_1_B 0x7118c
#define _PLANE_POS_2_B 0x7128c
--
2.27.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 08/11] drm/i915/adl_p: Add stride restriction when using DPT
2021-04-14 15:51 [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (6 preceding siblings ...)
2021-04-14 15:52 ` [Intel-gfx] [PATCH 07/11] drm/i915/xelpd: Support 128k plane stride Imre Deak
@ 2021-04-14 15:52 ` Imre Deak
2021-04-14 15:52 ` [Intel-gfx] [PATCH 09/11] drm/i915/adl_p: Disable support for 90/270 FB rotation Imre Deak
` (6 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Imre Deak @ 2021-04-14 15:52 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
Alderlake-P have a new stride restriction when using DPT and it is used
by non linear framebuffers. Stride needs to be a power of two to take
full DPT rows, but stride is a parameter set by userspace.
What we could do is use a fake stride when doing DPT allocation so
HW requirements are met and userspace don't need to be changed to
met this power of two restrictions but this change will take a while
to be implemented so for now adding this restriction in driver to
reject atomic commits that would cause visual corruptions.
BSpec: 53393
Acked-by: Matt Roper <matthew.d.roper@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ce685a7ba6a1d..2eba13898fbea 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11558,6 +11558,15 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
}
}
+ if (IS_ALDERLAKE_P(dev_priv) &&
+ mode_cmd->modifier[i] != DRM_FORMAT_MOD_LINEAR &&
+ !is_power_of_2(mode_cmd->pitches[i])) {
+ drm_dbg_kms(&dev_priv->drm,
+ "plane %d pitch (%d) must be power of two for tiled buffers\n",
+ i, mode_cmd->pitches[i]);
+ goto err;
+ }
+
fb->obj[i] = &obj->base;
}
--
2.27.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 09/11] drm/i915/adl_p: Disable support for 90/270 FB rotation
2021-04-14 15:51 [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (7 preceding siblings ...)
2021-04-14 15:52 ` [Intel-gfx] [PATCH 08/11] drm/i915/adl_p: Add stride restriction when using DPT Imre Deak
@ 2021-04-14 15:52 ` Imre Deak
2021-04-14 15:52 ` [Intel-gfx] [PATCH 10/11] drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs Imre Deak
` (5 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Imre Deak @ 2021-04-14 15:52 UTC (permalink / raw)
To: intel-gfx
The latest specification removed the support for 90/270 FB rotation on
ADL_P, even though legacy Y-tiled surfaces are supported. Align the code
accordingly.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_display_types.h | 6 +++--
drivers/gpu/drm/i915/display/intel_fb.c | 24 +++++++++++++++----
drivers/gpu/drm/i915/display/intel_fb.h | 1 +
.../drm/i915/display/skl_universal_plane.c | 3 +--
4 files changed, 25 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index cdc8fcb8c2aa7..a4c898dd71abb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -127,8 +127,10 @@ struct intel_framebuffer {
/* Params to remap the FB pages and program the plane registers in each view. */
struct intel_fb_view normal_view;
- struct intel_fb_view rotated_view;
- struct intel_fb_view remapped_view;
+ union {
+ struct intel_fb_view rotated_view;
+ struct intel_fb_view remapped_view;
+ };
struct i915_address_space *dpt_vm;
};
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 1b690b21310de..bd862f77762a2 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -743,6 +743,15 @@ static void intel_fb_view_init(struct intel_fb_view *view, enum i915_ggtt_view_t
view->gtt.type = view_type;
}
+bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb)
+{
+ if (DISPLAY_VER(to_i915(fb->base.dev)) >= 13)
+ return false;
+
+ return fb->base.modifier == I915_FORMAT_MOD_Y_TILED ||
+ fb->base.modifier == I915_FORMAT_MOD_Yf_TILED;
+}
+
int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb)
{
struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base);
@@ -753,8 +762,15 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *
unsigned int tile_size = intel_tile_size(i915);
intel_fb_view_init(&fb->normal_view, I915_GGTT_VIEW_NORMAL);
- intel_fb_view_init(&fb->rotated_view, I915_GGTT_VIEW_ROTATED);
- intel_fb_view_init(&fb->remapped_view, I915_GGTT_VIEW_REMAPPED);
+
+ drm_WARN_ON(&i915->drm,
+ intel_fb_supports_90_270_rotation(fb) &&
+ intel_fb_needs_pot_stride_remap(fb));
+
+ if (intel_fb_supports_90_270_rotation(fb))
+ intel_fb_view_init(&fb->rotated_view, I915_GGTT_VIEW_ROTATED);
+ if (intel_fb_needs_pot_stride_remap(fb))
+ intel_fb_view_init(&fb->remapped_view, I915_GGTT_VIEW_REMAPPED);
for (i = 0; i < num_planes; i++) {
struct fb_plane_view_dims view_dims;
@@ -795,9 +811,7 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *
offset = calc_plane_aligned_offset(fb, i, &x, &y);
- /* Y or Yf modifiers required for 90/270 rotation */
- if (fb->base.modifier == I915_FORMAT_MOD_Y_TILED ||
- fb->base.modifier == I915_FORMAT_MOD_Yf_TILED)
+ if (intel_fb_supports_90_270_rotation(fb))
gtt_offset_rotated += calc_plane_remap_info(fb, i, &view_dims,
offset, gtt_offset_rotated, x, y,
&fb->rotated_view);
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index e0953d8855b6b..47716487de19c 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -46,6 +46,7 @@ u32 intel_plane_compute_aligned_offset(int *x, int *y,
const struct intel_plane_state *state,
int color_plane);
+bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb);
int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb);
void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation,
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index c5b9669d2aacf..c06a3d4a9429d 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1160,8 +1160,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
}
if (drm_rotation_90_or_270(rotation)) {
- if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
- fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
+ if (!intel_fb_supports_90_270_rotation(to_intel_framebuffer(fb))) {
drm_dbg_kms(&dev_priv->drm,
"Y/Yf tiling required for 90/270!\n");
return -EINVAL;
--
2.27.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 10/11] drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs
2021-04-14 15:51 [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (8 preceding siblings ...)
2021-04-14 15:52 ` [Intel-gfx] [PATCH 09/11] drm/i915/adl_p: Disable support for 90/270 FB rotation Imre Deak
@ 2021-04-14 15:52 ` Imre Deak
2021-04-15 22:12 ` Imre Deak
2021-04-14 15:52 ` [Intel-gfx] [PATCH 11/11] drm/i915/adl_p: Enable remapping to pad DPT FB strides to POT Imre Deak
` (4 subsequent siblings)
14 siblings, 1 reply; 24+ messages in thread
From: Imre Deak @ 2021-04-14 15:52 UTC (permalink / raw)
To: intel-gfx
The specification only requires DPT FB strides to be POT aligned, but
there seems to be also a minimum of 8 stride tile requirement. Scanning
out FBs with < 8 stride tiles will result in pipe faults (even though
the stride is POT aligned).
Signed-off-by: Imre Deak <imre.deak@intel.com>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fb.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index bd862f77762a2..2ee10ece27c57 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -609,7 +609,11 @@ plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane,
unsigned int pitch_tiles)
{
if (intel_fb_needs_pot_stride_remap(fb))
- return roundup_pow_of_two(pitch_tiles);
+ /*
+ * ADL_P, the only platform needing a POT stride has a minimum
+ * of 8 stride tiles.
+ */
+ return roundup_pow_of_two(max(pitch_tiles, 8u));
else
return pitch_tiles;
}
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH 11/11] drm/i915/adl_p: Enable remapping to pad DPT FB strides to POT
2021-04-14 15:51 [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (9 preceding siblings ...)
2021-04-14 15:52 ` [Intel-gfx] [PATCH 10/11] drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs Imre Deak
@ 2021-04-14 15:52 ` Imre Deak
2021-04-14 17:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/adl_p: Add support for Display Page Tables Patchwork
` (3 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Imre Deak @ 2021-04-14 15:52 UTC (permalink / raw)
To: intel-gfx
Enable padding of DPT FB strides to POT, using the FB remapping logic.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++++++++----
drivers/gpu/drm/i915/display/intel_fb.c | 7 +++++--
drivers/gpu/drm/i915/display/intel_fb.h | 1 +
3 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2eba13898fbea..bb5cb3f37c408 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -227,16 +227,22 @@ static void dpt_cleanup(struct i915_address_space *vm)
}
static struct i915_address_space *
-intel_dpt_create(struct drm_gem_object *obj)
+intel_dpt_create(struct intel_framebuffer *fb)
{
+ struct drm_gem_object *obj = &intel_fb_obj(&fb->base)->base;
struct drm_i915_private *i915 = to_i915(obj->dev);
- size_t size = DIV_ROUND_UP_ULL(obj->size, 512);
struct drm_i915_gem_object *dpt_obj;
struct i915_address_space *vm;
struct i915_dpt *dpt;
+ size_t size;
int ret;
- size = round_up(size, 4096);
+ if (intel_fb_needs_pot_stride_remap(fb))
+ size = intel_remapped_info_size(&fb->remapped_view.gtt.remapped);
+ else
+ size = DIV_ROUND_UP_ULL(obj->size, I915_GTT_PAGE_SIZE);
+
+ size = round_up(size * sizeof(gen8_pte_t), I915_GTT_PAGE_SIZE);
dpt_obj = i915_gem_object_create_stolen(i915, size);
if (IS_ERR(dpt_obj))
@@ -11558,8 +11564,10 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
}
}
+ /* TODO: Add POT stride remapping support for CCS formats as well. */
if (IS_ALDERLAKE_P(dev_priv) &&
mode_cmd->modifier[i] != DRM_FORMAT_MOD_LINEAR &&
+ !intel_fb_needs_pot_stride_remap(intel_fb) &&
!is_power_of_2(mode_cmd->pitches[i])) {
drm_dbg_kms(&dev_priv->drm,
"plane %d pitch (%d) must be power of two for tiled buffers\n",
@@ -11577,7 +11585,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
if (intel_fb_uses_dpt(fb)) {
struct i915_address_space *vm;
- vm = intel_dpt_create(&obj->base);
+ vm = intel_dpt_create(intel_fb);
if (IS_ERR(vm)) {
ret = PTR_ERR(vm);
goto err;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 2ee10ece27c57..ebfee5e7cbc8b 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -486,9 +486,12 @@ static bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
return true;
}
-static bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb)
+bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb)
{
- return false;
+ struct drm_i915_private *i915 = to_i915(fb->base.dev);
+
+ return IS_ALDERLAKE_P(i915) && fb->base.modifier != DRM_FORMAT_MOD_LINEAR &&
+ !is_ccs_modifier(fb->base.modifier);
}
static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index 47716487de19c..f1c9754001e52 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -46,6 +46,7 @@ u32 intel_plane_compute_aligned_offset(int *x, int *y,
const struct intel_plane_state *state,
int color_plane);
+bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb);
bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb);
int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb);
--
2.27.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/adl_p: Add support for Display Page Tables
2021-04-14 15:51 [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (10 preceding siblings ...)
2021-04-14 15:52 ` [Intel-gfx] [PATCH 11/11] drm/i915/adl_p: Enable remapping to pad DPT FB strides to POT Imre Deak
@ 2021-04-14 17:22 ` Patchwork
2021-04-14 17:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
14 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2021-04-14 17:22 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/adl_p: Add support for Display Page Tables
URL : https://patchwork.freedesktop.org/series/89078/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fae46e1c4858 drm/i915: Pass intel_framebuffer instad of drm_framebuffer to intel_fill_fb_info()
-:156: CHECK:LINE_SPACING: Please don't use multiple blank lines
#156: FILE: drivers/gpu/drm/i915/display/intel_fb.h:49:
+
total: 0 errors, 0 warnings, 1 checks, 129 lines checked
ee88b73d7f94 drm/i915/xelpd: add XE_LPD display characteristics
c9f4c699d4b4 drm/i915/adl_p: Add PCI Devices IDs
-:25: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#25: FILE: include/drm/i915_pciids.h:649:
+#define INTEL_ADLP_IDS(info) \
+ INTEL_VGA_DEVICE(0x46A0, info), \
+ INTEL_VGA_DEVICE(0x46A1, info), \
+ INTEL_VGA_DEVICE(0x46A2, info), \
+ INTEL_VGA_DEVICE(0x46A3, info), \
+ INTEL_VGA_DEVICE(0x46A6, info), \
+ INTEL_VGA_DEVICE(0x46A8, info), \
+ INTEL_VGA_DEVICE(0x46AA, info), \
+ INTEL_VGA_DEVICE(0x462A, info), \
+ INTEL_VGA_DEVICE(0x4626, info), \
+ INTEL_VGA_DEVICE(0x4628, info), \
+ INTEL_VGA_DEVICE(0x46B0, info), \
+ INTEL_VGA_DEVICE(0x46B1, info), \
+ INTEL_VGA_DEVICE(0x46B2, info), \
+ INTEL_VGA_DEVICE(0x46B3, info), \
+ INTEL_VGA_DEVICE(0x46C0, info), \
+ INTEL_VGA_DEVICE(0x46C1, info), \
+ INTEL_VGA_DEVICE(0x46C2, info), \
+ INTEL_VGA_DEVICE(0x46C3, info)
-:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#25: FILE: include/drm/i915_pciids.h:649:
+#define INTEL_ADLP_IDS(info) \
+ INTEL_VGA_DEVICE(0x46A0, info), \
+ INTEL_VGA_DEVICE(0x46A1, info), \
+ INTEL_VGA_DEVICE(0x46A2, info), \
+ INTEL_VGA_DEVICE(0x46A3, info), \
+ INTEL_VGA_DEVICE(0x46A6, info), \
+ INTEL_VGA_DEVICE(0x46A8, info), \
+ INTEL_VGA_DEVICE(0x46AA, info), \
+ INTEL_VGA_DEVICE(0x462A, info), \
+ INTEL_VGA_DEVICE(0x4626, info), \
+ INTEL_VGA_DEVICE(0x4628, info), \
+ INTEL_VGA_DEVICE(0x46B0, info), \
+ INTEL_VGA_DEVICE(0x46B1, info), \
+ INTEL_VGA_DEVICE(0x46B2, info), \
+ INTEL_VGA_DEVICE(0x46B3, info), \
+ INTEL_VGA_DEVICE(0x46C0, info), \
+ INTEL_VGA_DEVICE(0x46C1, info), \
+ INTEL_VGA_DEVICE(0x46C2, info), \
+ INTEL_VGA_DEVICE(0x46C3, info)
total: 1 errors, 0 warnings, 1 checks, 25 lines checked
9c24583b5bbd drm/i915/adl_p: ADL_P device info enabling
4a28c5ef22b0 drm/i915/xelpd: First stab at DPT support
-:583: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#583: FILE: drivers/gpu/drm/i915/display/skl_universal_plane.c:945:
+ return offset >> 9;
+ } else {
total: 0 errors, 1 warnings, 0 checks, 586 lines checked
c4779e2af5ce drm/i915/xelpd: Fallback to plane stride limitations when using DPT
ae0259160293 drm/i915/xelpd: Support 128k plane stride
3ab439b2e61b drm/i915/adl_p: Add stride restriction when using DPT
dd8b2c31734c drm/i915/adl_p: Disable support for 90/270 FB rotation
a48fcda970df drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs
a992015218bc drm/i915/adl_p: Enable remapping to pad DPT FB strides to POT
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adl_p: Add support for Display Page Tables
2021-04-14 15:51 [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (11 preceding siblings ...)
2021-04-14 17:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/adl_p: Add support for Display Page Tables Patchwork
@ 2021-04-14 17:50 ` Patchwork
2021-04-14 20:32 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-04-15 11:29 ` [Intel-gfx] [PATCH 00/11] " Jani Nikula
14 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2021-04-14 17:50 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4026 bytes --]
== Series Details ==
Series: drm/i915/adl_p: Add support for Display Page Tables
URL : https://patchwork.freedesktop.org/series/89078/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9971 -> Patchwork_19939
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/index.html
Known issues
------------
Here are the changes found in Patchwork_19939 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@semaphore:
- fi-bsw-nick: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/fi-bsw-nick/igt@amdgpu/amd_basic@semaphore.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [PASS][2] -> [DMESG-FAIL][3] ([i915#165])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][4] -> [FAIL][5] ([i915#1372])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [INCOMPLETE][6] ([i915#2782] / [i915#2940]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/fi-bsw-nick/igt@i915_selftest@live@execlists.html
#### Warnings ####
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: [FAIL][8] ([i915#579]) -> [SKIP][9] ([fdo#109271])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
Participating hosts (45 -> 41)
------------------------------
Missing (4): fi-icl-y fi-ilk-m540 fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9971 -> Patchwork_19939
CI-20190529: 20190529
CI_DRM_9971: 8f38b366ca75c83434d586430306b9f83499f1b2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6064: 48d89e2c65c54883b0776930a884e6d3bcefb45b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19939: a992015218bc03e5ae4315a3c225da2336c2d001 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a992015218bc drm/i915/adl_p: Enable remapping to pad DPT FB strides to POT
a48fcda970df drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs
dd8b2c31734c drm/i915/adl_p: Disable support for 90/270 FB rotation
3ab439b2e61b drm/i915/adl_p: Add stride restriction when using DPT
ae0259160293 drm/i915/xelpd: Support 128k plane stride
c4779e2af5ce drm/i915/xelpd: Fallback to plane stride limitations when using DPT
4a28c5ef22b0 drm/i915/xelpd: First stab at DPT support
9c24583b5bbd drm/i915/adl_p: ADL_P device info enabling
c9f4c699d4b4 drm/i915/adl_p: Add PCI Devices IDs
ee88b73d7f94 drm/i915/xelpd: add XE_LPD display characteristics
fae46e1c4858 drm/i915: Pass intel_framebuffer instad of drm_framebuffer to intel_fill_fb_info()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/index.html
[-- Attachment #1.2: Type: text/html, Size: 4858 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/adl_p: Add support for Display Page Tables
2021-04-14 15:51 [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (12 preceding siblings ...)
2021-04-14 17:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-04-14 20:32 ` Patchwork
2021-04-15 11:29 ` [Intel-gfx] [PATCH 00/11] " Jani Nikula
14 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2021-04-14 20:32 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 28705 bytes --]
== Series Details ==
Series: drm/i915/adl_p: Add support for Display Page Tables
URL : https://patchwork.freedesktop.org/series/89078/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9971_full -> Patchwork_19939_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_19939_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19939_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19939_full:
### IGT changes ###
#### Warnings ####
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [FAIL][1] ([i915#2842]) -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-iclb3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-iclb4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
Known issues
------------
Here are the changes found in Patchwork_19939_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#658])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-iclb2/igt@feature_discovery@psr2.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-iclb5/igt@feature_discovery@psr2.html
* igt@gem_create@create-clear:
- shard-skl: [PASS][5] -> [FAIL][6] ([i915#3160])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-skl2/igt@gem_create@create-clear.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-skl9/igt@gem_create@create-clear.html
* igt@gem_ctx_persistence@process:
- shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-snb6/igt@gem_ctx_persistence@process.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][8] -> [TIMEOUT][9] ([i915#2369] / [i915#3063])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-tglb1/igt@gem_eio@unwedge-stress.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-tglb8/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_endless@dispatch@vcs0:
- shard-iclb: [PASS][10] -> [INCOMPLETE][11] ([i915#2502])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-iclb4/igt@gem_exec_endless@dispatch@vcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-iclb4/igt@gem_exec_endless@dispatch@vcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][12] ([i915#2846])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl7/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-kbl: NOTRUN -> [FAIL][13] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl1/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][14] -> [FAIL][15] ([i915#2842]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_whisper@basic-queues-forked-all:
- shard-glk: [PASS][16] -> [DMESG-WARN][17] ([i915#118] / [i915#95])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-glk9/igt@gem_exec_whisper@basic-queues-forked-all.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-glk6/igt@gem_exec_whisper@basic-queues-forked-all.html
* igt@gem_mmap_gtt@cpuset-medium-copy:
- shard-iclb: [PASS][18] -> [FAIL][19] ([i915#2428])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-iclb1/igt@gem_mmap_gtt@cpuset-medium-copy.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-iclb7/igt@gem_mmap_gtt@cpuset-medium-copy.html
* igt@gem_mmap_offset@clear:
- shard-glk: [PASS][20] -> [FAIL][21] ([i915#1888] / [i915#3160])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-glk1/igt@gem_mmap_offset@clear.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-glk4/igt@gem_mmap_offset@clear.html
* igt@gem_pwrite@basic-exhaustion:
- shard-skl: NOTRUN -> [WARN][22] ([i915#2658])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-skl9/igt@gem_pwrite@basic-exhaustion.html
- shard-apl: NOTRUN -> [WARN][23] ([i915#2658])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl8/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_render_copy@yf-tiled-to-vebox-x-tiled:
- shard-kbl: NOTRUN -> [SKIP][24] ([fdo#109271]) +61 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl1/igt@gem_render_copy@yf-tiled-to-vebox-x-tiled.html
* igt@gem_userptr_blits@set-cache-level:
- shard-skl: NOTRUN -> [FAIL][25] ([i915#3324])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-skl9/igt@gem_userptr_blits@set-cache-level.html
- shard-apl: NOTRUN -> [FAIL][26] ([i915#3324])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl8/igt@gem_userptr_blits@set-cache-level.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][27] ([i915#3318])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl7/igt@gem_userptr_blits@vma-merge.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][28] -> [DMESG-WARN][29] ([i915#180]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-apl6/igt@gem_workarounds@suspend-resume-context.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][30] -> [DMESG-WARN][31] ([i915#1436] / [i915#716])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-apl8/igt@gen9_exec_parse@allowed-single.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl1/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-dpms:
- shard-kbl: NOTRUN -> [FAIL][32] ([i915#454])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl7/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_big_joiner@invalid-modeset:
- shard-apl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#2705])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl7/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_ccs@pipe-c-random-ccs-data:
- shard-snb: NOTRUN -> [SKIP][34] ([fdo#109271]) +69 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-snb6/igt@kms_ccs@pipe-c-random-ccs-data.html
* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-skl: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-skl1/igt@kms_chamelium@hdmi-aspect-ratio.html
* igt@kms_color_chamelium@pipe-a-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +13 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl8/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-c-ctm-blue-to-red:
- shard-kbl: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl1/igt@kms_color_chamelium@pipe-c-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
- shard-snb: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +3 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-snb6/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][39] ([i915#1319]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl8/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@lic:
- shard-kbl: NOTRUN -> [TIMEOUT][40] ([i915#1319])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl1/igt@kms_content_protection@lic.html
* igt@kms_content_protection@uevent:
- shard-apl: NOTRUN -> [FAIL][41] ([i915#2105])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl6/igt@kms_content_protection@uevent.html
* igt@kms_draw_crc@draw-method-rgb565-blt-ytiled:
- shard-skl: [PASS][42] -> [DMESG-WARN][43] ([i915#1982])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-skl6/igt@kms_draw_crc@draw-method-rgb565-blt-ytiled.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-skl10/igt@kms_draw_crc@draw-method-rgb565-blt-ytiled.html
* igt@kms_flip@2x-flip-vs-panning-vs-hang:
- shard-skl: NOTRUN -> [SKIP][44] ([fdo#109271]) +28 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-skl1/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][45] -> [FAIL][46] ([i915#79])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][47] -> [DMESG-WARN][48] ([i915#180]) +6 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-skl: [PASS][49] -> [FAIL][50] ([i915#2122]) +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-skl8/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-skl2/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#2672])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-apl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#2642])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][53] -> [FAIL][54] ([i915#1188])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#533])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl6/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-kbl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#533])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl1/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_plane@plane-panning-bottom-right-pipe-b-planes:
- shard-snb: [PASS][57] -> [SKIP][58] ([fdo#109271]) +3 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-snb5/igt@kms_plane@plane-panning-bottom-right-pipe-b-planes.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-snb6/igt@kms_plane@plane-panning-bottom-right-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][59] ([fdo#108145] / [i915#265]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-kbl: NOTRUN -> [FAIL][60] ([fdo#108145] / [i915#265])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl1/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-apl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#2733])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl7/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#658]) +2 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-1:
- shard-skl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#658])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-skl1/igt@kms_psr2_sf@plane-move-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-kbl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#658]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][65] -> [SKIP][66] ([fdo#109441])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#2437]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl7/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id:
- shard-kbl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2437])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl1/igt@kms_writeback@writeback-fb-id.html
* igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
- shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271]) +182 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl6/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html
* igt@sysfs_clients@sema-10:
- shard-apl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#2994]) +3 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl6/igt@sysfs_clients@sema-10.html
* igt@sysfs_clients@split-50:
- shard-kbl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#2994])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl1/igt@sysfs_clients@split-50.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][72] ([i915#2842]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-glk: [FAIL][74] ([i915#2842]) -> [PASS][75] +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-glk8/igt@gem_exec_fair@basic-none@rcs0.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-glk5/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [FAIL][76] ([i915#2842]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-tglb1/igt@gem_exec_fair@basic-pace@bcs0.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-tglb8/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [FAIL][78] ([i915#2842]) -> [PASS][79] +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [SKIP][80] ([fdo#109271]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_whisper@basic-contexts-forked:
- shard-glk: [DMESG-WARN][82] ([i915#118] / [i915#95]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-glk2/igt@gem_exec_whisper@basic-contexts-forked.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-glk7/igt@gem_exec_whisper@basic-contexts-forked.html
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [FAIL][84] ([i915#2574]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-tglb5/igt@kms_async_flips@test-time-stamp.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-tglb3/igt@kms_async_flips@test-time-stamp.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][86] ([i915#180]) -> [PASS][87] +4 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-apl: [DMESG-WARN][88] ([i915#180]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-apl8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][90] ([fdo#108145] / [i915#265]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][92] ([fdo#109441]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][94] ([i915#2681] / [i915#2684]) -> [WARN][95] ([i915#1804] / [i915#2684])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-iclb: [SKIP][96] ([i915#2920]) -> [SKIP][97] ([i915#658])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][98], [FAIL][99], [FAIL][100], [FAIL][101], [FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#602]) -> ([FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116]) ([i915#180] / [i915#1814] / [i915#2292] / [i915#2505] / [i915#3002] / [i915#602])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-kbl6/igt@runner@aborted.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-kbl6/igt@runner@aborted.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-kbl7/igt@runner@aborted.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-kbl2/igt@runner@aborted.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-kbl1/igt@runner@aborted.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-kbl6/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-kbl6/igt@runner@aborted.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-kbl1/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-kbl2/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl6/igt@runner@aborted.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl2/igt@runner@aborted.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl3/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl3/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl4/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl4/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl1/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl4/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl4/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-kbl4/igt@runner@aborted.html
- shard-apl: ([FAIL][117], [FAIL][118]) ([fdo#109271] / [i915#1814] / [i915#3002]) -> ([FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#716])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-apl6/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-apl8/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl2/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl1/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl1/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-apl2/igt@runner@aborted.html
- shard-skl: ([FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126]) ([i915#1814] / [i915#2029] / [i915#3002]) -> ([FAIL][127], [FAIL][128]) ([i915#3002])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-skl9/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-skl7/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-skl2/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9971/shard-skl2/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-skl4/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/shard-skl8/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2292]: https://gitlab.freedesktop.org/drm/intel/issues/2292
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#2428]: https://gitlab.freedesktop.org/drm/intel/issues/2428
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#2574]: https://gitlab.freedesktop.org/drm/intel/issues/2574
[i915#2642]: https://gitlab.freedesktop.org/drm/intel/issues/2642
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2733]: https://gitlab.freedesktop.org/drm/intel/issues/2733
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3160]: https://gitlab.freedesktop.org/drm/intel/issues/3160
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3324]: https://gitlab.freedesktop.org/drm/intel/issues/3324
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9971 -> Patchwork_19939
CI-20190529: 20190529
CI_DRM_9971: 8f38b366ca75c83434d586430306b9f83499f1b2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6064: 48d89e2c65c54883b0776930a884e6d3bcefb45b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19939: a992015218bc03e5ae4315a3c225da2336c2d001 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19939/index.html
[-- Attachment #1.2: Type: text/html, Size: 36054 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables
2021-04-14 15:51 [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (13 preceding siblings ...)
2021-04-14 20:32 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2021-04-15 11:29 ` Jani Nikula
2021-04-21 11:03 ` Jani Nikula
14 siblings, 1 reply; 24+ messages in thread
From: Jani Nikula @ 2021-04-15 11:29 UTC (permalink / raw)
To: Imre Deak, intel-gfx; +Cc: Daniel Vetter
On Wed, 14 Apr 2021, Imre Deak <imre.deak@intel.com> wrote:
> Alder Lake-P adds a new Display Page Table hardware structure, mapping
> tiled framebuffer pages to the display engine, reducing the address
> space required in GGTT for these framebuffers.
>
> This patchset adds support for this taking a minimum set of dependency
> patches from the ADL_P enabling patchset at
> https://patchwork.freedesktop.org/series/87897/
Cc: Daniel
I guess we'll need a topic branch for the base enabling to merge to both
din and dign? I guess it'll need to include the stuff in
topic/intel-gen-to-ver too.
Shared stuff like this keeps being a problem with the separate dign
branch, especially when the only way to sync is to merge both din and
dign to drm-next and then backmerge to both.
BR,
Jani.
>
> Clinton Taylor (2):
> drm/i915/adl_p: Add PCI Devices IDs
> drm/i915/adl_p: ADL_P device info enabling
>
> Imre Deak (4):
> drm/i915: Pass intel_framebuffer instad of drm_framebuffer to
> intel_fill_fb_info()
> drm/i915/adl_p: Disable support for 90/270 FB rotation
> drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs
> drm/i915/adl_p: Enable remapping to pad DPT FB strides to POT
>
> José Roberto de Souza (2):
> drm/i915/xelpd: Fallback to plane stride limitations when using DPT
> drm/i915/adl_p: Add stride restriction when using DPT
>
> Juha-Pekka Heikkilä (1):
> drm/i915/xelpd: Support 128k plane stride
>
> Matt Roper (1):
> drm/i915/xelpd: add XE_LPD display characteristics
>
> Ville Syrjälä (1):
> drm/i915/xelpd: First stab at DPT support
>
> arch/x86/kernel/early-quirks.c | 1 +
> .../gpu/drm/i915/display/intel_atomic_plane.c | 7 +-
> drivers/gpu/drm/i915/display/intel_display.c | 381 ++++++++++++++++--
> drivers/gpu/drm/i915/display/intel_display.h | 1 +
> .../drm/i915/display/intel_display_types.h | 25 +-
> drivers/gpu/drm/i915/display/intel_fb.c | 92 +++--
> drivers/gpu/drm/i915/display/intel_fb.h | 5 +-
> drivers/gpu/drm/i915/display/intel_fbc.c | 6 +-
> .../drm/i915/display/skl_universal_plane.c | 68 +++-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 7 +
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 7 +-
> drivers/gpu/drm/i915/gt/intel_gtt.h | 5 +
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 22 +
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> drivers/gpu/drm/i915/intel_device_info.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> include/drm/i915_pciids.h | 21 +
> 18 files changed, 567 insertions(+), 86 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 10/11] drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs
2021-04-14 15:52 ` [Intel-gfx] [PATCH 10/11] drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs Imre Deak
@ 2021-04-15 22:12 ` Imre Deak
2021-05-06 11:11 ` Kahola, Mika
0 siblings, 1 reply; 24+ messages in thread
From: Imre Deak @ 2021-04-15 22:12 UTC (permalink / raw)
To: intel-gfx
On Wed, Apr 14, 2021 at 06:52:07PM +0300, Imre Deak wrote:
> The specification only requires DPT FB strides to be POT aligned, but
> there seems to be also a minimum of 8 stride tile requirement. Scanning
> out FBs with < 8 stride tiles will result in pipe faults (even though
> the stride is POT aligned).
This is now confirmed in bspec (index 53393).
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fb.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index bd862f77762a2..2ee10ece27c57 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -609,7 +609,11 @@ plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane,
> unsigned int pitch_tiles)
> {
> if (intel_fb_needs_pot_stride_remap(fb))
> - return roundup_pow_of_two(pitch_tiles);
> + /*
> + * ADL_P, the only platform needing a POT stride has a minimum
> + * of 8 stride tiles.
> + */
> + return roundup_pow_of_two(max(pitch_tiles, 8u));
> else
> return pitch_tiles;
> }
> --
> 2.27.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables
2021-04-15 11:29 ` [Intel-gfx] [PATCH 00/11] " Jani Nikula
@ 2021-04-21 11:03 ` Jani Nikula
2021-04-21 11:24 ` Imre Deak
0 siblings, 1 reply; 24+ messages in thread
From: Jani Nikula @ 2021-04-21 11:03 UTC (permalink / raw)
To: Imre Deak, intel-gfx; +Cc: Daniel Vetter
On Thu, 15 Apr 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Wed, 14 Apr 2021, Imre Deak <imre.deak@intel.com> wrote:
>> Alder Lake-P adds a new Display Page Table hardware structure, mapping
>> tiled framebuffer pages to the display engine, reducing the address
>> space required in GGTT for these framebuffers.
>>
>> This patchset adds support for this taking a minimum set of dependency
>> patches from the ADL_P enabling patchset at
>> https://patchwork.freedesktop.org/series/87897/
>
> Cc: Daniel
>
> I guess we'll need a topic branch for the base enabling to merge to both
> din and dign? I guess it'll need to include the stuff in
> topic/intel-gen-to-ver too.
>
> Shared stuff like this keeps being a problem with the separate dign
> branch, especially when the only way to sync is to merge both din and
> dign to drm-next and then backmerge to both.
I've created the topic branch.
When this series starts getting ready to merge, please use the
topic/adl-p-enabling branch, so we can merge it to both drm-intel-next
and drm-intel-gt-next.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables
2021-04-21 11:03 ` Jani Nikula
@ 2021-04-21 11:24 ` Imre Deak
2021-04-21 12:12 ` Jani Nikula
0 siblings, 1 reply; 24+ messages in thread
From: Imre Deak @ 2021-04-21 11:24 UTC (permalink / raw)
To: Jani Nikula; +Cc: Daniel Vetter, intel-gfx
On Wed, Apr 21, 2021 at 02:03:45PM +0300, Jani Nikula wrote:
> On Thu, 15 Apr 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > On Wed, 14 Apr 2021, Imre Deak <imre.deak@intel.com> wrote:
> >> Alder Lake-P adds a new Display Page Table hardware structure, mapping
> >> tiled framebuffer pages to the display engine, reducing the address
> >> space required in GGTT for these framebuffers.
> >>
> >> This patchset adds support for this taking a minimum set of dependency
> >> patches from the ADL_P enabling patchset at
> >> https://patchwork.freedesktop.org/series/87897/
> >
> > Cc: Daniel
> >
> > I guess we'll need a topic branch for the base enabling to merge to both
> > din and dign? I guess it'll need to include the stuff in
> > topic/intel-gen-to-ver too.
> >
> > Shared stuff like this keeps being a problem with the separate dign
> > branch, especially when the only way to sync is to merge both din and
> > dign to drm-next and then backmerge to both.
>
> I've created the topic branch.
>
> When this series starts getting ready to merge, please use the
> topic/adl-p-enabling branch, so we can merge it to both drm-intel-next
> and drm-intel-gt-next.
Ok, thanks, I would need a review for 4 (trivial) patches in the
patchset. Could you explain the reason for a separate branch?
> BR,
> Jani.
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables
2021-04-21 11:24 ` Imre Deak
@ 2021-04-21 12:12 ` Jani Nikula
2021-04-21 19:21 ` Imre Deak
0 siblings, 1 reply; 24+ messages in thread
From: Jani Nikula @ 2021-04-21 12:12 UTC (permalink / raw)
To: Imre Deak; +Cc: Daniel Vetter, intel-gfx
On Wed, 21 Apr 2021, Imre Deak <imre.deak@intel.com> wrote:
> On Wed, Apr 21, 2021 at 02:03:45PM +0300, Jani Nikula wrote:
>> On Thu, 15 Apr 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>> > On Wed, 14 Apr 2021, Imre Deak <imre.deak@intel.com> wrote:
>> >> Alder Lake-P adds a new Display Page Table hardware structure, mapping
>> >> tiled framebuffer pages to the display engine, reducing the address
>> >> space required in GGTT for these framebuffers.
>> >>
>> >> This patchset adds support for this taking a minimum set of dependency
>> >> patches from the ADL_P enabling patchset at
>> >> https://patchwork.freedesktop.org/series/87897/
>> >
>> > Cc: Daniel
>> >
>> > I guess we'll need a topic branch for the base enabling to merge to both
>> > din and dign? I guess it'll need to include the stuff in
>> > topic/intel-gen-to-ver too.
>> >
>> > Shared stuff like this keeps being a problem with the separate dign
>> > branch, especially when the only way to sync is to merge both din and
>> > dign to drm-next and then backmerge to both.
>>
>> I've created the topic branch.
>>
>> When this series starts getting ready to merge, please use the
>> topic/adl-p-enabling branch, so we can merge it to both drm-intel-next
>> and drm-intel-gt-next.
>
> Ok, thanks, I would need a review for 4 (trivial) patches in the
> patchset. Could you explain the reason for a separate branch?
drm-intel-next and drm-intel-gt-next only get synced via merges to
drm-next, and backmerges back to each branch. If adl-p basic enabling
patches (PCI IDs, device info, etc.) only get merged to drm-intel-next,
any gt enabling in drm-intel-gt-next will be pending on the merge +
backmerge, which will be some time after the next merge window. At least
three weeks away. Additionally accumulating merge conflicts.
With the topic branch, we can merge the basics to both right away, and
continue with details in each branch separately.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables
2021-04-21 12:12 ` Jani Nikula
@ 2021-04-21 19:21 ` Imre Deak
0 siblings, 0 replies; 24+ messages in thread
From: Imre Deak @ 2021-04-21 19:21 UTC (permalink / raw)
To: Jani Nikula; +Cc: Daniel Vetter, intel-gfx
On Wed, Apr 21, 2021 at 03:12:48PM +0300, Jani Nikula wrote:
> On Wed, 21 Apr 2021, Imre Deak <imre.deak@intel.com> wrote:
> > On Wed, Apr 21, 2021 at 02:03:45PM +0300, Jani Nikula wrote:
> >> On Thu, 15 Apr 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> >> > On Wed, 14 Apr 2021, Imre Deak <imre.deak@intel.com> wrote:
> >> >> Alder Lake-P adds a new Display Page Table hardware structure, mapping
> >> >> tiled framebuffer pages to the display engine, reducing the address
> >> >> space required in GGTT for these framebuffers.
> >> >>
> >> >> This patchset adds support for this taking a minimum set of dependency
> >> >> patches from the ADL_P enabling patchset at
> >> >> https://patchwork.freedesktop.org/series/87897/
> >> >
> >> > Cc: Daniel
> >> >
> >> > I guess we'll need a topic branch for the base enabling to merge to both
> >> > din and dign? I guess it'll need to include the stuff in
> >> > topic/intel-gen-to-ver too.
> >> >
> >> > Shared stuff like this keeps being a problem with the separate dign
> >> > branch, especially when the only way to sync is to merge both din and
> >> > dign to drm-next and then backmerge to both.
> >>
> >> I've created the topic branch.
> >>
> >> When this series starts getting ready to merge, please use the
> >> topic/adl-p-enabling branch, so we can merge it to both drm-intel-next
> >> and drm-intel-gt-next.
> >
> > Ok, thanks, I would need a review for 4 (trivial) patches in the
> > patchset. Could you explain the reason for a separate branch?
>
> drm-intel-next and drm-intel-gt-next only get synced via merges to
> drm-next, and backmerges back to each branch. If adl-p basic enabling
> patches (PCI IDs, device info, etc.) only get merged to drm-intel-next,
> any gt enabling in drm-intel-gt-next will be pending on the merge +
> backmerge, which will be some time after the next merge window. At least
> three weeks away. Additionally accumulating merge conflicts.
>
> With the topic branch, we can merge the basics to both right away, and
> continue with details in each branch separately.
Makes sense, thanks for explaining.
>
> BR,
> Jani.
>
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 04/11] drm/i915/adl_p: ADL_P device info enabling
2021-04-14 15:52 ` [Intel-gfx] [PATCH 04/11] drm/i915/adl_p: ADL_P device info enabling Imre Deak
@ 2021-05-05 23:54 ` Souza, Jose
0 siblings, 0 replies; 24+ messages in thread
From: Souza, Jose @ 2021-05-05 23:54 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Deak, Imre
On Wed, 2021-04-14 at 18:52 +0300, Imre Deak wrote:
> From: Clinton Taylor <Clinton.A.Taylor@intel.com>
>
> Add ADL-P to the device_info table and support MACROS.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Bspec: 49185, 55372, 55373
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> arch/x86/kernel/early-quirks.c | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++
> drivers/gpu/drm/i915/intel_device_info.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 5 files changed, 16 insertions(+)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index 6edd1e2ee8afa..b553ffe9b9851 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -552,6 +552,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
> INTEL_TGL_12_IDS(&gen11_early_ops),
> INTEL_RKL_IDS(&gen11_early_ops),
> INTEL_ADLS_IDS(&gen11_early_ops),
> + INTEL_ADLP_IDS(&gen11_early_ops),
> };
>
> struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e20294e9227a4..e5513e19beb5c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1392,6 +1392,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
> #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
> #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
> +#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> #define IS_BDW_ULT(dev_priv) \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 40b58a6dc3193..2384198e41f85 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -949,6 +949,17 @@ static const struct intel_device_info adl_s_info = {
> .ddb_size = 4096, \
> .num_supported_dbuf_slices = 4
>
> +static const struct intel_device_info adl_p_info = {
> + GEN12_FEATURES,
> + XE_LPD_FEATURES,
> + PLATFORM(INTEL_ALDERLAKE_P),
> + .require_force_probe = 1,
> + .platform_engine_mask =
> + BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> + .ppgtt_size = 48,
> + .dma_mask_size = 39,
> +};
> +
> #undef GEN
> #undef PLATFORM
>
> @@ -1026,6 +1037,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_TGL_12_IDS(&tgl_info),
> INTEL_RKL_IDS(&rkl_info),
> INTEL_ADLS_IDS(&adl_s_info),
> + INTEL_ADLP_IDS(&adl_p_info),
> {0, 0, 0}
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 6a351a7094174..3b975ce1ff591 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -67,6 +67,7 @@ static const char * const platform_names[] = {
> PLATFORM_NAME(ROCKETLAKE),
> PLATFORM_NAME(DG1),
> PLATFORM_NAME(ALDERLAKE_S),
> + PLATFORM_NAME(ALDERLAKE_P),
> };
> #undef PLATFORM_NAME
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 8ab4fa6c7fdd7..edf68244be2bc 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -87,6 +87,7 @@ enum intel_platform {
> INTEL_ROCKETLAKE,
> INTEL_DG1,
> INTEL_ALDERLAKE_S,
> + INTEL_ALDERLAKE_P,
> INTEL_MAX_PLATFORMS
> };
>
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 02/11] drm/i915/xelpd: add XE_LPD display characteristics
2021-04-14 15:51 ` [Intel-gfx] [PATCH 02/11] drm/i915/xelpd: add XE_LPD display characteristics Imre Deak
@ 2021-05-05 23:55 ` Souza, Jose
0 siblings, 0 replies; 24+ messages in thread
From: Souza, Jose @ 2021-05-05 23:55 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Deak, Imre
On Wed, 2021-04-14 at 18:51 +0300, Imre Deak wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
>
> Let's start preparing for upcoming platforms that will use an XE_LPD
> design.
>
> v2:
> - Use the now-preferred "XE_LPD" term to refer to this design
> - Utilize DISPLAY_VER() rather than a feature flag
> - Drop unused mbus_size field (Lucas)
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/i915_pci.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 44e7b94db63dc..40b58a6dc3193 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -939,6 +939,16 @@ static const struct intel_device_info adl_s_info = {
> .dma_mask_size = 46,
> };
>
> +#define XE_LPD_FEATURES \
> + .display.ver = 13, \
> + .display.has_psr_hw_tracking = 0, \
> + .abox_mask = GENMASK(1, 0), \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> + .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
> + .ddb_size = 4096, \
> + .num_supported_dbuf_slices = 4
> +
> #undef GEN
> #undef PLATFORM
>
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH 10/11] drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs
2021-04-15 22:12 ` Imre Deak
@ 2021-05-06 11:11 ` Kahola, Mika
0 siblings, 0 replies; 24+ messages in thread
From: Kahola, Mika @ 2021-05-06 11:11 UTC (permalink / raw)
To: Deak, Imre, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre
> Deak
> Sent: Friday, April 16, 2021 1:13 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 10/11] drm/i915/adl_p: Require a minimum of
> 8 tiles stride for DPT FBs
>
> On Wed, Apr 14, 2021 at 06:52:07PM +0300, Imre Deak wrote:
> > The specification only requires DPT FB strides to be POT aligned, but
> > there seems to be also a minimum of 8 stride tile requirement.
> > Scanning out FBs with < 8 stride tiles will result in pipe faults
> > (even though the stride is POT aligned).
>
> This is now confirmed in bspec (index 53393).
>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_fb.c | 6 +++++-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> > b/drivers/gpu/drm/i915/display/intel_fb.c
> > index bd862f77762a2..2ee10ece27c57 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -609,7 +609,11 @@ plane_view_dst_stride_tiles(const struct
> intel_framebuffer *fb, int color_plane,
> > unsigned int pitch_tiles)
> > {
> > if (intel_fb_needs_pot_stride_remap(fb))
> > - return roundup_pow_of_two(pitch_tiles);
> > + /*
> > + * ADL_P, the only platform needing a POT stride has a
> minimum
> > + * of 8 stride tiles.
> > + */
> > + return roundup_pow_of_two(max(pitch_tiles, 8u));
> > else
> > return pitch_tiles;
> > }
> > --
> > 2.27.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2021-05-06 11:11 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-14 15:51 [Intel-gfx] [PATCH 00/11] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
2021-04-14 15:51 ` [Intel-gfx] [PATCH 01/11] drm/i915: Pass intel_framebuffer instad of drm_framebuffer to intel_fill_fb_info() Imre Deak
2021-04-14 15:51 ` [Intel-gfx] [PATCH 02/11] drm/i915/xelpd: add XE_LPD display characteristics Imre Deak
2021-05-05 23:55 ` Souza, Jose
2021-04-14 15:52 ` [Intel-gfx] [PATCH 03/11] drm/i915/adl_p: Add PCI Devices IDs Imre Deak
2021-04-14 15:52 ` [Intel-gfx] [PATCH 04/11] drm/i915/adl_p: ADL_P device info enabling Imre Deak
2021-05-05 23:54 ` Souza, Jose
2021-04-14 15:52 ` [Intel-gfx] [PATCH 05/11] drm/i915/xelpd: First stab at DPT support Imre Deak
2021-04-14 15:52 ` [Intel-gfx] [PATCH 06/11] drm/i915/xelpd: Fallback to plane stride limitations when using DPT Imre Deak
2021-04-14 15:52 ` [Intel-gfx] [PATCH 07/11] drm/i915/xelpd: Support 128k plane stride Imre Deak
2021-04-14 15:52 ` [Intel-gfx] [PATCH 08/11] drm/i915/adl_p: Add stride restriction when using DPT Imre Deak
2021-04-14 15:52 ` [Intel-gfx] [PATCH 09/11] drm/i915/adl_p: Disable support for 90/270 FB rotation Imre Deak
2021-04-14 15:52 ` [Intel-gfx] [PATCH 10/11] drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs Imre Deak
2021-04-15 22:12 ` Imre Deak
2021-05-06 11:11 ` Kahola, Mika
2021-04-14 15:52 ` [Intel-gfx] [PATCH 11/11] drm/i915/adl_p: Enable remapping to pad DPT FB strides to POT Imre Deak
2021-04-14 17:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/adl_p: Add support for Display Page Tables Patchwork
2021-04-14 17:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-04-14 20:32 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-04-15 11:29 ` [Intel-gfx] [PATCH 00/11] " Jani Nikula
2021-04-21 11:03 ` Jani Nikula
2021-04-21 11:24 ` Imre Deak
2021-04-21 12:12 ` Jani Nikula
2021-04-21 19:21 ` Imre Deak
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