From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
To: linux-mm@kvack.org, akpm@linux-foundation.org
Cc: mpe@ellerman.id.au, linuxppc-dev@lists.ozlabs.org,
kaleshsingh@google.com, npiggin@gmail.com,
joel@joelfernandes.org,
Christophe Leroy <christophe.leroy@csgroup.eu>,
"Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Subject: [PATCH v5 6/9] mm/mremap: Use range flush that does TLB and page walk cache flush
Date: Thu, 22 Apr 2021 11:13:20 +0530 [thread overview]
Message-ID: <20210422054323.150993-7-aneesh.kumar@linux.ibm.com> (raw)
In-Reply-To: <20210422054323.150993-1-aneesh.kumar@linux.ibm.com>
Some architectures do have the concept of page walk cache which need
to be flush when updating higher levels of page tables. A fast mremap
that involves moving page table pages instead of copying pte entries
should flush page walk cache since the old translation cache is no more
valid.
Add new helper flush_pte_tlb_pwc_range() which invalidates both TLB and
page walk cache where TLB entries are mapped with page size PAGE_SIZE.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
arch/powerpc/include/asm/book3s/64/tlbflush.h | 10 ++++++++++
mm/mremap.c | 14 ++++++++++++--
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush.h b/arch/powerpc/include/asm/book3s/64/tlbflush.h
index f9f8a3a264f7..e84fee9db106 100644
--- a/arch/powerpc/include/asm/book3s/64/tlbflush.h
+++ b/arch/powerpc/include/asm/book3s/64/tlbflush.h
@@ -80,6 +80,16 @@ static inline void flush_hugetlb_tlb_range(struct vm_area_struct *vma,
return flush_hugetlb_tlb_pwc_range(vma, start, end, false);
}
+#define flush_pte_tlb_pwc_range flush_tlb_pwc_range
+static inline void flush_pte_tlb_pwc_range(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end)
+{
+ if (radix_enabled())
+ return radix__flush_tlb_pwc_range_psize(vma->vm_mm, start,
+ end, mmu_virtual_psize, true);
+ return hash__flush_tlb_range(vma, start, end);
+}
+
static inline void flush_tlb_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end)
{
diff --git a/mm/mremap.c b/mm/mremap.c
index 574287f9bb39..109560977944 100644
--- a/mm/mremap.c
+++ b/mm/mremap.c
@@ -210,6 +210,16 @@ static void move_ptes(struct vm_area_struct *vma, pmd_t *old_pmd,
drop_rmap_locks(vma);
}
+#ifndef flush_pte_tlb_pwc_range
+#define flush_pte_tlb_pwc_range flush_pte_tlb_pwc_range
+static inline void flush_pte_tlb_pwc_range(struct vm_area_struct *vma,
+ unsigned long start,
+ unsigned long end)
+{
+ return flush_tlb_range(vma, start, end);
+}
+#endif
+
#ifdef CONFIG_HAVE_MOVE_PMD
static bool move_normal_pmd(struct vm_area_struct *vma, unsigned long old_addr,
unsigned long new_addr, pmd_t *old_pmd, pmd_t *new_pmd)
@@ -260,7 +270,7 @@ static bool move_normal_pmd(struct vm_area_struct *vma, unsigned long old_addr,
VM_BUG_ON(!pmd_none(*new_pmd));
pmd_populate(mm, new_pmd, (pgtable_t)pmd_page_vaddr(pmd));
- flush_tlb_range(vma, old_addr, old_addr + PMD_SIZE);
+ flush_pte_tlb_pwc_range(vma, old_addr, old_addr + PMD_SIZE);
if (new_ptl != old_ptl)
spin_unlock(new_ptl);
spin_unlock(old_ptl);
@@ -307,7 +317,7 @@ static bool move_normal_pud(struct vm_area_struct *vma, unsigned long old_addr,
VM_BUG_ON(!pud_none(*new_pud));
pud_populate(mm, new_pud, (pmd_t *)pud_page_vaddr(pud));
- flush_tlb_range(vma, old_addr, old_addr + PUD_SIZE);
+ flush_pte_tlb_pwc_range(vma, old_addr, old_addr + PUD_SIZE);
if (new_ptl != old_ptl)
spin_unlock(new_ptl);
spin_unlock(old_ptl);
--
2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
To: linux-mm@kvack.org, akpm@linux-foundation.org
Cc: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>,
npiggin@gmail.com, kaleshsingh@google.com,
joel@joelfernandes.org, linuxppc-dev@lists.ozlabs.org
Subject: [PATCH v5 6/9] mm/mremap: Use range flush that does TLB and page walk cache flush
Date: Thu, 22 Apr 2021 11:13:20 +0530 [thread overview]
Message-ID: <20210422054323.150993-7-aneesh.kumar@linux.ibm.com> (raw)
In-Reply-To: <20210422054323.150993-1-aneesh.kumar@linux.ibm.com>
Some architectures do have the concept of page walk cache which need
to be flush when updating higher levels of page tables. A fast mremap
that involves moving page table pages instead of copying pte entries
should flush page walk cache since the old translation cache is no more
valid.
Add new helper flush_pte_tlb_pwc_range() which invalidates both TLB and
page walk cache where TLB entries are mapped with page size PAGE_SIZE.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
arch/powerpc/include/asm/book3s/64/tlbflush.h | 10 ++++++++++
mm/mremap.c | 14 ++++++++++++--
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush.h b/arch/powerpc/include/asm/book3s/64/tlbflush.h
index f9f8a3a264f7..e84fee9db106 100644
--- a/arch/powerpc/include/asm/book3s/64/tlbflush.h
+++ b/arch/powerpc/include/asm/book3s/64/tlbflush.h
@@ -80,6 +80,16 @@ static inline void flush_hugetlb_tlb_range(struct vm_area_struct *vma,
return flush_hugetlb_tlb_pwc_range(vma, start, end, false);
}
+#define flush_pte_tlb_pwc_range flush_tlb_pwc_range
+static inline void flush_pte_tlb_pwc_range(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end)
+{
+ if (radix_enabled())
+ return radix__flush_tlb_pwc_range_psize(vma->vm_mm, start,
+ end, mmu_virtual_psize, true);
+ return hash__flush_tlb_range(vma, start, end);
+}
+
static inline void flush_tlb_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end)
{
diff --git a/mm/mremap.c b/mm/mremap.c
index 574287f9bb39..109560977944 100644
--- a/mm/mremap.c
+++ b/mm/mremap.c
@@ -210,6 +210,16 @@ static void move_ptes(struct vm_area_struct *vma, pmd_t *old_pmd,
drop_rmap_locks(vma);
}
+#ifndef flush_pte_tlb_pwc_range
+#define flush_pte_tlb_pwc_range flush_pte_tlb_pwc_range
+static inline void flush_pte_tlb_pwc_range(struct vm_area_struct *vma,
+ unsigned long start,
+ unsigned long end)
+{
+ return flush_tlb_range(vma, start, end);
+}
+#endif
+
#ifdef CONFIG_HAVE_MOVE_PMD
static bool move_normal_pmd(struct vm_area_struct *vma, unsigned long old_addr,
unsigned long new_addr, pmd_t *old_pmd, pmd_t *new_pmd)
@@ -260,7 +270,7 @@ static bool move_normal_pmd(struct vm_area_struct *vma, unsigned long old_addr,
VM_BUG_ON(!pmd_none(*new_pmd));
pmd_populate(mm, new_pmd, (pgtable_t)pmd_page_vaddr(pmd));
- flush_tlb_range(vma, old_addr, old_addr + PMD_SIZE);
+ flush_pte_tlb_pwc_range(vma, old_addr, old_addr + PMD_SIZE);
if (new_ptl != old_ptl)
spin_unlock(new_ptl);
spin_unlock(old_ptl);
@@ -307,7 +317,7 @@ static bool move_normal_pud(struct vm_area_struct *vma, unsigned long old_addr,
VM_BUG_ON(!pud_none(*new_pud));
pud_populate(mm, new_pud, (pmd_t *)pud_page_vaddr(pud));
- flush_tlb_range(vma, old_addr, old_addr + PUD_SIZE);
+ flush_pte_tlb_pwc_range(vma, old_addr, old_addr + PUD_SIZE);
if (new_ptl != old_ptl)
spin_unlock(new_ptl);
spin_unlock(old_ptl);
--
2.30.2
next prev parent reply other threads:[~2021-04-22 5:44 UTC|newest]
Thread overview: 106+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-22 5:43 [PATCH v5 0/9] Speedup mremap on ppc64 Aneesh Kumar K.V
2021-04-22 5:43 ` Aneesh Kumar K.V
2021-04-22 5:43 ` [PATCH v5 1/9] selftest/mremap_test: Update the test to handle pagesize other than 4K Aneesh Kumar K.V
2021-04-22 5:43 ` Aneesh Kumar K.V
2021-04-22 5:43 ` [PATCH v5 2/9] selftest/mremap_test: Avoid crash with static build Aneesh Kumar K.V
2021-04-22 5:43 ` Aneesh Kumar K.V
2021-04-22 5:43 ` [PATCH v5 3/9] mm/mremap: Use pmd/pud_poplulate to update page table entries Aneesh Kumar K.V
2021-04-22 5:43 ` Aneesh Kumar K.V
2021-05-18 20:04 ` Nathan Chancellor
2021-05-18 20:04 ` Nathan Chancellor
2021-05-19 4:46 ` Aneesh Kumar K.V
2021-05-19 4:46 ` Aneesh Kumar K.V
2021-05-19 18:02 ` Nathan Chancellor
2021-05-19 18:02 ` Nathan Chancellor
2021-05-20 2:18 ` Peter Xu
2021-05-20 2:18 ` Peter Xu
2021-05-20 8:26 ` Aneesh Kumar K.V
2021-05-20 8:26 ` Aneesh Kumar K.V
2021-05-20 12:46 ` Peter Xu
2021-05-20 12:46 ` Peter Xu
2021-05-20 13:23 ` Aneesh Kumar K.V
2021-05-20 13:23 ` Aneesh Kumar K.V
2021-05-20 13:37 ` Aneesh Kumar K.V
2021-05-20 13:37 ` Aneesh Kumar K.V
2021-05-20 14:57 ` Peter Xu
2021-05-20 14:57 ` Peter Xu
2021-05-20 19:06 ` Zi Yan
2021-05-20 19:06 ` Zi Yan
2021-05-20 20:01 ` Peter Xu
2021-05-20 20:01 ` Peter Xu
2021-05-20 20:25 ` Kalesh Singh
2021-05-20 20:25 ` Kalesh Singh
2021-04-22 5:43 ` [PATCH v5 4/9] powerpc/mm/book3s64: Fix possible build error Aneesh Kumar K.V
2021-04-22 5:43 ` Aneesh Kumar K.V
2021-04-22 5:43 ` [PATCH v5 5/9] powerpc/mm/book3s64: Update tlb flush routines to take a page walk cache flush argument Aneesh Kumar K.V
2021-04-22 5:43 ` Aneesh Kumar K.V
2021-05-15 16:35 ` Guenter Roeck
2021-05-15 16:35 ` Guenter Roeck
2021-05-15 20:41 ` Andrew Morton
2021-05-15 20:41 ` Andrew Morton
2021-05-15 23:05 ` Guenter Roeck
2021-05-15 23:05 ` Guenter Roeck
2021-05-17 8:40 ` Aneesh Kumar K.V
2021-05-17 8:40 ` Aneesh Kumar K.V
2021-05-17 13:38 ` Guenter Roeck
2021-05-17 13:38 ` Guenter Roeck
2021-05-17 13:55 ` Aneesh Kumar K.V
2021-05-17 13:55 ` Aneesh Kumar K.V
2021-05-17 14:18 ` Guenter Roeck
2021-05-17 14:18 ` Guenter Roeck
2021-05-19 0:26 ` Michael Ellerman
2021-05-19 0:26 ` Michael Ellerman
2021-05-19 0:45 ` Segher Boessenkool
2021-05-19 0:45 ` Segher Boessenkool
2021-05-19 12:03 ` Segher Boessenkool
2021-05-19 13:37 ` Guenter Roeck
2021-05-19 14:20 ` Segher Boessenkool
2021-05-19 14:20 ` Segher Boessenkool
2021-05-19 15:28 ` Guenter Roeck
2021-05-19 15:28 ` Guenter Roeck
2021-05-20 7:37 ` Michael Ellerman
2021-05-20 12:17 ` Segher Boessenkool
2021-05-19 1:08 ` Guenter Roeck
2021-05-19 1:08 ` Guenter Roeck
2021-05-20 11:38 ` Michael Ellerman
2021-05-20 11:38 ` Michael Ellerman
2021-05-20 11:56 ` Guenter Roeck
2021-05-20 11:56 ` Guenter Roeck
2021-04-22 5:43 ` Aneesh Kumar K.V [this message]
2021-04-22 5:43 ` [PATCH v5 6/9] mm/mremap: Use range flush that does TLB and page walk cache flush Aneesh Kumar K.V
2021-04-22 5:43 ` [PATCH v5 7/9] mm/mremap: Move TLB flush outside page table lock Aneesh Kumar K.V
2021-04-22 5:43 ` Aneesh Kumar K.V
2021-05-20 15:26 ` Aneesh Kumar K.V
2021-05-20 15:26 ` Aneesh Kumar K.V
2021-05-20 16:57 ` Aneesh Kumar K.V
2021-05-20 16:57 ` Aneesh Kumar K.V
2021-05-21 2:40 ` Linus Torvalds
2021-05-21 2:40 ` Linus Torvalds
2021-05-21 3:03 ` Aneesh Kumar K.V
2021-05-21 3:03 ` Aneesh Kumar K.V
2021-05-21 3:28 ` Aneesh Kumar K.V
2021-05-21 3:28 ` Aneesh Kumar K.V
2021-05-21 6:13 ` Linus Torvalds
2021-05-21 6:13 ` Linus Torvalds
2021-05-21 12:50 ` Aneesh Kumar K.V
2021-05-21 12:50 ` Aneesh Kumar K.V
2021-05-21 13:03 ` Aneesh Kumar K.V
2021-05-21 13:03 ` Aneesh Kumar K.V
2021-05-21 16:03 ` Linus Torvalds
2021-05-21 16:03 ` Linus Torvalds
2021-05-21 16:29 ` Aneesh Kumar K.V
2021-05-21 16:29 ` Aneesh Kumar K.V
2021-05-24 14:24 ` Aneesh Kumar K.V
2021-05-24 14:24 ` Aneesh Kumar K.V
2021-05-21 15:24 ` Liam Howlett
2021-05-21 15:24 ` Liam Howlett
2021-05-21 16:02 ` Aneesh Kumar K.V
2021-05-21 16:02 ` Aneesh Kumar K.V
2021-05-21 16:05 ` Linus Torvalds
2021-05-21 16:05 ` Linus Torvalds
2021-04-22 5:43 ` [PATCH v5 8/9] mm/mremap: Allow arch runtime override Aneesh Kumar K.V
2021-04-22 5:43 ` Aneesh Kumar K.V
2021-04-22 5:43 ` [PATCH v5 9/9] powerpc/mm: Enable move pmd/pud Aneesh Kumar K.V
2021-04-22 5:43 ` Aneesh Kumar K.V
2021-05-11 22:19 ` Andrew Morton
2021-05-11 22:19 ` Andrew Morton
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