From: Sean Anderson <seanga2@gmail.com>
To: u-boot@lists.denx.de
Cc: Damien Le Moal <Damien.LeMoal@wdc.com>,
Leo Liang <ycliang@andestech.com>,
Lukasz Majewski <lukma@denx.de>,
Sean Anderson <seanga2@gmail.com>
Subject: [PATCH v3 09/11] k210: dts: Set PLL1 to the same rate as PLL0
Date: Fri, 11 Jun 2021 00:16:15 -0400 [thread overview]
Message-ID: <20210611041617.1665833-10-seanga2@gmail.com> (raw)
In-Reply-To: <20210611041617.1665833-1-seanga2@gmail.com>
Linux has had some stability issues when using AISRAM with a different
frequency from SRAM. Mirror their change here now that we relocate into
AISRAM.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
---
Changes in v3:
- Add CLK_K210_SET_RATE to defconfig so these changes apply
arch/riscv/dts/k210.dtsi | 2 ++
configs/sipeed_maix_bitm_defconfig | 1 +
2 files changed, 3 insertions(+)
diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
index 2492af8038..8bcd3cebde 100644
--- a/arch/riscv/dts/k210.dtsi
+++ b/arch/riscv/dts/k210.dtsi
@@ -501,6 +501,8 @@
#clock-cells = <1>;
compatible = "kendryte,k210-clk";
clocks = <&in0>;
+ assigned-clocks = <&sysclk K210_CLK_PLL1>;
+ assigned-clock-rates = <390000000>;
u-boot,dm-pre-reloc;
};
diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig
index bd877cd055..6a06f650ea 100644
--- a/configs/sipeed_maix_bitm_defconfig
+++ b/configs/sipeed_maix_bitm_defconfig
@@ -13,6 +13,7 @@ CONFIG_HUSH_PARSER=y
CONFIG_MTDIDS_DEFAULT="nor0=spi3:0"
CONFIG_MTDPARTS_DEFAULT="nor0:1M(u-boot),0x1000@0xfff000(env)"
# CONFIG_NET is not set
+CONFIG_CLK_K210_SET_RATE=y
# CONFIG_INPUT is not set
CONFIG_SF_DEFAULT_BUS=3
# CONFIG_DM_ETH is not set
--
2.31.0
next prev parent reply other threads:[~2021-06-11 4:18 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-11 4:16 [PATCH v3 00/11] clk: k210: Rewrite K210 clock without CCF Sean Anderson
2021-06-11 4:16 ` [PATCH v3 01/11] clk: Allow force setting clock defaults before relocation Sean Anderson
2021-06-11 4:16 ` [PATCH v3 02/11] clk: k210: Rewrite to remove CCF Sean Anderson
2021-06-16 1:54 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 03/11] clk: k210: Move pll into the rest of the driver Sean Anderson
2021-06-16 1:55 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 04/11] clk: k210: Implement soc_clk_dump Sean Anderson
2021-06-16 1:56 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 05/11] clk: k210: Re-add support for setting rate Sean Anderson
2021-06-16 1:57 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 06/11] clk: k210: Don't set PLL rates if we are already at the correct rate Sean Anderson
2021-06-16 1:58 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 07/11] clk: k210: Remove bypass driver Sean Anderson
2021-06-16 1:59 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 08/11] clk: k210: Move k210 clock out of its own subdirectory Sean Anderson
2021-06-16 2:01 ` Leo Liang
2021-06-11 4:16 ` Sean Anderson [this message]
2021-06-16 2:01 ` [PATCH v3 09/11] k210: dts: Set PLL1 to the same rate as PLL0 Leo Liang
2021-06-11 4:16 ` [PATCH v3 10/11] k210: Don't imply CCF Sean Anderson
2021-06-16 2:02 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 11/11] test: Add K210 PLL tests to sandbox defconfigs Sean Anderson
2021-06-11 8:21 ` [PATCH v3 00/11] clk: k210: Rewrite K210 clock without CCF Lukasz Majewski
2021-06-11 13:57 ` Sean Anderson
2021-06-13 23:08 ` Damien Le Moal
2021-06-11 23:14 ` Sean Anderson
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