From: Sean Anderson <seanga2@gmail.com>
To: u-boot@lists.denx.de
Cc: Damien Le Moal <Damien.LeMoal@wdc.com>,
Leo Liang <ycliang@andestech.com>,
Lukasz Majewski <lukma@denx.de>,
Sean Anderson <seanga2@gmail.com>
Subject: [PATCH v3 06/11] clk: k210: Don't set PLL rates if we are already at the correct rate
Date: Fri, 11 Jun 2021 00:16:12 -0400 [thread overview]
Message-ID: <20210611041617.1665833-7-seanga2@gmail.com> (raw)
In-Reply-To: <20210611041617.1665833-1-seanga2@gmail.com>
This speeds up boot by preventing multiple reconfigurations of the PLLs.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
---
(no changes since v1)
drivers/clk/kendryte/clk.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
index a2901f9b96..3148756968 100644
--- a/drivers/clk/kendryte/clk.c
+++ b/drivers/clk/kendryte/clk.c
@@ -847,21 +847,22 @@ static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate,
const struct k210_pll_params *pll = &k210_plls[id];
struct k210_pll_config config = {};
u32 reg;
+ ulong calc_rate;
if (rate_in < 0)
return rate_in;
- log_debug("Calculating parameters with rate=%lu and rate_in=%lu\n",
- rate, rate_in);
err = k210_pll_calc_config(rate, rate_in, &config);
if (err)
return err;
log_debug("Got r=%u f=%u od=%u\n", config.r, config.f, config.od);
- /*
- * Don't use clk_disable as it might not actually disable the pll due to
- * refcounting
- */
+ /* Don't bother setting the rate if we're already at that rate */
+ calc_rate = DIV_ROUND_DOWN_ULL(((u64)rate_in) * config.f,
+ config.r * config.od);
+ if (calc_rate == k210_pll_get_rate(priv, id, rate))
+ return calc_rate;
+
k210_pll_disable(priv, id);
reg = readl(priv->base + pll->off);
@@ -875,7 +876,7 @@ static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate,
| FIELD_PREP(K210_PLL_BWADJ, config.f - 1);
writel(reg, priv->base + pll->off);
- err = k210_pll_enable(priv, id);
+ k210_pll_enable(priv, id);
serial_setbrg();
return k210_pll_get_rate(priv, id, rate);
--
2.31.0
next prev parent reply other threads:[~2021-06-11 4:17 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-11 4:16 [PATCH v3 00/11] clk: k210: Rewrite K210 clock without CCF Sean Anderson
2021-06-11 4:16 ` [PATCH v3 01/11] clk: Allow force setting clock defaults before relocation Sean Anderson
2021-06-11 4:16 ` [PATCH v3 02/11] clk: k210: Rewrite to remove CCF Sean Anderson
2021-06-16 1:54 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 03/11] clk: k210: Move pll into the rest of the driver Sean Anderson
2021-06-16 1:55 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 04/11] clk: k210: Implement soc_clk_dump Sean Anderson
2021-06-16 1:56 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 05/11] clk: k210: Re-add support for setting rate Sean Anderson
2021-06-16 1:57 ` Leo Liang
2021-06-11 4:16 ` Sean Anderson [this message]
2021-06-16 1:58 ` [PATCH v3 06/11] clk: k210: Don't set PLL rates if we are already at the correct rate Leo Liang
2021-06-11 4:16 ` [PATCH v3 07/11] clk: k210: Remove bypass driver Sean Anderson
2021-06-16 1:59 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 08/11] clk: k210: Move k210 clock out of its own subdirectory Sean Anderson
2021-06-16 2:01 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 09/11] k210: dts: Set PLL1 to the same rate as PLL0 Sean Anderson
2021-06-16 2:01 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 10/11] k210: Don't imply CCF Sean Anderson
2021-06-16 2:02 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 11/11] test: Add K210 PLL tests to sandbox defconfigs Sean Anderson
2021-06-11 8:21 ` [PATCH v3 00/11] clk: k210: Rewrite K210 clock without CCF Lukasz Majewski
2021-06-11 13:57 ` Sean Anderson
2021-06-13 23:08 ` Damien Le Moal
2021-06-11 23:14 ` Sean Anderson
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