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From: Aswath Govindraju <a-govindraju@ti.com>
To: unlisted-recipients:; (no To-header on input)
Cc: Vignesh Raghavendra <vigneshr@ti.com>, Suman Anna <s-anna@ti.com>,
	Lokesh Vutla <lokeshvutla@ti.com>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Aswath Govindraju <a-govindraju@ti.com>,
	Nishanth Menon <nm@ti.com>, Tero Kristo <kristo@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v4 2/3] arm64: dts: ti: k3-am64-main: Reserve OCMRAM for DMSC-lite and secure proxy communication
Date: Tue, 15 Jun 2021 23:13:24 +0530	[thread overview]
Message-ID: <20210615174325.22853-3-a-govindraju@ti.com> (raw)
In-Reply-To: <20210615174325.22853-1-a-govindraju@ti.com>

The final 128KB in SRAM is reserved by default for DMSC-lite code and
secure proxy communication buffer. The memory region used for DMSC-lite
code can be optionally freed up by secure firmware API[1]. However, the
buffer for secure proxy communication is not configurable. This default
hardware configuration is unique for AM64.

Therefore, indicate the area reserved for DMSC-lite code and secure proxy
communication buffer in the oc_sram device tree node.

[1] - http://downloads.ti.com/tisci/esd/latest/6_topic_user_guides/security_handover.html#triggering-security-handover

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 693fe24e7f7a..6a883f4349cb 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -27,6 +27,14 @@
 		tfa-sram@0 {
 			reg = <0x0 0x1c000>;
 		};
+
+		dmsc-sram@1e0000 {
+			reg = <0x1e0000 0x1c000>;
+		};
+
+		sproxy-sram@1fc000 {
+			reg = <0x1fc000 0x4000>;
+		};
 	};
 
 	main_conf: syscon@43000000 {
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Aswath Govindraju <a-govindraju@ti.com>
Cc: Nishanth Menon <nm@ti.com>,
	devicetree@vger.kernel.org, Vignesh Raghavendra <vigneshr@ti.com>,
	Tero Kristo <kristo@kernel.org>,
	Lokesh Vutla <lokeshvutla@ti.com>,
	linux-kernel@vger.kernel.org,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Rob Herring <robh+dt@kernel.org>,
	Aswath Govindraju <a-govindraju@ti.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 2/3] arm64: dts: ti: k3-am64-main: Reserve OCMRAM for DMSC-lite and secure proxy communication
Date: Tue, 15 Jun 2021 23:13:24 +0530	[thread overview]
Message-ID: <20210615174325.22853-3-a-govindraju@ti.com> (raw)
In-Reply-To: <20210615174325.22853-1-a-govindraju@ti.com>

The final 128KB in SRAM is reserved by default for DMSC-lite code and
secure proxy communication buffer. The memory region used for DMSC-lite
code can be optionally freed up by secure firmware API[1]. However, the
buffer for secure proxy communication is not configurable. This default
hardware configuration is unique for AM64.

Therefore, indicate the area reserved for DMSC-lite code and secure proxy
communication buffer in the oc_sram device tree node.

[1] - http://downloads.ti.com/tisci/esd/latest/6_topic_user_guides/security_handover.html#triggering-security-handover

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 693fe24e7f7a..6a883f4349cb 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -27,6 +27,14 @@
 		tfa-sram@0 {
 			reg = <0x0 0x1c000>;
 		};
+
+		dmsc-sram@1e0000 {
+			reg = <0x1e0000 0x1c000>;
+		};
+
+		sproxy-sram@1fc000 {
+			reg = <0x1fc000 0x4000>;
+		};
 	};
 
 	main_conf: syscon@43000000 {
-- 
2.17.1


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  parent reply	other threads:[~2021-06-15 17:43 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-15 17:43 [PATCH v4 0/3] AM64: Update the locations of various elements in SRAM Aswath Govindraju
2021-06-15 17:43 ` Aswath Govindraju
2021-06-15 17:43 ` [PATCH v4 1/3] arm64: dts: ti: k3-am64-main: Update TF-A's maximum size and node name Aswath Govindraju
2021-06-15 17:43   ` Aswath Govindraju
2021-06-16  0:19   ` Nishanth Menon
2021-06-16  0:19     ` Nishanth Menon
2021-06-15 17:43 ` Aswath Govindraju [this message]
2021-06-15 17:43   ` [PATCH v4 2/3] arm64: dts: ti: k3-am64-main: Reserve OCMRAM for DMSC-lite and secure proxy communication Aswath Govindraju
2021-06-15 18:48   ` Suman Anna
2021-06-15 18:48     ` Suman Anna
2021-06-15 17:43 ` [PATCH v4 3/3] arm64: dts: ti: k3-am64-main: Update the location of TF-A Aswath Govindraju
2021-06-15 17:43   ` Aswath Govindraju
2021-06-15 18:48   ` Suman Anna
2021-06-15 18:48     ` Suman Anna
2021-06-16  0:20   ` Nishanth Menon
2021-06-16  0:20     ` Nishanth Menon
2021-06-16  8:43     ` Aswath Govindraju
2021-06-16  8:43       ` Aswath Govindraju
2021-06-15 18:49 ` [PATCH v4 0/3] AM64: Update the locations of various elements in SRAM Suman Anna
2021-06-15 18:49   ` Suman Anna

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