From: Hamza Mahfooz <hamza.mahfooz@amd.com>
To: <linux-kernel@vger.kernel.org>
Cc: "Harry Wentland" <harry.wentland@amd.com>,
"Fangzhi Zuo" <Jerry.Zuo@amd.com>,
"Wayne Lin" <Wayne.Lin@amd.com>,
"Aurabindo Pillai" <aurabindo.pillai@amd.com>,
hersenxs.wu@amd.com, "Hamza Mahfooz" <hamza.mahfooz@amd.com>,
"Leo Li" <sunpeng.li@amd.com>,
"Rodrigo Siqueira" <Rodrigo.Siqueira@amd.com>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Pan, Xinhui" <Xinhui.Pan@amd.com>,
"David Airlie" <airlied@linux.ie>,
"Daniel Vetter" <daniel@ffwll.ch>,
"Lyude Paul" <lyude@redhat.com>,
"Mikita Lipski" <mikita.lipski@amd.com>,
"Claudio Suarez" <cssk@net-c.es>,
"Bhawanpreet Lakha" <Bhawanpreet.Lakha@amd.com>,
"Roman Li" <Roman.Li@amd.com>, "Ian Chen" <ian.chen@amd.com>,
"Colin Ian King" <colin.king@intel.com>,
"Nicholas Kazlauskas" <nicholas.kazlauskas@amd.com>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"Jani Nikula" <jani.nikula@intel.com>,
"Imran Khan" <imran.f.khan@oracle.com>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Kees Cook" <keescook@chromium.org>,
"Imre Deak" <imre.deak@intel.com>,
"Sankeerth Billakanti" <quic_sbillaka@quicinc.com>,
"Javier Martinez Canillas" <javierm@redhat.com>,
amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: [PATCH v2 2/3] drm/amd/display: consider DSC pass-through during mode validation
Date: Fri, 5 Aug 2022 17:13:04 -0400 [thread overview]
Message-ID: <20220805211317.176672-2-hamza.mahfooz@amd.com> (raw)
In-Reply-To: <20220805211317.176672-1-hamza.mahfooz@amd.com>
Add a mode validation routine for DSC pass-through. Both the link from
source to hub, and the link from hub to monitor are checked, according
to the current link training result and full pbn returned by enum path
resource sideband message.
Pick up the minimum value as the bandwidth bottleneck for the end to
end link bandwidth constraint, and check if the maximum DSC decompression
bandwidth can fit.
Co-authored-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
v2: use multi-line comments, use a temp variable in kbps_from_pbn() and
add a debug print statement in dm_dp_mst_is_port_support_mode().
---
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 79 +++++++++++++++++--
1 file changed, 74 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 2e74ccf7df5b..ef6c94cd852b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -36,6 +36,7 @@
#include "dm_helpers.h"
#include "dc_link_ddc.h"
+#include "dc_link_dp.h"
#include "ddc_service_types.h"
#include "dpcd_defs.h"
@@ -1388,17 +1389,85 @@ bool pre_validate_dsc(struct drm_atomic_state *state,
#endif
+static unsigned int kbps_from_pbn(unsigned int pbn)
+{
+ unsigned int kbps = pbn;
+
+ kbps *= (1000000 / PEAK_FACTOR_X1000);
+ kbps *= 8;
+ kbps *= 54;
+ kbps /= 64;
+
+ return kbps;
+}
+
+static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
+ struct dc_dsc_bw_range *bw_range)
+{
+ struct dc_dsc_policy dsc_policy = {0};
+
+ dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy);
+ dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],
+ stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
+ dsc_policy.min_target_bpp * 16,
+ dsc_policy.max_target_bpp * 16,
+ &stream->sink->dsc_caps.dsc_dec_caps,
+ &stream->timing, bw_range);
+
+ return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16;
+}
+
enum dc_status dm_dp_mst_is_port_support_mode(
struct amdgpu_dm_connector *aconnector,
struct dc_stream_state *stream)
{
+ struct dc_link_settings cur_link_settings;
+ unsigned int end_to_end_bw_in_kbps = 0;
+ unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0;
+ unsigned int max_compressed_bw_in_kbps = 0;
+ struct dc_dsc_bw_range bw_range = {0};
int bpp, pbn, branch_max_throughput_mps = 0;
- /* check if mode could be supported within fUll_pbn */
- bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
- pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
- if (pbn > aconnector->port->full_pbn)
- return DC_FAIL_BANDWIDTH_VALIDATE;
+ /*
+ * check if the mode could be supported if DSC pass-through is supported
+ * AND check if there enough bandwidth available to support the mode
+ * with DSC enabled.
+ */
+ if (is_dsc_common_config_possible(stream, &bw_range) &&
+ aconnector->port->passthrough_aux) {
+ mutex_lock(&aconnector->mst_mgr.lock);
+
+ cur_link_settings = stream->link->verified_link_cap;
+
+ upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
+ &cur_link_settings
+ );
+ down_link_bw_in_kbps = kbps_from_pbn(aconnector->port->full_pbn);
+
+ /* pick the bottleneck */
+ end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps,
+ down_link_bw_in_kbps);
+
+ mutex_unlock(&aconnector->mst_mgr.lock);
+
+ /*
+ * use the maximum dsc compression bandwidth as the required
+ * bandwidth for the mode
+ */
+ max_compressed_bw_in_kbps = bw_range.min_kbps;
+
+ if (end_to_end_bw_in_kbps < max_compressed_bw_in_kbps) {
+ DRM_DEBUG_DRIVER("Mode does not fit into DSC pass-through bandwidth validation\n");
+ return DC_FAIL_BANDWIDTH_VALIDATE;
+ }
+ } else {
+ /* check if mode could be supported within full_pbn */
+ bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
+ pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
+
+ if (pbn > aconnector->port->full_pbn)
+ return DC_FAIL_BANDWIDTH_VALIDATE;
+ }
/* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
switch (stream->timing.pixel_encoding) {
--
2.37.1
WARNING: multiple messages have this Message-ID (diff)
From: Hamza Mahfooz <hamza.mahfooz@amd.com>
To: <linux-kernel@vger.kernel.org>
Cc: "Ian Chen" <ian.chen@amd.com>,
"Sankeerth Billakanti" <quic_sbillaka@quicinc.com>,
"David Airlie" <airlied@linux.ie>,
dri-devel@lists.freedesktop.org,
"Hamza Mahfooz" <hamza.mahfooz@amd.com>,
"Imran Khan" <imran.f.khan@oracle.com>,
"Kees Cook" <keescook@chromium.org>,
"Rodrigo Siqueira" <Rodrigo.Siqueira@amd.com>,
"Javier Martinez Canillas" <javierm@redhat.com>,
amd-gfx@lists.freedesktop.org,
"Jani Nikula" <jani.nikula@intel.com>,
"Fangzhi Zuo" <Jerry.Zuo@amd.com>,
"Aurabindo Pillai" <aurabindo.pillai@amd.com>,
"Leo Li" <sunpeng.li@amd.com>,
hersenxs.wu@amd.com, "Mikita Lipski" <mikita.lipski@amd.com>,
"Bhawanpreet Lakha" <Bhawanpreet.Lakha@amd.com>,
"Pan, Xinhui" <Xinhui.Pan@amd.com>, "Roman Li" <Roman.Li@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Claudio Suarez" <cssk@net-c.es>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"Wayne Lin" <Wayne.Lin@amd.com>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Colin Ian King" <colin.king@intel.com>,
"Nicholas Kazlauskas" <nicholas.kazlauskas@amd.com>
Subject: [PATCH v2 2/3] drm/amd/display: consider DSC pass-through during mode validation
Date: Fri, 5 Aug 2022 17:13:04 -0400 [thread overview]
Message-ID: <20220805211317.176672-2-hamza.mahfooz@amd.com> (raw)
In-Reply-To: <20220805211317.176672-1-hamza.mahfooz@amd.com>
Add a mode validation routine for DSC pass-through. Both the link from
source to hub, and the link from hub to monitor are checked, according
to the current link training result and full pbn returned by enum path
resource sideband message.
Pick up the minimum value as the bandwidth bottleneck for the end to
end link bandwidth constraint, and check if the maximum DSC decompression
bandwidth can fit.
Co-authored-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
v2: use multi-line comments, use a temp variable in kbps_from_pbn() and
add a debug print statement in dm_dp_mst_is_port_support_mode().
---
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 79 +++++++++++++++++--
1 file changed, 74 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 2e74ccf7df5b..ef6c94cd852b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -36,6 +36,7 @@
#include "dm_helpers.h"
#include "dc_link_ddc.h"
+#include "dc_link_dp.h"
#include "ddc_service_types.h"
#include "dpcd_defs.h"
@@ -1388,17 +1389,85 @@ bool pre_validate_dsc(struct drm_atomic_state *state,
#endif
+static unsigned int kbps_from_pbn(unsigned int pbn)
+{
+ unsigned int kbps = pbn;
+
+ kbps *= (1000000 / PEAK_FACTOR_X1000);
+ kbps *= 8;
+ kbps *= 54;
+ kbps /= 64;
+
+ return kbps;
+}
+
+static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
+ struct dc_dsc_bw_range *bw_range)
+{
+ struct dc_dsc_policy dsc_policy = {0};
+
+ dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy);
+ dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],
+ stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
+ dsc_policy.min_target_bpp * 16,
+ dsc_policy.max_target_bpp * 16,
+ &stream->sink->dsc_caps.dsc_dec_caps,
+ &stream->timing, bw_range);
+
+ return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16;
+}
+
enum dc_status dm_dp_mst_is_port_support_mode(
struct amdgpu_dm_connector *aconnector,
struct dc_stream_state *stream)
{
+ struct dc_link_settings cur_link_settings;
+ unsigned int end_to_end_bw_in_kbps = 0;
+ unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0;
+ unsigned int max_compressed_bw_in_kbps = 0;
+ struct dc_dsc_bw_range bw_range = {0};
int bpp, pbn, branch_max_throughput_mps = 0;
- /* check if mode could be supported within fUll_pbn */
- bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
- pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
- if (pbn > aconnector->port->full_pbn)
- return DC_FAIL_BANDWIDTH_VALIDATE;
+ /*
+ * check if the mode could be supported if DSC pass-through is supported
+ * AND check if there enough bandwidth available to support the mode
+ * with DSC enabled.
+ */
+ if (is_dsc_common_config_possible(stream, &bw_range) &&
+ aconnector->port->passthrough_aux) {
+ mutex_lock(&aconnector->mst_mgr.lock);
+
+ cur_link_settings = stream->link->verified_link_cap;
+
+ upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
+ &cur_link_settings
+ );
+ down_link_bw_in_kbps = kbps_from_pbn(aconnector->port->full_pbn);
+
+ /* pick the bottleneck */
+ end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps,
+ down_link_bw_in_kbps);
+
+ mutex_unlock(&aconnector->mst_mgr.lock);
+
+ /*
+ * use the maximum dsc compression bandwidth as the required
+ * bandwidth for the mode
+ */
+ max_compressed_bw_in_kbps = bw_range.min_kbps;
+
+ if (end_to_end_bw_in_kbps < max_compressed_bw_in_kbps) {
+ DRM_DEBUG_DRIVER("Mode does not fit into DSC pass-through bandwidth validation\n");
+ return DC_FAIL_BANDWIDTH_VALIDATE;
+ }
+ } else {
+ /* check if mode could be supported within full_pbn */
+ bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
+ pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
+
+ if (pbn > aconnector->port->full_pbn)
+ return DC_FAIL_BANDWIDTH_VALIDATE;
+ }
/* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
switch (stream->timing.pixel_encoding) {
--
2.37.1
WARNING: multiple messages have this Message-ID (diff)
From: Hamza Mahfooz <hamza.mahfooz@amd.com>
To: <linux-kernel@vger.kernel.org>
Cc: "Ian Chen" <ian.chen@amd.com>,
"Sankeerth Billakanti" <quic_sbillaka@quicinc.com>,
"David Airlie" <airlied@linux.ie>,
"Imre Deak" <imre.deak@intel.com>,
dri-devel@lists.freedesktop.org,
"Hamza Mahfooz" <hamza.mahfooz@amd.com>,
"Imran Khan" <imran.f.khan@oracle.com>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Kees Cook" <keescook@chromium.org>,
"Rodrigo Siqueira" <Rodrigo.Siqueira@amd.com>,
"Javier Martinez Canillas" <javierm@redhat.com>,
amd-gfx@lists.freedesktop.org,
"Jani Nikula" <jani.nikula@intel.com>,
"Fangzhi Zuo" <Jerry.Zuo@amd.com>,
"Aurabindo Pillai" <aurabindo.pillai@amd.com>,
"Harry Wentland" <harry.wentland@amd.com>,
"Daniel Vetter" <daniel@ffwll.ch>, "Leo Li" <sunpeng.li@amd.com>,
hersenxs.wu@amd.com, "Mikita Lipski" <mikita.lipski@amd.com>,
"Bhawanpreet Lakha" <Bhawanpreet.Lakha@amd.com>,
"Pan, Xinhui" <Xinhui.Pan@amd.com>, "Roman Li" <Roman.Li@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Claudio Suarez" <cssk@net-c.es>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"Wayne Lin" <Wayne.Lin@amd.com>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Colin Ian King" <colin.king@intel.com>,
"Nicholas Kazlauskas" <nicholas.kazlauskas@amd.com>
Subject: [PATCH v2 2/3] drm/amd/display: consider DSC pass-through during mode validation
Date: Fri, 5 Aug 2022 17:13:04 -0400 [thread overview]
Message-ID: <20220805211317.176672-2-hamza.mahfooz@amd.com> (raw)
In-Reply-To: <20220805211317.176672-1-hamza.mahfooz@amd.com>
Add a mode validation routine for DSC pass-through. Both the link from
source to hub, and the link from hub to monitor are checked, according
to the current link training result and full pbn returned by enum path
resource sideband message.
Pick up the minimum value as the bandwidth bottleneck for the end to
end link bandwidth constraint, and check if the maximum DSC decompression
bandwidth can fit.
Co-authored-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
v2: use multi-line comments, use a temp variable in kbps_from_pbn() and
add a debug print statement in dm_dp_mst_is_port_support_mode().
---
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 79 +++++++++++++++++--
1 file changed, 74 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 2e74ccf7df5b..ef6c94cd852b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -36,6 +36,7 @@
#include "dm_helpers.h"
#include "dc_link_ddc.h"
+#include "dc_link_dp.h"
#include "ddc_service_types.h"
#include "dpcd_defs.h"
@@ -1388,17 +1389,85 @@ bool pre_validate_dsc(struct drm_atomic_state *state,
#endif
+static unsigned int kbps_from_pbn(unsigned int pbn)
+{
+ unsigned int kbps = pbn;
+
+ kbps *= (1000000 / PEAK_FACTOR_X1000);
+ kbps *= 8;
+ kbps *= 54;
+ kbps /= 64;
+
+ return kbps;
+}
+
+static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
+ struct dc_dsc_bw_range *bw_range)
+{
+ struct dc_dsc_policy dsc_policy = {0};
+
+ dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy);
+ dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],
+ stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
+ dsc_policy.min_target_bpp * 16,
+ dsc_policy.max_target_bpp * 16,
+ &stream->sink->dsc_caps.dsc_dec_caps,
+ &stream->timing, bw_range);
+
+ return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16;
+}
+
enum dc_status dm_dp_mst_is_port_support_mode(
struct amdgpu_dm_connector *aconnector,
struct dc_stream_state *stream)
{
+ struct dc_link_settings cur_link_settings;
+ unsigned int end_to_end_bw_in_kbps = 0;
+ unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0;
+ unsigned int max_compressed_bw_in_kbps = 0;
+ struct dc_dsc_bw_range bw_range = {0};
int bpp, pbn, branch_max_throughput_mps = 0;
- /* check if mode could be supported within fUll_pbn */
- bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
- pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
- if (pbn > aconnector->port->full_pbn)
- return DC_FAIL_BANDWIDTH_VALIDATE;
+ /*
+ * check if the mode could be supported if DSC pass-through is supported
+ * AND check if there enough bandwidth available to support the mode
+ * with DSC enabled.
+ */
+ if (is_dsc_common_config_possible(stream, &bw_range) &&
+ aconnector->port->passthrough_aux) {
+ mutex_lock(&aconnector->mst_mgr.lock);
+
+ cur_link_settings = stream->link->verified_link_cap;
+
+ upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
+ &cur_link_settings
+ );
+ down_link_bw_in_kbps = kbps_from_pbn(aconnector->port->full_pbn);
+
+ /* pick the bottleneck */
+ end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps,
+ down_link_bw_in_kbps);
+
+ mutex_unlock(&aconnector->mst_mgr.lock);
+
+ /*
+ * use the maximum dsc compression bandwidth as the required
+ * bandwidth for the mode
+ */
+ max_compressed_bw_in_kbps = bw_range.min_kbps;
+
+ if (end_to_end_bw_in_kbps < max_compressed_bw_in_kbps) {
+ DRM_DEBUG_DRIVER("Mode does not fit into DSC pass-through bandwidth validation\n");
+ return DC_FAIL_BANDWIDTH_VALIDATE;
+ }
+ } else {
+ /* check if mode could be supported within full_pbn */
+ bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
+ pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
+
+ if (pbn > aconnector->port->full_pbn)
+ return DC_FAIL_BANDWIDTH_VALIDATE;
+ }
/* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
switch (stream->timing.pixel_encoding) {
--
2.37.1
next prev parent reply other threads:[~2022-08-05 21:13 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-05 21:13 [PATCH v2 1/3] drm/dp_mst: add passthrough_aux to struct drm_dp_mst_port Hamza Mahfooz
2022-08-05 21:13 ` Hamza Mahfooz
2022-08-05 21:13 ` Hamza Mahfooz
2022-08-05 21:13 ` Hamza Mahfooz [this message]
2022-08-05 21:13 ` [PATCH v2 2/3] drm/amd/display: consider DSC pass-through during mode validation Hamza Mahfooz
2022-08-05 21:13 ` Hamza Mahfooz
2022-08-11 11:02 ` Anders Roxell
2022-08-11 11:02 ` Anders Roxell
2022-08-11 11:02 ` Anders Roxell
2022-08-05 21:13 ` [PATCH v2 3/3] drm/amd/display: implement DSC pass-through support Hamza Mahfooz
2022-08-05 21:13 ` Hamza Mahfooz
2022-08-05 21:13 ` Hamza Mahfooz
2022-08-05 21:17 ` [PATCH v2 1/3] drm/dp_mst: add passthrough_aux to struct drm_dp_mst_port Lyude Paul
2022-08-05 21:17 ` Lyude Paul
2022-08-05 21:17 ` Lyude Paul
2022-08-09 15:15 ` Hamza Mahfooz
2022-08-09 15:15 ` Hamza Mahfooz
2022-08-09 15:15 ` Hamza Mahfooz
2022-08-09 22:01 ` Lyude Paul
2022-08-09 22:01 ` Lyude Paul
2022-08-09 22:01 ` Lyude Paul
2022-08-10 13:23 ` Hamza Mahfooz
2022-08-10 13:23 ` Hamza Mahfooz
2022-08-10 13:23 ` Hamza Mahfooz
2022-08-10 21:24 ` Lyude Paul
2022-08-10 21:24 ` Lyude Paul
2022-08-10 21:24 ` Lyude Paul
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