From: Lu Baolu <baolu.lu@linux.intel.com>
To: Joerg Roedel <joro@8bytes.org>
Cc: kan.liang@linux.intel.com, iommu@lists.linux.dev,
linux-kernel@vger.kernel.org
Subject: [PATCH 05/12] iommu/vt-d: Set No Execute Enable bit in PASID table entry
Date: Tue, 31 Jan 2023 15:37:33 +0800 [thread overview]
Message-ID: <20230131073740.378984-6-baolu.lu@linux.intel.com> (raw)
In-Reply-To: <20230131073740.378984-1-baolu.lu@linux.intel.com>
Setup No Execute Enable bit (Bit 133) of a scalable mode PASID entry.
This is to allow the use of XD bit of the first level page table.
Fixes: ddf09b6d43ec ("iommu/vt-d: Setup pasid entries for iova over first level")
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Link: https://lore.kernel.org/r/20230126095438.354205-1-baolu.lu@linux.intel.com
---
drivers/iommu/intel/pasid.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index fb3c7020028d..ec964ac7d797 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -364,6 +364,16 @@ static inline void pasid_set_page_snoop(struct pasid_entry *pe, bool value)
pasid_set_bits(&pe->val[1], 1 << 23, value << 23);
}
+/*
+ * Setup No Execute Enable bit (Bit 133) of a scalable mode PASID
+ * entry. It is required when XD bit of the first level page table
+ * entry is about to be set.
+ */
+static inline void pasid_set_nxe(struct pasid_entry *pe)
+{
+ pasid_set_bits(&pe->val[2], 1 << 5, 1 << 5);
+}
+
/*
* Setup the Page Snoop (PGSNP) field (Bit 88) of a scalable mode
* PASID entry.
@@ -557,6 +567,7 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu,
pasid_set_domain_id(pte, did);
pasid_set_address_width(pte, iommu->agaw);
pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
+ pasid_set_nxe(pte);
/* Setup Present and PASID Granular Transfer Type: */
pasid_set_translation_type(pte, PASID_ENTRY_PGTT_FL_ONLY);
--
2.34.1
next prev parent reply other threads:[~2023-01-31 7:46 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-31 7:37 [PATCH 00/12] [PULL REQUEST] Intel IOMMU updates for Linux v6.3 Lu Baolu
2023-01-31 7:37 ` [PATCH 01/12] iommu/vt-d: Remove include/linux/intel-svm.h Lu Baolu
2023-01-31 7:37 ` [PATCH 02/12] iommu/vt-d: Remove unused fields in svm structures Lu Baolu
2023-01-31 7:37 ` [PATCH 03/12] iommu/vt-d: Remove users from intel_svm_dev Lu Baolu
2023-01-31 7:37 ` [PATCH 04/12] iommu/vt-d: Remove sva " Lu Baolu
2023-01-31 7:37 ` Lu Baolu [this message]
2023-01-31 7:37 ` [PATCH 06/12] iommu/vt-d: Support size of the register set in DRHD Lu Baolu
2023-01-31 7:37 ` [PATCH 07/12] iommu/vt-d: Retrieve IOMMU perfmon capability information Lu Baolu
2023-01-31 7:37 ` [PATCH 08/12] iommu/vt-d: Support Enhanced Command Interface Lu Baolu
2023-01-31 7:37 ` [PATCH 09/12] iommu/vt-d: Add IOMMU perfmon support Lu Baolu
2023-01-31 7:37 ` [PATCH 10/12] iommu/vt-d: Support cpumask for IOMMU perfmon Lu Baolu
2023-01-31 7:37 ` [PATCH 11/12] iommu/vt-d: Add IOMMU perfmon overflow handler support Lu Baolu
2023-01-31 7:37 ` [PATCH 12/12] iommu/vt-d: Enable IOMMU perfmon support Lu Baolu
2023-02-03 10:09 ` [PATCH 00/12] [PULL REQUEST] Intel IOMMU updates for Linux v6.3 Joerg Roedel
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