From: Anshuman Khandual <anshuman.khandual@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual <anshuman.khandual@arm.com>, Jonathan Corbet <corbet@lwn.net>, Marc Zyngier <maz@kernel.org>, Oliver Upton <oliver.upton@linux.dev>, James Morse <james.morse@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Mark Brown <broonie@kernel.org>, Mark Rutland <mark.rutland@arm.com>, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [RFC 7/8] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9 Date: Fri, 5 Apr 2024 13:30:07 +0530 [thread overview] Message-ID: <20240405080008.1225223-8-anshuman.khandual@arm.com> (raw) In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com> Fine grained trap control for MDSELR_EL1 register needs to be configured in HDFGRTR2_EL2, and HDFGWTR2_EL2 registers when kernel enters at EL1, but EL2 is also present. This adds a new helper __init_el2_fgt2() initializing this new FEAT_FGT2 based fine grained registers. MDCR_EL2.EBWE needs to be enabled for additional (beyond 16) breakpoint and watchpoint exceptions when kernel enters at EL1, but EL2 is also present. This updates __init_el2_debug() as required for FEAT_Debugv8p9. While here, also update booting.rst with MDCR_EL3 and SCR_EL3 requirements. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Marc Zyngier <maz@kernel.org> Cc: Oliver Upton <oliver.upton@linux.dev> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: kvmarm@lists.linux.dev Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> --- Documentation/arch/arm64/booting.rst | 19 +++++++++++++++++++ arch/arm64/include/asm/el2_setup.h | 27 +++++++++++++++++++++++++++ arch/arm64/include/asm/kvm_arm.h | 1 + 3 files changed, 47 insertions(+) diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst index b57776a68f15..e69d972018cf 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -285,6 +285,12 @@ Before jumping into the kernel, the following conditions must be met: - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1. + For CPUs with the Fine Grained Traps (FEAT_FGT2) extension present: + + - If EL3 is present and the kernel is entered at EL2: + + - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1. + For CPUs with support for HCRX_EL2 (FEAT_HCX) present: - If EL3 is present and the kernel is entered at EL2: @@ -319,6 +325,19 @@ Before jumping into the kernel, the following conditions must be met: - ZCR_EL2.LEN must be initialised to the same value for all CPUs the kernel will execute on. + For CPUs with FEAT_Debugv8p9 extension present: + + - If the kernel is entered at EL1 and EL2 is present: + + - HDFGRTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1 + - HDFGWTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1 + - MDCR_EL2.EBWE (bit 43) must be initialized to 0b1 + + - If EL3 is present: + + - MDCR_EL3.TDA (bit 9) must be initialized to 0b0 + - MDCR_EL3.EBWE (bit 43) must be initialized to 0b1 + For CPUs with the Scalable Matrix Extension (FEAT_SME): - If EL3 is present: diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index b7afaa026842..0425067a93d9 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -96,6 +96,14 @@ // to own it. .Lskip_trace_\@: + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4 + cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9 + b.lt .Lskip_dbg_v8p9_\@ + + mov x0, #MDCR_EL2_EBWE + orr x2, x2, x0 +.Lskip_dbg_v8p9_\@: msr mdcr_el2, x2 // Configure debug traps .endm @@ -203,6 +211,24 @@ .Lskip_fgt_\@: .endm +.macro __init_el2_fgt2 + mrs x1, id_aa64mmfr0_el1 + ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 + cmp x1, #ID_AA64MMFR0_EL1_FGT_FGT2 + b.lt .Lskip_fgt2_\@ + + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4 + cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9 + b.lt .Lskip_dbg_v8p9_\@ + + mov_q x0, HDFGWTR2_EL2_nMDSELR_EL1 + msr_s SYS_HDFGWTR2_EL2, x0 + msr_s SYS_HDFGRTR2_EL2, x0 +.Lskip_dbg_v8p9_\@: +.Lskip_fgt2_\@: +.endm + .macro __init_el2_nvhe_prepare_eret mov x0, #INIT_PSTATE_EL1 msr spsr_el2, x0 @@ -228,6 +254,7 @@ __init_el2_nvhe_idregs __init_el2_cptr __init_el2_fgt + __init_el2_fgt2 .endm #ifndef __KVM_NVHE_HYPERVISOR__ diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index e01bb5ca13b7..9d77dfc43e08 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -306,6 +306,7 @@ BIT(11)) /* Hyp Debug Configuration Register bits */ +#define MDCR_EL2_EBWE (UL(1) << 43) #define MDCR_EL2_E2TB_MASK (UL(0x3)) #define MDCR_EL2_E2TB_SHIFT (UL(24)) #define MDCR_EL2_HPMFZS (UL(1) << 36) -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual <anshuman.khandual@arm.com>, Jonathan Corbet <corbet@lwn.net>, Marc Zyngier <maz@kernel.org>, Oliver Upton <oliver.upton@linux.dev>, James Morse <james.morse@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Mark Brown <broonie@kernel.org>, Mark Rutland <mark.rutland@arm.com>, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [RFC 7/8] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9 Date: Fri, 5 Apr 2024 13:30:07 +0530 [thread overview] Message-ID: <20240405080008.1225223-8-anshuman.khandual@arm.com> (raw) In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com> Fine grained trap control for MDSELR_EL1 register needs to be configured in HDFGRTR2_EL2, and HDFGWTR2_EL2 registers when kernel enters at EL1, but EL2 is also present. This adds a new helper __init_el2_fgt2() initializing this new FEAT_FGT2 based fine grained registers. MDCR_EL2.EBWE needs to be enabled for additional (beyond 16) breakpoint and watchpoint exceptions when kernel enters at EL1, but EL2 is also present. This updates __init_el2_debug() as required for FEAT_Debugv8p9. While here, also update booting.rst with MDCR_EL3 and SCR_EL3 requirements. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Marc Zyngier <maz@kernel.org> Cc: Oliver Upton <oliver.upton@linux.dev> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: kvmarm@lists.linux.dev Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> --- Documentation/arch/arm64/booting.rst | 19 +++++++++++++++++++ arch/arm64/include/asm/el2_setup.h | 27 +++++++++++++++++++++++++++ arch/arm64/include/asm/kvm_arm.h | 1 + 3 files changed, 47 insertions(+) diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst index b57776a68f15..e69d972018cf 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -285,6 +285,12 @@ Before jumping into the kernel, the following conditions must be met: - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1. + For CPUs with the Fine Grained Traps (FEAT_FGT2) extension present: + + - If EL3 is present and the kernel is entered at EL2: + + - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1. + For CPUs with support for HCRX_EL2 (FEAT_HCX) present: - If EL3 is present and the kernel is entered at EL2: @@ -319,6 +325,19 @@ Before jumping into the kernel, the following conditions must be met: - ZCR_EL2.LEN must be initialised to the same value for all CPUs the kernel will execute on. + For CPUs with FEAT_Debugv8p9 extension present: + + - If the kernel is entered at EL1 and EL2 is present: + + - HDFGRTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1 + - HDFGWTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1 + - MDCR_EL2.EBWE (bit 43) must be initialized to 0b1 + + - If EL3 is present: + + - MDCR_EL3.TDA (bit 9) must be initialized to 0b0 + - MDCR_EL3.EBWE (bit 43) must be initialized to 0b1 + For CPUs with the Scalable Matrix Extension (FEAT_SME): - If EL3 is present: diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index b7afaa026842..0425067a93d9 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -96,6 +96,14 @@ // to own it. .Lskip_trace_\@: + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4 + cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9 + b.lt .Lskip_dbg_v8p9_\@ + + mov x0, #MDCR_EL2_EBWE + orr x2, x2, x0 +.Lskip_dbg_v8p9_\@: msr mdcr_el2, x2 // Configure debug traps .endm @@ -203,6 +211,24 @@ .Lskip_fgt_\@: .endm +.macro __init_el2_fgt2 + mrs x1, id_aa64mmfr0_el1 + ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 + cmp x1, #ID_AA64MMFR0_EL1_FGT_FGT2 + b.lt .Lskip_fgt2_\@ + + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4 + cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9 + b.lt .Lskip_dbg_v8p9_\@ + + mov_q x0, HDFGWTR2_EL2_nMDSELR_EL1 + msr_s SYS_HDFGWTR2_EL2, x0 + msr_s SYS_HDFGRTR2_EL2, x0 +.Lskip_dbg_v8p9_\@: +.Lskip_fgt2_\@: +.endm + .macro __init_el2_nvhe_prepare_eret mov x0, #INIT_PSTATE_EL1 msr spsr_el2, x0 @@ -228,6 +254,7 @@ __init_el2_nvhe_idregs __init_el2_cptr __init_el2_fgt + __init_el2_fgt2 .endm #ifndef __KVM_NVHE_HYPERVISOR__ diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index e01bb5ca13b7..9d77dfc43e08 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -306,6 +306,7 @@ BIT(11)) /* Hyp Debug Configuration Register bits */ +#define MDCR_EL2_EBWE (UL(1) << 43) #define MDCR_EL2_E2TB_MASK (UL(0x3)) #define MDCR_EL2_E2TB_SHIFT (UL(24)) #define MDCR_EL2_HPMFZS (UL(1) << 36) -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-04-05 8:00 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-05 8:00 [RFC 0/8] arm64/hw_breakpoint: Enable FEAT_Debugv8p9 Anshuman Khandual 2024-04-05 8:00 ` Anshuman Khandual 2024-04-05 8:00 ` [RFC 1/8] arm64/sysreg: Add register fields for MDSELR_EL1 Anshuman Khandual 2024-04-05 8:00 ` Anshuman Khandual 2024-04-05 12:52 ` Mark Brown 2024-04-05 12:52 ` Mark Brown 2024-04-05 8:00 ` [RFC 2/8] arm64/sysreg: Add register fields for HDFGRTR2_EL2 Anshuman Khandual 2024-04-05 8:00 ` Anshuman Khandual 2024-04-05 12:59 ` Mark Brown 2024-04-05 12:59 ` Mark Brown 2024-04-05 8:00 ` [RFC 3/8] arm64/sysreg: Add register fields for HDFGWTR2_EL2 Anshuman Khandual 2024-04-05 8:00 ` Anshuman Khandual 2024-04-05 13:08 ` Mark Brown 2024-04-05 13:08 ` Mark Brown 2024-04-05 8:00 ` [RFC 4/8] arm64/sysreg: Update ID_AA64MMFR0_EL1 register Anshuman Khandual 2024-04-05 8:00 ` Anshuman Khandual 2024-04-05 13:16 ` Mark Brown 2024-04-05 13:16 ` Mark Brown 2024-04-05 8:00 ` [RFC 5/8] KVM: arm64: Explicitly handle MDSELR_EL1 traps as UNDEFINED Anshuman Khandual 2024-04-05 8:00 ` Anshuman Khandual 2024-04-05 10:15 ` Marc Zyngier 2024-04-05 10:15 ` Marc Zyngier 2024-04-12 2:41 ` Anshuman Khandual 2024-04-12 2:41 ` Anshuman Khandual 2024-04-12 11:05 ` Marc Zyngier 2024-04-12 11:05 ` Marc Zyngier 2024-04-16 5:46 ` Anshuman Khandual 2024-04-16 5:46 ` Anshuman Khandual 2024-04-16 8:15 ` Marc Zyngier 2024-04-16 8:15 ` Marc Zyngier 2024-04-05 8:00 ` [RFC 6/8] arm64/cpufeature: Add field details for ID_AA64DFR1_EL1 register Anshuman Khandual 2024-04-05 8:00 ` Anshuman Khandual 2024-04-05 8:00 ` Anshuman Khandual [this message] 2024-04-05 8:00 ` [RFC 7/8] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9 Anshuman Khandual 2024-04-05 8:00 ` [RFC 8/8] arm64/hw_breakpoint: Enable FEAT_Debugv8p9 Anshuman Khandual 2024-04-05 8:00 ` Anshuman Khandual 2024-04-05 10:26 ` Marc Zyngier 2024-04-05 10:26 ` Marc Zyngier 2024-04-16 3:13 ` Anshuman Khandual 2024-04-16 3:13 ` Anshuman Khandual 2024-04-16 3:54 ` [RFC 0/8] " Anshuman Khandual 2024-04-16 3:54 ` Anshuman Khandual
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