From: Waiman Long <waiman.long@hp.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>,
Thomas Gleixner <tglx@linutronix.de>,
"H. Peter Anvin" <hpa@zytor.com>,
x86@kernel.org, linux-kernel@vger.kernel.org,
Scott J Norton <scott.norton@hp.com>,
Douglas Hatch <doug.hatch@hp.com>,
Davidlohr Bueso <dave@stgolabs.net>,
will.deacon@arm.com
Subject: Re: [PATCH v2 1/6] locking/pvqspinlock: Unconditional PV kick with _Q_SLOW_VAL
Date: Thu, 16 Jul 2015 10:07:58 -0400 [thread overview]
Message-ID: <55A7BABE.2070507@hp.com> (raw)
In-Reply-To: <20150716054214.GU19282@twins.programming.kicks-ass.net>
On 07/16/2015 01:42 AM, Peter Zijlstra wrote:
> On Wed, Jul 15, 2015 at 08:18:23PM -0400, Waiman Long wrote:
>> On 07/15/2015 05:10 AM, Peter Zijlstra wrote:
>>> /*
>>> + * A failed cmpxchg doesn't provide any memory-ordering guarantees,
>>> + * so we need a barrier to order the read of the node data in
>>> + * pv_unhash *after* we've read the lock being _Q_SLOW_VAL.
>>> + *
>>> + * Matches the cmpxchg() in pv_wait_head() setting _Q_SLOW_VAL.
>>> + */
>>> + smp_rmb();
>> According to memory_barriers.txt, cmpxchg() is a full memory barrier. It
>> didn't say a failed cmpxchg will lose its memory guarantee. So is the
>> documentation right?
> The documentation is not entirely clear on this; but there are hints
> that this is so.
>
>> Or is that true for some architectures? I think it is
>> not true for x86.
> On x86 LOCK CMPXCHG is always a sync point, but yes there are archs for
> which a failed cmpxchg does _NOT_ provide any barrier semantics.
>
> The reason I started looking was because Will made Argh64 one of those.
That is what I suspected. In that case, I am fine with the patch as
smp_rmb() is an nop in x86 anyway.
Acked-by: Waiman Long <Waiman.Long@hp.com>
BTW, I think we also need to update the documentation to make it clear
that a failed cmpxchg() or atomic_cmpxchg() may not be a full memory
barrier as most people may not be aware of that.
Cheers,
Longman
next prev parent reply other threads:[~2015-07-16 14:08 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-15 2:13 [PATCH 0/6 v2] locking/qspinlock: Enhance pvqspinlock performance Waiman Long
2015-07-15 2:13 ` [PATCH v2 1/6] locking/pvqspinlock: Unconditional PV kick with _Q_SLOW_VAL Waiman Long
2015-07-15 9:10 ` Peter Zijlstra
2015-07-16 0:18 ` Waiman Long
2015-07-16 5:42 ` Peter Zijlstra
2015-07-16 14:07 ` Waiman Long [this message]
2015-07-16 15:04 ` Waiman Long
2015-07-16 15:10 ` Will Deacon
2015-08-03 16:59 ` [tip:locking/core] locking/Documentation: Clarify failed cmpxchg( ) memory ordering semantics tip-bot for Will Deacon
2015-08-03 17:36 ` Davidlohr Bueso
2015-07-15 2:13 ` [PATCH v2 2/6] locking/pvqspinlock: Add pending bit support Waiman Long
2015-07-15 2:13 ` [PATCH v2 3/6] locking/pvqspinlock: Collect slowpath lock statistics Waiman Long
2015-07-15 2:13 ` [PATCH v2 4/6] locking/pvqspinlock: Allow vCPUs kick-ahead Waiman Long
2015-07-15 9:39 ` Peter Zijlstra
2015-07-16 2:01 ` Waiman Long
2015-07-16 5:46 ` Peter Zijlstra
2015-07-16 14:51 ` Waiman Long
2015-07-15 2:13 ` [PATCH v2 5/6] locking/pvqspinlock: Opportunistically defer kicking to unlock time Waiman Long
2015-07-15 6:14 ` Raghavendra K T
2015-07-15 10:03 ` Peter Zijlstra
2015-07-16 2:18 ` Waiman Long
2015-07-16 5:49 ` Peter Zijlstra
2015-07-15 2:13 ` [PATCH v2 6/6] locking/pvqspinlock: Queue node adaptive spinning Waiman Long
2015-07-15 10:01 ` Peter Zijlstra
2015-07-16 2:13 ` Waiman Long
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