Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support

From: Nick Kossifidis <mick@ics.forth.gr>
To: Guo Ren <guoren@kernel.org>
Cc: "Nick Kossifidis" <mick@ics.forth.gr>,
	"Christoph Hellwig" <hch@lst.de>,
	"Drew Fustini" <drew@beagleboard.org>,
	"Anup Patel" <anup.patel@wdc.com>,
	"Palmer Dabbelt" <palmerdabbelt@google.com>,
	wefu@redhat.com, "Wei Wu (吴伟)" <lazyparser@gmail.com>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
	linux-arch <linux-arch@vger.kernel.org>,
	linux-sunxi@lists.linux.dev, "Guo Ren" <guoren@linux.alibaba.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Benjamin Koch" <snowball@c3pb.de>,
	"Matteo Croce" <mcroce@linux.microsoft.com>,
	"Wei Fu" <tekkamanninja@gmail.com>
Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support
Date: Mon, 07 Jun 2021 11:35:55 +0300	[thread overview]
Message-ID: <7347df23102503c77c5da10b48afcf9a@mailhost.ics.forth.gr> (raw)
In-Reply-To: <CAJF2gTQuQ5bE6HeGSoNaDynA0o3+KEo4snwft42YGzE=+DjKOQ@mail.gmail.com>

Στις 2021-06-07 06:19, Guo Ren έγραψε:
>> The C-bit was recently dropped, there is a new proposal for Page Based
>> Memory Attributes (PBMT) that we can work on / push for.
> C-bit still needs discussion, we shouldn't drop it directly.
> 

You can always participate on the discussion on virtmem mailing list.

> Raise a page fault won't solve anything. We still need access to the
> page with proper performance.
> 

The point is that future hw implementations will be required to return a 
page fault in case we tamper with those reserved bits, they won't just 
ignore them. Supporting custom values there means supporting 
non-compliant implementations.

> 
> We need PTEs to provide a non-coherency solution, and only CMO
> instructions are not enough. We can't modify so many Linux drivers to
> fit it.
> From Linux non-coherency view, we need:
>  - Non-cache + Strong Order PTE attributes to deal with drivers' DMA 
> descriptors
>  - Non-cache + weak order to deal with framebuffer drivers
>  - CMO dma_sync to sync cache with DMA devices
>  - Userspace icache_sync solution, which prevents calls to S-mode with
> IPI fence.i. (Necessary to JIT java scenarios.)
> 
> All above are not in spec, but the real chips are done.
> (Actually, these have been talked about for more than five years, we
> still haven't the uniform idea.)
> 
> The idea of C-bit is really important for us which prevents our chips
> violates the spec.

Have you checked the PBMT proposal ? It defines (so far) the following 
attributes that can be set on PTEs to override the PMAs of the 
underlying physical memory:

Bits [62:61]
00 (WB) -> Cacheable, default ordering
01 (NC) -> Noncacheable, default ordering
10 (IO) -> Noncacheable, strong ordering

So it'll cover the use cases you mention.