From: "Michael S. Tsirkin" <mst@redhat.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Bui Quang Minh <minhquangbui99@gmail.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>,
Stefano Stabellini <sstabellini@kernel.org>,
Anthony Perard <anthony.perard@citrix.com>,
Paul Durrant <paul@xen.org>,
Sunil Muthuswamy <sunilmut@microsoft.com>,
xen-devel@lists.xenproject.org
Subject: [PULL 14/60] apic, i386/tcg: add x2apic transitions
Date: Wed, 14 Feb 2024 06:13:57 -0500 [thread overview]
Message-ID: <774204cf9874e58dc7fc13394a505452357750ad.1707909001.git.mst@redhat.com> (raw)
In-Reply-To: <cover.1707909001.git.mst@redhat.com>
From: Bui Quang Minh <minhquangbui99@gmail.com>
This commit adds support for x2APIC transitions when writing to
MSR_IA32_APICBASE register and finally adds CPUID_EXT_X2APIC to
TCG_EXT_FEATURES.
The set_base in APICCommonClass now returns an integer to indicate error in
execution. apic_set_base return -1 on invalid APIC state transition,
accelerator can use this to raise appropriate exception.
Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com>
Message-Id: <20240111154404.5333-4-minhquangbui99@gmail.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/i386/apic.h | 2 +-
include/hw/i386/apic_internal.h | 2 +-
target/i386/cpu.h | 4 ++
hw/i386/kvm/apic.c | 3 +-
hw/i386/xen/xen_apic.c | 3 +-
hw/intc/apic.c | 62 +++++++++++++++++++++++++++-
hw/intc/apic_common.c | 13 +++---
target/i386/cpu.c | 9 ++--
target/i386/tcg/sysemu/misc_helper.c | 14 ++++++-
target/i386/whpx/whpx-apic.c | 3 +-
10 files changed, 96 insertions(+), 19 deletions(-)
diff --git a/include/hw/i386/apic.h b/include/hw/i386/apic.h
index c8ca41ab44..f6e7489f2d 100644
--- a/include/hw/i386/apic.h
+++ b/include/hw/i386/apic.h
@@ -8,7 +8,7 @@ int apic_accept_pic_intr(DeviceState *s);
void apic_deliver_pic_intr(DeviceState *s, int level);
void apic_deliver_nmi(DeviceState *d);
int apic_get_interrupt(DeviceState *s);
-void cpu_set_apic_base(DeviceState *s, uint64_t val);
+int cpu_set_apic_base(DeviceState *s, uint64_t val);
uint64_t cpu_get_apic_base(DeviceState *s);
void cpu_set_apic_tpr(DeviceState *s, uint8_t val);
uint8_t cpu_get_apic_tpr(DeviceState *s);
diff --git a/include/hw/i386/apic_internal.h b/include/hw/i386/apic_internal.h
index e796e6cae3..d6e85833da 100644
--- a/include/hw/i386/apic_internal.h
+++ b/include/hw/i386/apic_internal.h
@@ -137,7 +137,7 @@ struct APICCommonClass {
DeviceRealize realize;
DeviceUnrealize unrealize;
- void (*set_base)(APICCommonState *s, uint64_t val);
+ int (*set_base)(APICCommonState *s, uint64_t val);
void (*set_tpr)(APICCommonState *s, uint8_t val);
uint8_t (*get_tpr)(APICCommonState *s);
void (*enable_tpr_reporting)(APICCommonState *s, bool enable);
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 08eaa61c56..dfe43b8204 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -379,6 +379,10 @@ typedef enum X86Seg {
#define MSR_IA32_APICBASE_ENABLE (1<<11)
#define MSR_IA32_APICBASE_EXTD (1 << 10)
#define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
+#define MSR_IA32_APICBASE_RESERVED \
+ (~(uint64_t)(MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE \
+ | MSR_IA32_APICBASE_EXTD | MSR_IA32_APICBASE_BASE))
+
#define MSR_IA32_FEATURE_CONTROL 0x0000003a
#define MSR_TSC_ADJUST 0x0000003b
#define MSR_IA32_SPEC_CTRL 0x48
diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c
index 1e89ca0899..a72c28e8a7 100644
--- a/hw/i386/kvm/apic.c
+++ b/hw/i386/kvm/apic.c
@@ -95,9 +95,10 @@ void kvm_get_apic_state(DeviceState *dev, struct kvm_lapic_state *kapic)
apic_next_timer(s, s->initial_count_load_time);
}
-static void kvm_apic_set_base(APICCommonState *s, uint64_t val)
+static int kvm_apic_set_base(APICCommonState *s, uint64_t val)
{
s->apicbase = val;
+ return 0;
}
static void kvm_apic_set_tpr(APICCommonState *s, uint8_t val)
diff --git a/hw/i386/xen/xen_apic.c b/hw/i386/xen/xen_apic.c
index 7c7a60b166..101e16a766 100644
--- a/hw/i386/xen/xen_apic.c
+++ b/hw/i386/xen/xen_apic.c
@@ -49,8 +49,9 @@ static void xen_apic_realize(DeviceState *dev, Error **errp)
msi_nonbroken = true;
}
-static void xen_apic_set_base(APICCommonState *s, uint64_t val)
+static int xen_apic_set_base(APICCommonState *s, uint64_t val)
{
+ return 0;
}
static void xen_apic_set_tpr(APICCommonState *s, uint8_t val)
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index 178fb26b47..1d887d66b8 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -308,8 +308,49 @@ bool is_x2apic_mode(DeviceState *dev)
return s->apicbase & MSR_IA32_APICBASE_EXTD;
}
-static void apic_set_base(APICCommonState *s, uint64_t val)
+static int apic_set_base_check(APICCommonState *s, uint64_t val)
{
+ /* Enable x2apic when x2apic is not supported by CPU */
+ if (!cpu_has_x2apic_feature(&s->cpu->env) &&
+ val & MSR_IA32_APICBASE_EXTD) {
+ return -1;
+ }
+
+ /*
+ * Transition into invalid state
+ * (s->apicbase & MSR_IA32_APICBASE_ENABLE == 0) &&
+ * (s->apicbase & MSR_IA32_APICBASE_EXTD) == 1
+ */
+ if (!(val & MSR_IA32_APICBASE_ENABLE) &&
+ (val & MSR_IA32_APICBASE_EXTD)) {
+ return -1;
+ }
+
+ /* Invalid transition from disabled mode to x2APIC */
+ if (!(s->apicbase & MSR_IA32_APICBASE_ENABLE) &&
+ !(s->apicbase & MSR_IA32_APICBASE_EXTD) &&
+ (val & MSR_IA32_APICBASE_ENABLE) &&
+ (val & MSR_IA32_APICBASE_EXTD)) {
+ return -1;
+ }
+
+ /* Invalid transition from x2APIC to xAPIC */
+ if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) &&
+ (s->apicbase & MSR_IA32_APICBASE_EXTD) &&
+ (val & MSR_IA32_APICBASE_ENABLE) &&
+ !(val & MSR_IA32_APICBASE_EXTD)) {
+ return -1;
+ }
+
+ return 0;
+}
+
+static int apic_set_base(APICCommonState *s, uint64_t val)
+{
+ if (apic_set_base_check(s, val) < 0) {
+ return -1;
+ }
+
s->apicbase = (val & 0xfffff000) |
(s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
/* if disabled, cannot be enabled again */
@@ -318,6 +359,25 @@ static void apic_set_base(APICCommonState *s, uint64_t val)
cpu_clear_apic_feature(&s->cpu->env);
s->spurious_vec &= ~APIC_SV_ENABLE;
}
+
+ /* Transition from disabled mode to xAPIC */
+ if (!(s->apicbase & MSR_IA32_APICBASE_ENABLE) &&
+ (val & MSR_IA32_APICBASE_ENABLE)) {
+ s->apicbase |= MSR_IA32_APICBASE_ENABLE;
+ cpu_set_apic_feature(&s->cpu->env);
+ }
+
+ /* Transition from xAPIC to x2APIC */
+ if (cpu_has_x2apic_feature(&s->cpu->env) &&
+ !(s->apicbase & MSR_IA32_APICBASE_EXTD) &&
+ (val & MSR_IA32_APICBASE_EXTD)) {
+ s->apicbase |= MSR_IA32_APICBASE_EXTD;
+
+ s->log_dest = ((s->initial_apic_id & 0xffff0) << 16) |
+ (1 << (s->initial_apic_id & 0xf));
+ }
+
+ return 0;
}
static void apic_set_tpr(APICCommonState *s, uint8_t val)
diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
index 3c43ac9a1d..16ab40a35f 100644
--- a/hw/intc/apic_common.c
+++ b/hw/intc/apic_common.c
@@ -35,20 +35,19 @@
bool apic_report_tpr_access;
-void cpu_set_apic_base(DeviceState *dev, uint64_t val)
+int cpu_set_apic_base(DeviceState *dev, uint64_t val)
{
trace_cpu_set_apic_base(val);
if (dev) {
APICCommonState *s = APIC_COMMON(dev);
APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
- /* switching to x2APIC, reset possibly modified xAPIC ID */
- if (!(s->apicbase & MSR_IA32_APICBASE_EXTD) &&
- (val & MSR_IA32_APICBASE_EXTD)) {
- s->id = s->initial_apic_id;
- }
- info->set_base(s, val);
+ /* Reset possibly modified xAPIC ID */
+ s->id = s->initial_apic_id;
+ return info->set_base(s, val);
}
+
+ return 0;
}
uint64_t cpu_get_apic_base(DeviceState *dev)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ef46755a50..2126b0e589 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -631,8 +631,8 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
* in CPL=3; remove them if they are ever implemented for system emulation.
*/
#if defined CONFIG_USER_ONLY
-#define CPUID_EXT_KERNEL_FEATURES (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER | \
- CPUID_EXT_X2APIC)
+#define CPUID_EXT_KERNEL_FEATURES \
+ (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER)
#else
#define CPUID_EXT_KERNEL_FEATURES 0
#endif
@@ -642,12 +642,13 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \
- CPUID_EXT_FMA | CPUID_EXT_KERNEL_FEATURES)
+ CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES)
/* missing:
CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID,
CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
- CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER */
+ CPUID_EXT_TSC_DEADLINE_TIMER
+ */
#ifdef TARGET_X86_64
#define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM
diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c
index 1c43a9f4f7..7de0a6e866 100644
--- a/target/i386/tcg/sysemu/misc_helper.c
+++ b/target/i386/tcg/sysemu/misc_helper.c
@@ -158,9 +158,19 @@ void helper_wrmsr(CPUX86State *env)
case MSR_IA32_SYSENTER_EIP:
env->sysenter_eip = val;
break;
- case MSR_IA32_APICBASE:
- cpu_set_apic_base(env_archcpu(env)->apic_state, val);
+ case MSR_IA32_APICBASE: {
+ int ret;
+
+ if (val & MSR_IA32_APICBASE_RESERVED) {
+ goto error;
+ }
+
+ ret = cpu_set_apic_base(env_archcpu(env)->apic_state, val);
+ if (ret < 0) {
+ goto error;
+ }
break;
+ }
case MSR_EFER:
{
uint64_t update_mask;
diff --git a/target/i386/whpx/whpx-apic.c b/target/i386/whpx/whpx-apic.c
index 8710e37567..7e14ded978 100644
--- a/target/i386/whpx/whpx-apic.c
+++ b/target/i386/whpx/whpx-apic.c
@@ -90,9 +90,10 @@ static void whpx_get_apic_state(APICCommonState *s,
apic_next_timer(s, s->initial_count_load_time);
}
-static void whpx_apic_set_base(APICCommonState *s, uint64_t val)
+static int whpx_apic_set_base(APICCommonState *s, uint64_t val)
{
s->apicbase = val;
+ return 0;
}
static void whpx_put_apic_base(CPUState *cpu, uint64_t val)
--
MST
next prev parent reply other threads:[~2024-02-14 11:17 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-14 11:13 [PULL 00/60] virtio,pc,pci: features, cleanups, fixes Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 01/60] virtio: split into vhost-user-base and vhost-user-device Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 02/60] hw/virtio: convert vhost-user-base to async shutdown Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 03/60] hw/virtio: derive vhost-user-rng from vhost-user-base Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 04/60] hw/virtio: derive vhost-user-gpio " Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 05/60] hw/virtio: derive vhost-user-i2c " Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 06/60] hw/virtio: add vhost-user-snd and vhost-user-snd-pci devices Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 07/60] docs/system: add a basic enumeration of vhost-user devices Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 08/60] hw/virtio: Support set_config() callback in vhost-user-base Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 09/60] docs/system: Add vhost-user-input documentation Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 10/60] hw/virtio: Move vhost-user-input into virtio folder Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 11/60] hw/virtio: derive vhost-user-input from vhost-user-base Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 12/60] i386/tcg: implement x2APIC registers MSR access Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 13/60] apic: add support for x2APIC mode Michael S. Tsirkin
2024-02-14 11:13 ` Michael S. Tsirkin [this message]
2024-02-14 11:14 ` [PULL 15/60] intel_iommu: allow Extended Interrupt Mode when using userspace APIC Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 16/60] test: bios-tables-test: prepare IVRS change in ACPI table Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 17/60] amd_iommu: report x2APIC support to the operating system Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 18/60] test: bios-tables-test: add IVRS changed binary Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 19/60] hw/i386/x86: Reverse if statement Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 20/60] hw/i386/x86: Fix PIC interrupt handling if APIC is globally disabled Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 21/60] target/i386/cpu: Fix typo in comment Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 22/60] hw/block/fdc-isa: Move portio_list from FDCtrl to FDCtrlISABus Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 23/60] hw/block/fdc-sysbus: Move iomem from FDCtrl to FDCtrlSysBus Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 24/60] hw/char/parallel: Move portio_list from ParallelState to ISAParallelState Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 25/60] exec/ioport: Resolve redundant .base attribute in struct MemoryRegionPortio Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 26/60] exec/ioport: Add portio_list_set_address() Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 27/60] exec/ioport: Add portio_list_set_enabled() Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 28/60] hw/block/fdc-isa: Implement relocation and enabling/disabling for TYPE_ISA_FDC Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 29/60] hw/char/serial-isa: Implement relocation and enabling/disabling for TYPE_ISA_SERIAL Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 30/60] hw/char/parallel-isa: Implement relocation and enabling/disabling for TYPE_ISA_PARALLEL Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 31/60] hw/ppc/pegasos2: Let pegasos2 machine configure SuperI/O functions Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 32/60] hw/isa/vt82c686: Implement relocation and toggling of " Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 33/60] vhost-user.rst: Fix vring address description Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 34/60] MAINTAINERS: Drop myself as VT-d maintainers Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 35/60] virtio_iommu: Clear IOMMUPciBus pointer cache when system reset Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 36/60] smmu: Clear SMMUPciBus " Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 37/60] cxl/cdat: Handle cdat table build errors Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 38/60] hw/mem/cxl_type3: Drop handling of failure of g_malloc0() and g_malloc() Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 39/60] hw/pci-bridge/cxl_upstream: Drop g_malloc() failure handling Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 40/60] cxl/cdat: Fix header sum value in CDAT checksum Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 41/60] hw/cxl/mbox: Remove dead code Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 42/60] hw/cxl/device: read from register values in mdev_reg_read() Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 43/60] hw/cxl: Pass CXLComponentState to cache_mem_ops Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 44/60] hw/cxl: Pass NULL for a NULL MemoryRegionOps Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 45/60] hw/mem/cxl_type3: Fix potential divide by zero reported by coverity Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 46/60] tests/acpi: Allow update of DSDT.cxl Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 47/60] hw/i386: Fix _STA return value for ACPI0017 Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 48/60] tests/acpi: Update DSDT.cxl to reflect change _STA return value Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 49/60] hw/cxl: Update HDM Decoder capability to version 3 Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 50/60] hw/cxl: Update link register definitions Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 51/60] hw/cxl: Update RAS Capability Definitions for version 3 Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 52/60] hw/cxl: Update mailbox status registers Michael S. Tsirkin
2024-02-14 11:16 ` [PULL 53/60] hw/cxl: Standardize all references on CXL r3.1 and minor updates Michael S. Tsirkin
2024-03-08 13:47 ` Peter Maydell
2024-03-08 14:34 ` Jonathan Cameron via
2024-03-08 14:38 ` Peter Maydell
2024-03-08 15:07 ` Jonathan Cameron via
2024-02-14 11:16 ` [PULL 54/60] virtio-gpu: Correct virgl_renderer_resource_get_info() error check Michael S. Tsirkin
2024-02-14 11:16 ` [PULL 55/60] hw/smbios: Fix OEM strings table option validation Michael S. Tsirkin
2024-02-14 11:16 ` [PULL 56/60] hw/smbios: Fix port connector " Michael S. Tsirkin
2024-02-14 11:16 ` [PULL 57/60] hw/display/virtio-gpu.c: use reset_bh class method Michael S. Tsirkin
2024-02-14 11:16 ` [PULL 58/60] virtio-gpu.c: add resource_destroy " Michael S. Tsirkin
2024-02-14 11:16 ` [PULL 59/60] virtio-gpu-rutabaga.c: override resource_destroy method Michael S. Tsirkin
2024-02-14 11:16 ` [PULL 60/60] MAINTAINERS: Switch to my Enfabrica email Michael S. Tsirkin
2024-02-14 11:19 ` [PULL 00/60] virtio,pc,pci: features, cleanups, fixes Michael S. Tsirkin
2024-02-14 17:32 ` Peter Maydell
2024-02-15 9:20 ` Michael Tokarev
2024-02-15 13:39 ` Michael S. Tsirkin
2024-02-15 13:51 ` Michael Tokarev
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