From: "Michael S. Tsirkin" <mst@redhat.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Bui Quang Minh <minhquangbui99@gmail.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Richard Henderson <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>
Subject: [PULL 12/60] i386/tcg: implement x2APIC registers MSR access
Date: Wed, 14 Feb 2024 06:13:51 -0500 [thread overview]
Message-ID: <b2101358e591c9f0a93739dd3aee72935a79af80.1707909001.git.mst@redhat.com> (raw)
In-Reply-To: <cover.1707909001.git.mst@redhat.com>
From: Bui Quang Minh <minhquangbui99@gmail.com>
This commit creates apic_register_read/write which are used by both
apic_mem_read/write for MMIO access and apic_msr_read/write for MSR access.
The apic_msr_read/write returns -1 on error, accelerator can use this to
raise the appropriate exception.
Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com>
Message-Id: <20240111154404.5333-2-minhquangbui99@gmail.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/i386/apic.h | 3 +
target/i386/cpu.h | 3 +
hw/intc/apic.c | 122 ++++++++++++++++++++-------
target/i386/tcg/sysemu/misc_helper.c | 27 ++++++
hw/intc/trace-events | 4 +-
5 files changed, 127 insertions(+), 32 deletions(-)
diff --git a/include/hw/i386/apic.h b/include/hw/i386/apic.h
index bdc15a7a73..ddea4213db 100644
--- a/include/hw/i386/apic.h
+++ b/include/hw/i386/apic.h
@@ -18,6 +18,9 @@ void apic_sipi(DeviceState *s);
void apic_poll_irq(DeviceState *d);
void apic_designate_bsp(DeviceState *d, bool bsp);
int apic_get_highest_priority_irr(DeviceState *dev);
+int apic_msr_read(int index, uint64_t *val);
+int apic_msr_write(int index, uint64_t val);
+bool is_x2apic_mode(DeviceState *d);
/* pc.c */
DeviceState *cpu_get_current_apic(void);
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 6a5b180ccb..afabdeab75 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -545,6 +545,9 @@ typedef enum X86Seg {
#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
#define MSR_IA32_VMX_VMFUNC 0x00000491
+#define MSR_APIC_START 0x00000800
+#define MSR_APIC_END 0x000008ff
+
#define XSTATE_FP_BIT 0
#define XSTATE_SSE_BIT 1
#define XSTATE_YMM_BIT 2
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index ac3d47d231..7a349c0723 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -288,6 +288,13 @@ void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
}
+bool is_x2apic_mode(DeviceState *dev)
+{
+ APICCommonState *s = APIC(dev);
+
+ return s->apicbase & MSR_IA32_APICBASE_EXTD;
+}
+
static void apic_set_base(APICCommonState *s, uint64_t val)
{
s->apicbase = (val & 0xfffff000) |
@@ -636,24 +643,19 @@ static void apic_timer(void *opaque)
apic_timer_update(s, s->next_time);
}
-static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size)
+static int apic_register_read(int index, uint64_t *value)
{
DeviceState *dev;
APICCommonState *s;
uint32_t val;
- int index;
-
- if (size < 4) {
- return 0;
- }
+ int ret = 0;
dev = cpu_get_current_apic();
if (!dev) {
- return 0;
+ return -1;
}
s = APIC(dev);
- index = (addr >> 4) & 0xff;
switch(index) {
case 0x02: /* id */
val = s->id << 24;
@@ -718,12 +720,46 @@ static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size)
default:
s->esr |= APIC_ESR_ILLEGAL_ADDRESS;
val = 0;
+ ret = -1;
break;
}
- trace_apic_mem_readl(addr, val);
+
+ trace_apic_register_read(index, val);
+ *value = val;
+ return ret;
+}
+
+static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size)
+{
+ uint64_t val;
+ int index;
+
+ if (size < 4) {
+ return 0;
+ }
+
+ index = (addr >> 4) & 0xff;
+ apic_register_read(index, &val);
+
return val;
}
+int apic_msr_read(int index, uint64_t *val)
+{
+ DeviceState *dev;
+
+ dev = cpu_get_current_apic();
+ if (!dev) {
+ return -1;
+ }
+
+ if (!is_x2apic_mode(dev)) {
+ return -1;
+ }
+
+ return apic_register_read(index, val);
+}
+
static void apic_send_msi(MSIMessage *msi)
{
uint64_t addr = msi->address;
@@ -737,35 +773,18 @@ static void apic_send_msi(MSIMessage *msi)
apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
}
-static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val,
- unsigned size)
+static int apic_register_write(int index, uint64_t val)
{
DeviceState *dev;
APICCommonState *s;
- int index = (addr >> 4) & 0xff;
-
- if (size < 4) {
- return;
- }
-
- if (addr > 0xfff || !index) {
- /* MSI and MMIO APIC are at the same memory location,
- * but actually not on the global bus: MSI is on PCI bus
- * APIC is connected directly to the CPU.
- * Mapping them on the global bus happens to work because
- * MSI registers are reserved in APIC MMIO and vice versa. */
- MSIMessage msi = { .address = addr, .data = val };
- apic_send_msi(&msi);
- return;
- }
dev = cpu_get_current_apic();
if (!dev) {
- return;
+ return -1;
}
s = APIC(dev);
- trace_apic_mem_writel(addr, val);
+ trace_apic_register_write(index, val);
switch(index) {
case 0x02:
@@ -839,8 +858,51 @@ static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val,
break;
default:
s->esr |= APIC_ESR_ILLEGAL_ADDRESS;
- break;
+ return -1;
}
+
+ return 0;
+}
+
+static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+ int index = (addr >> 4) & 0xff;
+
+ if (size < 4) {
+ return;
+ }
+
+ if (addr > 0xfff || !index) {
+ /*
+ * MSI and MMIO APIC are at the same memory location,
+ * but actually not on the global bus: MSI is on PCI bus
+ * APIC is connected directly to the CPU.
+ * Mapping them on the global bus happens to work because
+ * MSI registers are reserved in APIC MMIO and vice versa.
+ */
+ MSIMessage msi = { .address = addr, .data = val };
+ apic_send_msi(&msi);
+ return;
+ }
+
+ apic_register_write(index, val);
+}
+
+int apic_msr_write(int index, uint64_t val)
+{
+ DeviceState *dev;
+
+ dev = cpu_get_current_apic();
+ if (!dev) {
+ return -1;
+ }
+
+ if (!is_x2apic_mode(dev)) {
+ return -1;
+ }
+
+ return apic_register_write(index, val);
}
static void apic_pre_save(APICCommonState *s)
diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c
index 1ddfc9fe09..1c43a9f4f7 100644
--- a/target/i386/tcg/sysemu/misc_helper.c
+++ b/target/i386/tcg/sysemu/misc_helper.c
@@ -25,6 +25,7 @@
#include "exec/address-spaces.h"
#include "exec/exec-all.h"
#include "tcg/helper-tcg.h"
+#include "hw/i386/apic.h"
void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
{
@@ -289,6 +290,19 @@ void helper_wrmsr(CPUX86State *env)
env->msr_bndcfgs = val;
cpu_sync_bndcs_hflags(env);
break;
+ case MSR_APIC_START ... MSR_APIC_END: {
+ int ret;
+ int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START;
+
+ bql_lock();
+ ret = apic_msr_write(index, val);
+ bql_unlock();
+ if (ret < 0) {
+ goto error;
+ }
+
+ break;
+ }
default:
if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
@@ -455,6 +469,19 @@ void helper_rdmsr(CPUX86State *env)
val = (cs->nr_threads * cs->nr_cores) | (cs->nr_cores << 16);
break;
}
+ case MSR_APIC_START ... MSR_APIC_END: {
+ int ret;
+ int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START;
+
+ bql_lock();
+ ret = apic_msr_read(index, &val);
+ bql_unlock();
+ if (ret < 0) {
+ raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
+ }
+
+ break;
+ }
default:
if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 36ff71f947..1ef29d0256 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -14,8 +14,8 @@ cpu_get_apic_base(uint64_t val) "0x%016"PRIx64
# apic.c
apic_local_deliver(int vector, uint32_t lvt) "vector %d delivery mode %d"
apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t trigger_mode) "dest %d dest_mode %d delivery_mode %d vector %d trigger_mode %d"
-apic_mem_readl(uint64_t addr, uint32_t val) "0x%"PRIx64" = 0x%08x"
-apic_mem_writel(uint64_t addr, uint32_t val) "0x%"PRIx64" = 0x%08x"
+apic_register_read(uint8_t reg, uint64_t val) "register 0x%02x = 0x%"PRIx64
+apic_register_write(uint8_t reg, uint64_t val) "register 0x%02x = 0x%"PRIx64
# ioapic.c
ioapic_set_remote_irr(int n) "set remote irr for pin %d"
--
MST
next prev parent reply other threads:[~2024-02-14 11:14 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-14 11:13 [PULL 00/60] virtio,pc,pci: features, cleanups, fixes Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 01/60] virtio: split into vhost-user-base and vhost-user-device Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 02/60] hw/virtio: convert vhost-user-base to async shutdown Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 03/60] hw/virtio: derive vhost-user-rng from vhost-user-base Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 04/60] hw/virtio: derive vhost-user-gpio " Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 05/60] hw/virtio: derive vhost-user-i2c " Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 06/60] hw/virtio: add vhost-user-snd and vhost-user-snd-pci devices Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 07/60] docs/system: add a basic enumeration of vhost-user devices Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 08/60] hw/virtio: Support set_config() callback in vhost-user-base Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 09/60] docs/system: Add vhost-user-input documentation Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 10/60] hw/virtio: Move vhost-user-input into virtio folder Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 11/60] hw/virtio: derive vhost-user-input from vhost-user-base Michael S. Tsirkin
2024-02-14 11:13 ` Michael S. Tsirkin [this message]
2024-02-14 11:13 ` [PULL 13/60] apic: add support for x2APIC mode Michael S. Tsirkin
2024-02-14 11:13 ` [PULL 14/60] apic, i386/tcg: add x2apic transitions Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 15/60] intel_iommu: allow Extended Interrupt Mode when using userspace APIC Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 16/60] test: bios-tables-test: prepare IVRS change in ACPI table Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 17/60] amd_iommu: report x2APIC support to the operating system Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 18/60] test: bios-tables-test: add IVRS changed binary Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 19/60] hw/i386/x86: Reverse if statement Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 20/60] hw/i386/x86: Fix PIC interrupt handling if APIC is globally disabled Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 21/60] target/i386/cpu: Fix typo in comment Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 22/60] hw/block/fdc-isa: Move portio_list from FDCtrl to FDCtrlISABus Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 23/60] hw/block/fdc-sysbus: Move iomem from FDCtrl to FDCtrlSysBus Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 24/60] hw/char/parallel: Move portio_list from ParallelState to ISAParallelState Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 25/60] exec/ioport: Resolve redundant .base attribute in struct MemoryRegionPortio Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 26/60] exec/ioport: Add portio_list_set_address() Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 27/60] exec/ioport: Add portio_list_set_enabled() Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 28/60] hw/block/fdc-isa: Implement relocation and enabling/disabling for TYPE_ISA_FDC Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 29/60] hw/char/serial-isa: Implement relocation and enabling/disabling for TYPE_ISA_SERIAL Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 30/60] hw/char/parallel-isa: Implement relocation and enabling/disabling for TYPE_ISA_PARALLEL Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 31/60] hw/ppc/pegasos2: Let pegasos2 machine configure SuperI/O functions Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 32/60] hw/isa/vt82c686: Implement relocation and toggling of " Michael S. Tsirkin
2024-02-14 11:14 ` [PULL 33/60] vhost-user.rst: Fix vring address description Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 34/60] MAINTAINERS: Drop myself as VT-d maintainers Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 35/60] virtio_iommu: Clear IOMMUPciBus pointer cache when system reset Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 36/60] smmu: Clear SMMUPciBus " Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 37/60] cxl/cdat: Handle cdat table build errors Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 38/60] hw/mem/cxl_type3: Drop handling of failure of g_malloc0() and g_malloc() Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 39/60] hw/pci-bridge/cxl_upstream: Drop g_malloc() failure handling Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 40/60] cxl/cdat: Fix header sum value in CDAT checksum Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 41/60] hw/cxl/mbox: Remove dead code Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 42/60] hw/cxl/device: read from register values in mdev_reg_read() Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 43/60] hw/cxl: Pass CXLComponentState to cache_mem_ops Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 44/60] hw/cxl: Pass NULL for a NULL MemoryRegionOps Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 45/60] hw/mem/cxl_type3: Fix potential divide by zero reported by coverity Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 46/60] tests/acpi: Allow update of DSDT.cxl Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 47/60] hw/i386: Fix _STA return value for ACPI0017 Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 48/60] tests/acpi: Update DSDT.cxl to reflect change _STA return value Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 49/60] hw/cxl: Update HDM Decoder capability to version 3 Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 50/60] hw/cxl: Update link register definitions Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 51/60] hw/cxl: Update RAS Capability Definitions for version 3 Michael S. Tsirkin
2024-02-14 11:15 ` [PULL 52/60] hw/cxl: Update mailbox status registers Michael S. Tsirkin
2024-02-14 11:16 ` [PULL 53/60] hw/cxl: Standardize all references on CXL r3.1 and minor updates Michael S. Tsirkin
2024-03-08 13:47 ` Peter Maydell
2024-03-08 14:34 ` Jonathan Cameron via
2024-03-08 14:38 ` Peter Maydell
2024-03-08 15:07 ` Jonathan Cameron via
2024-02-14 11:16 ` [PULL 54/60] virtio-gpu: Correct virgl_renderer_resource_get_info() error check Michael S. Tsirkin
2024-02-14 11:16 ` [PULL 55/60] hw/smbios: Fix OEM strings table option validation Michael S. Tsirkin
2024-02-14 11:16 ` [PULL 56/60] hw/smbios: Fix port connector " Michael S. Tsirkin
2024-02-14 11:16 ` [PULL 57/60] hw/display/virtio-gpu.c: use reset_bh class method Michael S. Tsirkin
2024-02-14 11:16 ` [PULL 58/60] virtio-gpu.c: add resource_destroy " Michael S. Tsirkin
2024-02-14 11:16 ` [PULL 59/60] virtio-gpu-rutabaga.c: override resource_destroy method Michael S. Tsirkin
2024-02-14 11:16 ` [PULL 60/60] MAINTAINERS: Switch to my Enfabrica email Michael S. Tsirkin
2024-02-14 11:19 ` [PULL 00/60] virtio,pc,pci: features, cleanups, fixes Michael S. Tsirkin
2024-02-14 17:32 ` Peter Maydell
2024-02-15 9:20 ` Michael Tokarev
2024-02-15 13:39 ` Michael S. Tsirkin
2024-02-15 13:51 ` Michael Tokarev
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