From: isaku.yamahata@intel.com
To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com,
Paolo Bonzini <pbonzini@redhat.com>,
erdemaktas@google.com, Sean Christopherson <seanjc@google.com>,
Sagi Shahar <sagis@google.com>
Subject: [PATCH v8 032/103] KVM: x86/mmu: Allow non-zero value for non-present SPTE
Date: Sun, 7 Aug 2022 15:01:17 -0700 [thread overview]
Message-ID: <8aa5fe0bd8b2e79634440087c32a5d32b4dbe1af.1659854790.git.isaku.yamahata@intel.com> (raw)
In-Reply-To: <cover.1659854790.git.isaku.yamahata@intel.com>
From: Sean Christopherson <sean.j.christopherson@intel.com>
For TD guest, the current way to emulate MMIO doesn't work any more, as KVM
is not able to access the private memory of TD guest and do the emulation.
Instead, TD guest expects to receive #VE when it accesses the MMIO and then
it can explicitly makes hypercall to KVM to get the expected information.
To achieve this, the TDX module always enables "EPT-violation #VE" in the
VMCS control. And accordingly, KVM needs to configure the MMIO spte to
trigger EPT violation (instead of misconfiguration) and at the same time,
also clear the "suppress #VE" bit so the TD guest can get the #VE instead
of causing actual EPT violation to KVM.
In order for KVM to be able to have chance to set up the correct SPTE for
MMIO for TD guest, the default non-present SPTE must have the "suppress
guest accesses the MMIO.
Also, when TD guest accesses the actual shared memory, it should continue
to trigger EPT violation to the KVM instead of receiving the #VE (the TDX
module guarantees KVM will receive EPT violation for private memory
access). This means for the shared memory, the SPTE also must have the
"suppress #VE" bit set for the non-present SPTE.
Add support to allow a non-zero value for the non-present SPTE (i.e. when
the page table is firstly allocated, and when the SPTE is zapped) to allow
setting "suppress #VE" bit for the non-present SPTE.
Introduce a new macro SHADOW_NONPRESENT_VALUE to be the "suppress #VE" bit.
Unconditionally set the "suppress #VE" bit (which is bit 63) for both AMD
and Intel as: 1) AMD hardware doesn't use this bit; 2) for normal VMX
guest, KVM never enables the "EPT-violation #VE" in VMCS control and
"suppress #VE" bit is ignored by hardware.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
---
arch/x86/include/asm/vmx.h | 1 +
arch/x86/kvm/mmu/mmu.c | 77 +++++++++++++++++++++++++++++++---
arch/x86/kvm/mmu/paging_tmpl.h | 3 +-
arch/x86/kvm/mmu/spte.c | 4 +-
arch/x86/kvm/mmu/spte.h | 28 ++++++++++++-
arch/x86/kvm/mmu/tdp_mmu.c | 23 ++++++----
6 files changed, 119 insertions(+), 17 deletions(-)
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index c371ef695fcc..6231ef005a50 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -511,6 +511,7 @@ enum vmcs_field {
#define VMX_EPT_IPAT_BIT (1ull << 6)
#define VMX_EPT_ACCESS_BIT (1ull << 8)
#define VMX_EPT_DIRTY_BIT (1ull << 9)
+#define VMX_EPT_SUPPRESS_VE_BIT (1ull << 63)
#define VMX_EPT_RWX_MASK (VMX_EPT_READABLE_MASK | \
VMX_EPT_WRITABLE_MASK | \
VMX_EPT_EXECUTABLE_MASK)
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 3e1317325e1f..216708a433e7 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -538,9 +538,9 @@ static u64 mmu_spte_clear_track_bits(struct kvm *kvm, u64 *sptep)
if (!is_shadow_present_pte(old_spte) ||
!spte_has_volatile_bits(old_spte))
- __update_clear_spte_fast(sptep, 0ull);
+ __update_clear_spte_fast(sptep, SHADOW_NONPRESENT_VALUE);
else
- old_spte = __update_clear_spte_slow(sptep, 0ull);
+ old_spte = __update_clear_spte_slow(sptep, SHADOW_NONPRESENT_VALUE);
if (!is_shadow_present_pte(old_spte))
return old_spte;
@@ -574,7 +574,7 @@ static u64 mmu_spte_clear_track_bits(struct kvm *kvm, u64 *sptep)
*/
static void mmu_spte_clear_no_track(u64 *sptep)
{
- __update_clear_spte_fast(sptep, 0ull);
+ __update_clear_spte_fast(sptep, SHADOW_NONPRESENT_VALUE);
}
static u64 mmu_spte_get_lockless(u64 *sptep)
@@ -642,6 +642,55 @@ static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
}
}
+#ifdef CONFIG_X86_64
+static inline void kvm_init_shadow_page(void *page)
+{
+ int ign;
+
+ /*
+ * AMD: "suppress #VE" bit is ignored
+ * Intel non-TD(VMX): "suppress #VE" bit is ignored because
+ * EPT_VIOLATION_VE isn't set.
+ * guest TD: TDX module sets EPT_VIOLATION_VE
+ * conventional SEPT: "suppress #VE" bit must be set to get EPT violation
+ * private SEPT: "suppress #VE" bit is ignored. CPU doesn't walk it
+ *
+ * For simplicity, unconditionally initialize SPET to set "suppress #VE".
+ */
+ asm volatile ("rep stosq\n\t"
+ : "=c"(ign), "=D"(page)
+ : "a"(SHADOW_NONPRESENT_VALUE), "c"(4096/8), "D"(page)
+ : "memory"
+ );
+}
+
+static int mmu_topup_shadow_page_cache(struct kvm_vcpu *vcpu)
+{
+ struct kvm_mmu_memory_cache *mc = &vcpu->arch.mmu_shadow_page_cache;
+ int start, end, i, r;
+
+ start = kvm_mmu_memory_cache_nr_free_objects(mc);
+ r = kvm_mmu_topup_memory_cache(mc, PT64_ROOT_MAX_LEVEL);
+
+ /*
+ * Note, topup may have allocated objects even if it failed to allocate
+ * the minimum number of objects required to make forward progress _at
+ * this time_. Initialize newly allocated objects even on failure, as
+ * userspace can free memory and rerun the vCPU in response to -ENOMEM.
+ */
+ end = kvm_mmu_memory_cache_nr_free_objects(mc);
+ for (i = start; i < end; i++)
+ kvm_init_shadow_page(mc->objects[i]);
+ return r;
+}
+#else
+static int mmu_topup_shadow_page_cache(struct kvm_vcpu *vcpu)
+{
+ return kvm_mmu_topup_memory_cache(vcpu->arch.mmu_shadow_page_cache,
+ PT64_ROOT_MAX_LEVEL);
+}
+#endif /* CONFIG_X86_64 */
+
static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect)
{
int r;
@@ -651,8 +700,7 @@ static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect)
1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM);
if (r)
return r;
- r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache,
- PT64_ROOT_MAX_LEVEL);
+ r = mmu_topup_shadow_page_cache(vcpu);
if (r)
return r;
if (maybe_indirect) {
@@ -5815,7 +5863,24 @@ int kvm_mmu_create(struct kvm_vcpu *vcpu)
vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache;
vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO;
- vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
+ /*
+ * When X86_64, initial SEPT entries are initialized with
+ * SHADOW_NONPRESENT_VALUE. Otherwise zeroed. See
+ * mmu_topup_shadow_page_cache().
+ *
+ * Shared EPTEs need to be initialized with SUPPRESS_VE=1, otherwise
+ * not-present EPT violations would be reflected into the guest by
+ * hardware as #VE exceptions. This is handled by initializing page
+ * allocations via kvm_init_shadow_page() during cache topup.
+ * In that case, telling the page allocation to zero-initialize the page
+ * would be wasted effort.
+ *
+ * The initialization is harmless for S-EPT entries because KVM's copy
+ * of the S-EPT isn't consumed by hardware, and because under the hood
+ * S-EPT entries should never #VE.
+ */
+ if (!IS_ENABLED(X86_64))
+ vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
vcpu->arch.mmu = &vcpu->arch.root_mmu;
vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
diff --git a/arch/x86/kvm/mmu/paging_tmpl.h b/arch/x86/kvm/mmu/paging_tmpl.h
index f5958071220c..fe1e973dfb33 100644
--- a/arch/x86/kvm/mmu/paging_tmpl.h
+++ b/arch/x86/kvm/mmu/paging_tmpl.h
@@ -1036,7 +1036,8 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
gpa_t pte_gpa;
gfn_t gfn;
- if (!sp->spt[i])
+ /* spt[i] has initial value of shadow page table allocation */
+ if (sp->spt[i] != SHADOW_NONPRESENT_VALUE)
continue;
pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
diff --git a/arch/x86/kvm/mmu/spte.c b/arch/x86/kvm/mmu/spte.c
index 7314d27d57a4..24cba35570ae 100644
--- a/arch/x86/kvm/mmu/spte.c
+++ b/arch/x86/kvm/mmu/spte.c
@@ -391,7 +391,9 @@ void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only)
shadow_dirty_mask = has_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull;
shadow_nx_mask = 0ull;
shadow_x_mask = VMX_EPT_EXECUTABLE_MASK;
- shadow_present_mask = has_exec_only ? 0ull : VMX_EPT_READABLE_MASK;
+ /* VMX_EPT_SUPPRESS_VE_BIT is needed for W or X violation. */
+ shadow_present_mask =
+ (has_exec_only ? 0ull : VMX_EPT_READABLE_MASK) | VMX_EPT_SUPPRESS_VE_BIT;
/*
* EPT overrides the host MTRRs, and so KVM must program the desired
* memtype directly into the SPTEs. Note, this mask is just the mask
diff --git a/arch/x86/kvm/mmu/spte.h b/arch/x86/kvm/mmu/spte.h
index cabe3fbb4f39..30f456e59e58 100644
--- a/arch/x86/kvm/mmu/spte.h
+++ b/arch/x86/kvm/mmu/spte.h
@@ -136,6 +136,19 @@ static_assert(MMIO_SPTE_GEN_LOW_BITS == 8 && MMIO_SPTE_GEN_HIGH_BITS == 11);
#define MMIO_SPTE_GEN_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_BITS + MMIO_SPTE_GEN_HIGH_BITS - 1, 0)
+/*
+ * non-present SPTE value for both VMX and SVM for TDP MMU.
+ * For SVM NPT, for non-present spte (bit 0 = 0), other bits are ignored.
+ * For VMX EPT, bit 63 is ignored if #VE is disabled.
+ * bit 63 is #VE suppress if #VE is enabled.
+ */
+#ifdef CONFIG_X86_64
+#define SHADOW_NONPRESENT_VALUE BIT_ULL(63)
+static_assert(!(SHADOW_NONPRESENT_VALUE & SPTE_MMU_PRESENT_MASK));
+#else
+#define SHADOW_NONPRESENT_VALUE 0ULL
+#endif
+
extern u64 __read_mostly shadow_host_writable_mask;
extern u64 __read_mostly shadow_mmu_writable_mask;
extern u64 __read_mostly shadow_nx_mask;
@@ -175,16 +188,27 @@ extern u64 __read_mostly shadow_nonpresent_or_rsvd_mask;
* non-present intermediate value. Other threads which encounter this value
* should not modify the SPTE.
*
+ * For X86_64 case, SHADOW_NONPRESENT_VALUE, "suppress #VE" bit, is set because
+ * "EPT violation #VE" in the secondary VM execution control may be enabled.
+ * Because TDX module sets "EPT violation #VE" for TD, "suppress #VE" bit for
+ * the conventional EPT needs to be set.
+ *
* Use a semi-arbitrary value that doesn't set RWX bits, i.e. is not-present on
* bot AMD and Intel CPUs, and doesn't set PFN bits, i.e. doesn't create a L1TF
* vulnerability. Use only low bits to avoid 64-bit immediates.
*
* Only used by the TDP MMU.
*/
-#define REMOVED_SPTE 0x5a0ULL
+#define __REMOVED_SPTE 0x5a0ULL
/* Removed SPTEs must not be misconstrued as shadow present PTEs. */
-static_assert(!(REMOVED_SPTE & SPTE_MMU_PRESENT_MASK));
+static_assert(!(__REMOVED_SPTE & SPTE_MMU_PRESENT_MASK));
+
+/*
+ * See above comment around __REMOVED_SPTE. REMOVED_SPTE is the actual
+ * intermediate value set to the removed SPET. it sets the "suppress #VE" bit.
+ */
+#define REMOVED_SPTE (SHADOW_NONPRESENT_VALUE | __REMOVED_SPTE)
static inline bool is_removed_spte(u64 spte)
{
diff --git a/arch/x86/kvm/mmu/tdp_mmu.c b/arch/x86/kvm/mmu/tdp_mmu.c
index bf2ccf9debca..af510dd31ebc 100644
--- a/arch/x86/kvm/mmu/tdp_mmu.c
+++ b/arch/x86/kvm/mmu/tdp_mmu.c
@@ -682,8 +682,16 @@ static inline int tdp_mmu_zap_spte_atomic(struct kvm *kvm,
* overwrite the special removed SPTE value. No bookkeeping is needed
* here since the SPTE is going from non-present to non-present. Use
* the raw write helper to avoid an unnecessary check on volatile bits.
+ *
+ * Set non-present value to SHADOW_NONPRESENT_VALUE, rather than 0.
+ * It is because when TDX is enabled, TDX module always
+ * enables "EPT-violation #VE", so KVM needs to set
+ * "suppress #VE" bit in EPT table entries, in order to get
+ * real EPT violation, rather than TDVMCALL. KVM sets
+ * SHADOW_NONPRESENT_VALUE (which sets "suppress #VE" bit) so it
+ * can be set when EPT table entries are zapped.
*/
- __kvm_tdp_mmu_write_spte(iter->sptep, 0);
+ __kvm_tdp_mmu_write_spte(iter->sptep, SHADOW_NONPRESENT_VALUE);
return 0;
}
@@ -860,8 +868,8 @@ static void __tdp_mmu_zap_root(struct kvm *kvm, struct kvm_mmu_page *root,
continue;
if (!shared)
- tdp_mmu_set_spte(kvm, &iter, 0);
- else if (tdp_mmu_set_spte_atomic(kvm, &iter, 0))
+ tdp_mmu_set_spte(kvm, &iter, SHADOW_NONPRESENT_VALUE);
+ else if (tdp_mmu_set_spte_atomic(kvm, &iter, SHADOW_NONPRESENT_VALUE))
goto retry;
}
}
@@ -917,8 +925,9 @@ bool kvm_tdp_mmu_zap_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
if (WARN_ON_ONCE(!is_shadow_present_pte(old_spte)))
return false;
- __tdp_mmu_set_spte(kvm, kvm_mmu_page_as_id(sp), sp->ptep, old_spte, 0,
- sp->gfn, sp->role.level + 1, true, true);
+ __tdp_mmu_set_spte(kvm, kvm_mmu_page_as_id(sp), sp->ptep, old_spte,
+ SHADOW_NONPRESENT_VALUE, sp->gfn, sp->role.level + 1,
+ true, true);
return true;
}
@@ -952,7 +961,7 @@ static bool tdp_mmu_zap_leafs(struct kvm *kvm, struct kvm_mmu_page *root,
!is_last_spte(iter.old_spte, iter.level))
continue;
- tdp_mmu_set_spte(kvm, &iter, 0);
+ tdp_mmu_set_spte(kvm, &iter, SHADOW_NONPRESENT_VALUE);
flush = true;
}
@@ -1316,7 +1325,7 @@ static bool set_spte_gfn(struct kvm *kvm, struct tdp_iter *iter,
* invariant that the PFN of a present * leaf SPTE can never change.
* See __handle_changed_spte().
*/
- tdp_mmu_set_spte(kvm, iter, 0);
+ tdp_mmu_set_spte(kvm, iter, SHADOW_NONPRESENT_VALUE);
if (!pte_write(range->pte)) {
new_spte = kvm_mmu_changed_pte_notifier_make_spte(iter->old_spte,
--
2.25.1
next prev parent reply other threads:[~2022-08-07 22:08 UTC|newest]
Thread overview: 165+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-07 22:00 [PATCH v8 000/103] KVM TDX basic feature support isaku.yamahata
2022-08-07 22:00 ` [PATCH v8 001/103] KVM: x86: Move check_processor_compatibility from init ops to runtime ops isaku.yamahata
2022-08-07 22:00 ` [PATCH v8 002/103] Partially revert "KVM: Pass kvm_init()'s opaque param to additional arch funcs" isaku.yamahata
2022-08-11 9:59 ` Huang, Kai
2022-08-25 19:48 ` Isaku Yamahata
2022-08-07 22:00 ` [PATCH v8 003/103] KVM: Refactor CPU compatibility check on module initialization isaku.yamahata
2022-08-09 7:16 ` Binbin Wu
2022-08-11 11:16 ` Huang, Kai
2022-08-11 17:39 ` Sean Christopherson
2022-08-12 11:35 ` Huang, Kai
2022-08-15 22:35 ` Sean Christopherson
2022-08-15 23:06 ` Huang, Kai
2022-08-23 5:27 ` Isaku Yamahata
2022-09-01 9:03 ` Marc Zyngier
2022-09-01 14:08 ` Sean Christopherson
2022-08-07 22:00 ` [PATCH v8 004/103] KVM: VMX: Move out vmx_x86_ops to 'main.c' to wrap VMX and TDX isaku.yamahata
2022-08-09 8:38 ` Binbin Wu
2022-08-11 11:38 ` Huang, Kai
2022-08-07 22:00 ` [PATCH v8 005/103] KVM: x86: Refactor KVM VMX module init/exit functions isaku.yamahata
2022-08-07 22:00 ` [PATCH v8 006/103] KVM: Enable hardware before doing arch VM initialization isaku.yamahata
2022-08-07 22:00 ` [PATCH v8 007/103] KVM: TDX: Add placeholders for TDX VM/vcpu structure isaku.yamahata
2022-08-07 22:00 ` [PATCH v8 008/103] x86/virt/tdx: Add a helper function to return system wide info about TDX module isaku.yamahata
2022-08-29 8:49 ` Yuan Yao
2022-08-07 22:00 ` [PATCH v8 009/103] KVM: TDX: Initialize the TDX module when loading the KVM intel kernel module isaku.yamahata
2022-08-08 10:41 ` Huang, Kai
2022-08-25 20:16 ` Isaku Yamahata
2022-08-10 8:18 ` Binbin Wu
2022-08-25 20:24 ` Isaku Yamahata
2022-08-07 22:00 ` [PATCH v8 010/103] KVM: x86: Introduce vm_type to differentiate default VMs from confidential VMs isaku.yamahata
2022-08-07 22:00 ` [PATCH v8 011/103] KVM: TDX: Make TDX VM type supported isaku.yamahata
2022-08-07 22:00 ` [PATCH v8 012/103] [MARKER] The start of TDX KVM patch series: TDX architectural definitions isaku.yamahata
2022-08-07 22:00 ` [PATCH v8 013/103] KVM: TDX: Define " isaku.yamahata
2022-08-11 3:15 ` Binbin Wu
2022-08-25 21:50 ` Isaku Yamahata
2022-08-07 22:00 ` [PATCH v8 014/103] KVM: TDX: Add TDX "architectural" error codes isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 015/103] KVM: TDX: Add C wrapper functions for SEAMCALLs to the TDX module isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 016/103] KVM: TDX: Add helper functions to print TDX SEAMCALL error isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 017/103] [MARKER] The start of TDX KVM patch series: TD VM creation/destruction isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 018/103] KVM: TDX: Stub in tdx.h with structs, accessors, and VMCS helpers isaku.yamahata
2022-08-23 3:39 ` Binbin Wu
2022-08-23 15:40 ` Sean Christopherson
2022-08-26 4:48 ` Isaku Yamahata
2022-08-30 6:51 ` Yuan Yao
2022-08-31 3:40 ` Xiaoyao Li
2022-08-26 6:24 ` Binbin Wu
2022-08-07 22:01 ` [PATCH v8 019/103] x86/cpu: Add helper functions to allocate/free TDX private host key id isaku.yamahata
2022-08-30 7:17 ` Yuan Yao
2022-08-07 22:01 ` [PATCH v8 020/103] KVM: TDX: create/destroy VM structure isaku.yamahata
2022-08-24 0:53 ` Erdem Aktas
2022-08-26 6:44 ` Isaku Yamahata
2022-08-27 3:52 ` Binbin Wu
2022-08-29 19:09 ` Isaku Yamahata
2022-08-30 8:57 ` Binbin Wu
2022-08-30 9:26 ` Xiaoyao Li
2022-08-30 12:01 ` Yuan Yao
2022-08-07 22:01 ` [PATCH v8 021/103] KVM: TDX: x86: Add ioctl to get TDX systemwide parameters isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 022/103] KVM: TDX: Add place holder for TDX VM specific mem_enc_op ioctl isaku.yamahata
2022-08-29 4:07 ` Binbin Wu
2022-08-29 19:17 ` Isaku Yamahata
2022-08-31 2:18 ` Yuan Yao
2022-08-07 22:01 ` [PATCH v8 023/103] KVM: TDX: initialize VM with TDX specific parameters isaku.yamahata
2022-08-29 8:08 ` Binbin Wu
2022-08-31 5:51 ` Yuan Yao
2022-08-07 22:01 ` [PATCH v8 024/103] KVM: TDX: Make pmu_intel.c ignore guest TD case isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 025/103] [MARKER] The start of TDX KVM patch series: TD vcpu creation/destruction isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 026/103] KVM: TDX: allocate/free TDX vcpu structure isaku.yamahata
2022-08-30 3:20 ` Binbin Wu
2022-08-07 22:01 ` [PATCH v8 027/103] KVM: TDX: Do TDX specific vcpu initialization isaku.yamahata
2022-08-30 9:10 ` Binbin Wu
2022-08-07 22:01 ` [PATCH v8 028/103] [MARKER] The start of TDX KVM patch series: KVM MMU GPA shared bits isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 029/103] KVM: x86/mmu: introduce config for PRIVATE KVM MMU isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 030/103] KVM: x86/mmu: Add address conversion functions for TDX shared bit of GPA isaku.yamahata
2022-08-31 7:07 ` Yuan Yao
2022-08-07 22:01 ` [PATCH v8 031/103] [MARKER] The start of TDX KVM patch series: KVM TDP refactoring for TDX isaku.yamahata
2022-08-07 22:01 ` isaku.yamahata [this message]
2022-08-09 2:56 ` [PATCH v8 032/103] KVM: x86/mmu: Allow non-zero value for non-present SPTE Huang, Kai
2022-08-31 8:03 ` Yuan Yao
2022-08-07 22:01 ` [PATCH v8 033/103] KVM: x86/mmu: Track shadow MMIO value/mask on a per-VM basis isaku.yamahata
2022-08-08 10:14 ` Huang, Kai
2022-09-01 5:54 ` Yuan Yao
2022-08-07 22:01 ` [PATCH v8 034/103] KVM: x86/mmu: Disallow fast page fault on private GPA isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 035/103] KVM: x86/mmu: Allow per-VM override of the TDP max page level isaku.yamahata
2022-09-01 6:07 ` Yuan Yao
2022-08-07 22:01 ` [PATCH v8 036/103] KVM: VMX: Introduce test mode related to EPT violation VE isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 037/103] [MARKER] The start of TDX KVM patch series: KVM TDP MMU hooks isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 038/103] KVM: x86/tdp_mmu: refactor kvm_tdp_mmu_map() isaku.yamahata
2022-09-01 6:48 ` Yuan Yao
2022-08-07 22:01 ` [PATCH v8 039/103] KVM: x86/tdp_mmu: Init role member of struct kvm_mmu_page at allocation isaku.yamahata
2022-09-01 7:12 ` Yuan Yao
2022-08-07 22:01 ` [PATCH v8 040/103] KVM: x86/mmu: Require TDP MMU for TDX isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 041/103] KVM: x86/mmu: Add a new is_private member for union kvm_mmu_page_role isaku.yamahata
2022-09-01 7:44 ` Yuan Yao
2022-08-07 22:01 ` [PATCH v8 042/103] KVM: x86/mmu: Add a private pointer to struct kvm_mmu_page isaku.yamahata
2022-09-01 8:59 ` Yuan Yao
2022-08-07 22:01 ` [PATCH v8 043/103] KVM: x86/tdp_mmu: Don't zap private pages for unsupported cases isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 044/103] KVM: x86/tdp_mmu: Support TDX private mapping for TDP MMU isaku.yamahata
2022-09-02 6:38 ` Yuan Yao
2022-08-07 22:01 ` [PATCH v8 045/103] [MARKER] The start of TDX KVM patch series: TDX EPT violation isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 046/103] KVM: x86/mmu: Disallow dirty logging for x86 TDX isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 047/103] KVM: x86/tdp_mmu: Ignore unsupported mmu operation on private GFNs isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 048/103] KVM: VMX: Split out guts of EPT violation to common/exposed function isaku.yamahata
2022-09-02 7:05 ` Yuan Yao
2022-08-07 22:01 ` [PATCH v8 049/103] KVM: VMX: Move setting of EPT MMU masks to common VT-x code isaku.yamahata
2022-09-02 7:23 ` Yuan Yao
2022-08-07 22:01 ` [PATCH v8 050/103] KVM: TDX: Add load_mmu_pgd method for TDX isaku.yamahata
2022-09-02 7:27 ` Yuan Yao
2022-08-07 22:01 ` [PATCH v8 051/103] KVM: TDX: don't request KVM_REQ_APIC_PAGE_RELOAD isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 052/103] KVM: x86/VMX: introduce vmx tlb_remote_flush and tlb_remote_flush_with_range isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 053/103] KVM: TDX: TDP MMU TDX support isaku.yamahata
2022-08-16 15:35 ` Sean Christopherson
2022-08-16 23:04 ` Huang, Kai
2022-08-07 22:01 ` [PATCH v8 054/103] [MARKER] The start of TDX KVM patch series: KVM TDP MMU MapGPA isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 055/103] KVM: Add functions to track whether GFN is private or shared isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 056/103] KVM: x86/mmu: Let vcpu re-try when faulting page type conflict isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 057/103] KVM: x86/mmu: Introduce kvm_mmu_map_tdp_page() for use by TDX isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 058/103] KVM: x86/tdp_mmu: implement MapGPA hypercall for TDX isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 059/103] [MARKER] The start of TDX KVM patch series: TD finalization isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 060/103] KVM: TDX: Create initial guest memory isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 061/103] KVM: TDX: Finalize VM initialization isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 062/103] [MARKER] The start of TDX KVM patch series: TD vcpu enter/exit isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 063/103] KVM: TDX: Add helper assembly function to TDX vcpu isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 064/103] KVM: TDX: Implement TDX vcpu enter/exit path isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 065/103] KVM: TDX: vcpu_run: save/restore host state(host kernel gs) isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 066/103] KVM: TDX: restore host xsave state when exit from the guest TD isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 067/103] KVM: x86: Allow to update cached values in kvm_user_return_msrs w/o wrmsr isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 068/103] KVM: TDX: restore user ret MSRs isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 069/103] [MARKER] The start of TDX KVM patch series: TD vcpu exits/interrupts/hypercalls isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 070/103] KVM: TDX: complete interrupts after tdexit isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 071/103] KVM: TDX: restore debug store when TD exit isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 072/103] KVM: TDX: handle vcpu migration over logical processor isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 073/103] KVM: x86: Add a switch_db_regs flag to handle TDX's auto-switched behavior isaku.yamahata
2022-08-07 22:01 ` [PATCH v8 074/103] KVM: TDX: Add support for find pending IRQ in a protected local APIC isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 075/103] KVM: x86: Assume timer IRQ was injected if APIC state is proteced isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 076/103] KVM: TDX: remove use of struct vcpu_vmx from posted_interrupt.c isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 077/103] KVM: TDX: Implement interrupt injection isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 078/103] KVM: TDX: Implements vcpu request_immediate_exit isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 079/103] KVM: TDX: Implement methods to inject NMI isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 080/103] KVM: VMX: Modify NMI and INTR handlers to take intr_info as function argument isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 081/103] KVM: VMX: Move NMI/exception handler to common helper isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 082/103] KVM: x86: Split core of hypercall emulation to helper function isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 083/103] KVM: TDX: Add a place holder to handle TDX VM exit isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 084/103] KVM: TDX: Retry seamcall when TDX_OPERAND_BUSY with operand SEPT isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 085/103] KVM: TDX: handle EXIT_REASON_OTHER_SMI isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 086/103] KVM: TDX: handle ept violation/misconfig exit isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 087/103] KVM: TDX: handle EXCEPTION_NMI and EXTERNAL_INTERRUPT isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 088/103] KVM: TDX: Add a place holder for handler of TDX hypercalls (TDG.VP.VMCALL) isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 089/103] KVM: TDX: handle KVM hypercall with TDG.VP.VMCALL isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 090/103] KVM: TDX: Handle TDX PV CPUID hypercall isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 091/103] KVM: TDX: Handle TDX PV HLT hypercall isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 092/103] KVM: TDX: Handle TDX PV port io hypercall isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 093/103] KVM: TDX: Handle TDX PV MMIO hypercall isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 094/103] KVM: TDX: Implement callbacks for MSR operations for TDX isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 095/103] KVM: TDX: Handle TDX PV rdmsr/wrmsr hypercall isaku.yamahata
2022-08-17 22:40 ` Sagi Shahar
2022-08-26 6:46 ` Isaku Yamahata
2022-08-07 22:02 ` [PATCH v8 096/103] KVM: TDX: Handle TDX PV report fatal error hypercall isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 097/103] KVM: TDX: Handle TDX PV map_gpa hypercall isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 098/103] KVM: TDX: Handle TDG.VP.VMCALL<GetTdVmCallInfo> hypercall isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 099/103] KVM: TDX: Silently discard SMI request isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 100/103] KVM: TDX: Silently ignore INIT/SIPI isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 101/103] KVM: TDX: Add methods to ignore accesses to CPU state isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 102/103] Documentation/virt/kvm: Document on Trust Domain Extensions(TDX) isaku.yamahata
2022-08-07 22:02 ` [PATCH v8 103/103] KVM: x86: design documentation on TDX support of x86 KVM TDP MMU isaku.yamahata
2022-08-08 3:47 ` [PATCH v8 000/103] KVM TDX basic feature support Bagas Sanjaya
2022-08-08 20:44 ` Isaku Yamahata
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