From: Viresh Kumar <viresh.kumar@linaro.org>
To: Thomas Gleixner <tglx@linutronix.de>,
Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: linaro-kernel@lists.linaro.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Viresh Kumar <viresh.kumar@linaro.org>,
Jacob Pan <jacob.jun.pan@linux.intel.com>,
Jamie Iles <jamie@jamieiles.com>
Subject: [PATCH 05/41] clocksource: dw_apb: Migrate to new 'set-state' interface
Date: Thu, 18 Jun 2015 16:24:19 +0530 [thread overview]
Message-ID: <8fc35aa8bdb893ee9e92e3f3c7af2671b8ed8319.1434622147.git.viresh.kumar@linaro.org> (raw)
In-Reply-To: <cover.1434622147.git.viresh.kumar@linaro.org>
In-Reply-To: <cover.1434622147.git.viresh.kumar@linaro.org>
Migrate dw_apb driver to the new 'set-state' interface provided by
clockevents core, the earlier 'set-mode' interface is marked obsolete
now.
This also enables us to implement callbacks for new states of clockevent
devices, for example: ONESHOT_STOPPED.
Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
Cc: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
drivers/clocksource/dw_apb_timer.c | 143 +++++++++++++++++++++----------------
1 file changed, 81 insertions(+), 62 deletions(-)
diff --git a/drivers/clocksource/dw_apb_timer.c b/drivers/clocksource/dw_apb_timer.c
index 35a88097af3c..97ba7cbc2cbd 100644
--- a/drivers/clocksource/dw_apb_timer.c
+++ b/drivers/clocksource/dw_apb_timer.c
@@ -110,71 +110,87 @@ static void apbt_enable_int(struct dw_apb_timer *timer)
apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
}
-static void apbt_set_mode(enum clock_event_mode mode,
- struct clock_event_device *evt)
+static int apbt_shutdown(struct clock_event_device *evt)
{
+ struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
unsigned long ctrl;
- unsigned long period;
+
+ pr_debug("%s CPU %d state=shutdown\n", __func__,
+ cpumask_first(evt->cpumask));
+
+ ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
+ ctrl &= ~APBTMR_CONTROL_ENABLE;
+ apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
+ return 0;
+}
+
+static int apbt_set_oneshot(struct clock_event_device *evt)
+{
struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
+ unsigned long ctrl;
- pr_debug("%s CPU %d mode=%d\n", __func__,
- cpumask_first(evt->cpumask),
- mode);
-
- switch (mode) {
- case CLOCK_EVT_MODE_PERIODIC:
- period = DIV_ROUND_UP(dw_ced->timer.freq, HZ);
- ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
- ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
- apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
- /*
- * DW APB p. 46, have to disable timer before load counter,
- * may cause sync problem.
- */
- ctrl &= ~APBTMR_CONTROL_ENABLE;
- apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
- udelay(1);
- pr_debug("Setting clock period %lu for HZ %d\n", period, HZ);
- apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT);
- ctrl |= APBTMR_CONTROL_ENABLE;
- apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
- break;
-
- case CLOCK_EVT_MODE_ONESHOT:
- ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
- /*
- * set free running mode, this mode will let timer reload max
- * timeout which will give time (3min on 25MHz clock) to rearm
- * the next event, therefore emulate the one-shot mode.
- */
- ctrl &= ~APBTMR_CONTROL_ENABLE;
- ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
-
- apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
- /* write again to set free running mode */
- apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
-
- /*
- * DW APB p. 46, load counter with all 1s before starting free
- * running mode.
- */
- apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT);
- ctrl &= ~APBTMR_CONTROL_INT;
- ctrl |= APBTMR_CONTROL_ENABLE;
- apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
- break;
-
- case CLOCK_EVT_MODE_UNUSED:
- case CLOCK_EVT_MODE_SHUTDOWN:
- ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
- ctrl &= ~APBTMR_CONTROL_ENABLE;
- apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
- break;
-
- case CLOCK_EVT_MODE_RESUME:
- apbt_enable_int(&dw_ced->timer);
- break;
- }
+ pr_debug("%s CPU %d state=oneshot\n", __func__,
+ cpumask_first(evt->cpumask));
+
+ ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
+ /*
+ * set free running mode, this mode will let timer reload max
+ * timeout which will give time (3min on 25MHz clock) to rearm
+ * the next event, therefore emulate the one-shot mode.
+ */
+ ctrl &= ~APBTMR_CONTROL_ENABLE;
+ ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
+
+ apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
+ /* write again to set free running mode */
+ apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
+
+ /*
+ * DW APB p. 46, load counter with all 1s before starting free
+ * running mode.
+ */
+ apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT);
+ ctrl &= ~APBTMR_CONTROL_INT;
+ ctrl |= APBTMR_CONTROL_ENABLE;
+ apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
+ return 0;
+}
+
+static int apbt_set_periodic(struct clock_event_device *evt)
+{
+ struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
+ unsigned long period = DIV_ROUND_UP(dw_ced->timer.freq, HZ);
+ unsigned long ctrl;
+
+ pr_debug("%s CPU %d state=periodic\n", __func__,
+ cpumask_first(evt->cpumask));
+
+ ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
+ ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
+ apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
+ /*
+ * DW APB p. 46, have to disable timer before load counter,
+ * may cause sync problem.
+ */
+ ctrl &= ~APBTMR_CONTROL_ENABLE;
+ apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
+ udelay(1);
+ pr_debug("Setting clock period %lu for HZ %d\n", period, HZ);
+ apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT);
+ ctrl |= APBTMR_CONTROL_ENABLE;
+ apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
+ return 0;
+}
+
+static int apbt_resume(struct clock_event_device *evt)
+{
+ struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
+
+ pr_debug("%s CPU %d state=resume\n", __func__,
+ cpumask_first(evt->cpumask));
+
+ apbt_enable_int(&dw_ced->timer);
+ return 0;
}
static int apbt_next_event(unsigned long delta,
@@ -233,7 +249,10 @@ dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
dw_ced->ced.min_delta_ns = clockevent_delta2ns(5000, &dw_ced->ced);
dw_ced->ced.cpumask = cpumask_of(cpu);
dw_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
- dw_ced->ced.set_mode = apbt_set_mode;
+ dw_ced->ced.set_state_shutdown = apbt_shutdown;
+ dw_ced->ced.set_state_periodic = apbt_set_periodic;
+ dw_ced->ced.set_state_oneshot = apbt_set_oneshot;
+ dw_ced->ced.tick_resume = apbt_resume;
dw_ced->ced.set_next_event = apbt_next_event;
dw_ced->ced.irq = dw_ced->timer.irq;
dw_ced->ced.rating = rating;
--
2.4.0
WARNING: multiple messages have this Message-ID (diff)
From: viresh.kumar@linaro.org (Viresh Kumar)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 05/41] clocksource: dw_apb: Migrate to new 'set-state' interface
Date: Thu, 18 Jun 2015 16:24:19 +0530 [thread overview]
Message-ID: <8fc35aa8bdb893ee9e92e3f3c7af2671b8ed8319.1434622147.git.viresh.kumar@linaro.org> (raw)
In-Reply-To: <cover.1434622147.git.viresh.kumar@linaro.org>
Migrate dw_apb driver to the new 'set-state' interface provided by
clockevents core, the earlier 'set-mode' interface is marked obsolete
now.
This also enables us to implement callbacks for new states of clockevent
devices, for example: ONESHOT_STOPPED.
Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
Cc: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
drivers/clocksource/dw_apb_timer.c | 143 +++++++++++++++++++++----------------
1 file changed, 81 insertions(+), 62 deletions(-)
diff --git a/drivers/clocksource/dw_apb_timer.c b/drivers/clocksource/dw_apb_timer.c
index 35a88097af3c..97ba7cbc2cbd 100644
--- a/drivers/clocksource/dw_apb_timer.c
+++ b/drivers/clocksource/dw_apb_timer.c
@@ -110,71 +110,87 @@ static void apbt_enable_int(struct dw_apb_timer *timer)
apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
}
-static void apbt_set_mode(enum clock_event_mode mode,
- struct clock_event_device *evt)
+static int apbt_shutdown(struct clock_event_device *evt)
{
+ struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
unsigned long ctrl;
- unsigned long period;
+
+ pr_debug("%s CPU %d state=shutdown\n", __func__,
+ cpumask_first(evt->cpumask));
+
+ ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
+ ctrl &= ~APBTMR_CONTROL_ENABLE;
+ apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
+ return 0;
+}
+
+static int apbt_set_oneshot(struct clock_event_device *evt)
+{
struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
+ unsigned long ctrl;
- pr_debug("%s CPU %d mode=%d\n", __func__,
- cpumask_first(evt->cpumask),
- mode);
-
- switch (mode) {
- case CLOCK_EVT_MODE_PERIODIC:
- period = DIV_ROUND_UP(dw_ced->timer.freq, HZ);
- ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
- ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
- apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
- /*
- * DW APB p. 46, have to disable timer before load counter,
- * may cause sync problem.
- */
- ctrl &= ~APBTMR_CONTROL_ENABLE;
- apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
- udelay(1);
- pr_debug("Setting clock period %lu for HZ %d\n", period, HZ);
- apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT);
- ctrl |= APBTMR_CONTROL_ENABLE;
- apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
- break;
-
- case CLOCK_EVT_MODE_ONESHOT:
- ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
- /*
- * set free running mode, this mode will let timer reload max
- * timeout which will give time (3min on 25MHz clock) to rearm
- * the next event, therefore emulate the one-shot mode.
- */
- ctrl &= ~APBTMR_CONTROL_ENABLE;
- ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
-
- apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
- /* write again to set free running mode */
- apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
-
- /*
- * DW APB p. 46, load counter with all 1s before starting free
- * running mode.
- */
- apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT);
- ctrl &= ~APBTMR_CONTROL_INT;
- ctrl |= APBTMR_CONTROL_ENABLE;
- apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
- break;
-
- case CLOCK_EVT_MODE_UNUSED:
- case CLOCK_EVT_MODE_SHUTDOWN:
- ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
- ctrl &= ~APBTMR_CONTROL_ENABLE;
- apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
- break;
-
- case CLOCK_EVT_MODE_RESUME:
- apbt_enable_int(&dw_ced->timer);
- break;
- }
+ pr_debug("%s CPU %d state=oneshot\n", __func__,
+ cpumask_first(evt->cpumask));
+
+ ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
+ /*
+ * set free running mode, this mode will let timer reload max
+ * timeout which will give time (3min on 25MHz clock) to rearm
+ * the next event, therefore emulate the one-shot mode.
+ */
+ ctrl &= ~APBTMR_CONTROL_ENABLE;
+ ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
+
+ apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
+ /* write again to set free running mode */
+ apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
+
+ /*
+ * DW APB p. 46, load counter with all 1s before starting free
+ * running mode.
+ */
+ apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT);
+ ctrl &= ~APBTMR_CONTROL_INT;
+ ctrl |= APBTMR_CONTROL_ENABLE;
+ apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
+ return 0;
+}
+
+static int apbt_set_periodic(struct clock_event_device *evt)
+{
+ struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
+ unsigned long period = DIV_ROUND_UP(dw_ced->timer.freq, HZ);
+ unsigned long ctrl;
+
+ pr_debug("%s CPU %d state=periodic\n", __func__,
+ cpumask_first(evt->cpumask));
+
+ ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
+ ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
+ apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
+ /*
+ * DW APB p. 46, have to disable timer before load counter,
+ * may cause sync problem.
+ */
+ ctrl &= ~APBTMR_CONTROL_ENABLE;
+ apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
+ udelay(1);
+ pr_debug("Setting clock period %lu for HZ %d\n", period, HZ);
+ apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT);
+ ctrl |= APBTMR_CONTROL_ENABLE;
+ apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
+ return 0;
+}
+
+static int apbt_resume(struct clock_event_device *evt)
+{
+ struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
+
+ pr_debug("%s CPU %d state=resume\n", __func__,
+ cpumask_first(evt->cpumask));
+
+ apbt_enable_int(&dw_ced->timer);
+ return 0;
}
static int apbt_next_event(unsigned long delta,
@@ -233,7 +249,10 @@ dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
dw_ced->ced.min_delta_ns = clockevent_delta2ns(5000, &dw_ced->ced);
dw_ced->ced.cpumask = cpumask_of(cpu);
dw_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
- dw_ced->ced.set_mode = apbt_set_mode;
+ dw_ced->ced.set_state_shutdown = apbt_shutdown;
+ dw_ced->ced.set_state_periodic = apbt_set_periodic;
+ dw_ced->ced.set_state_oneshot = apbt_set_oneshot;
+ dw_ced->ced.tick_resume = apbt_resume;
dw_ced->ced.set_next_event = apbt_next_event;
dw_ced->ced.irq = dw_ced->timer.irq;
dw_ced->ced.rating = rating;
--
2.4.0
next prev parent reply other threads:[~2015-06-18 10:55 UTC|newest]
Thread overview: 171+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1434622147.git.viresh.kumar@linaro.org>
2015-06-18 10:54 ` [PATCH 01/41] clocksource: asm9260: Migrate to new 'set-state' interface Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-30 8:25 ` Daniel Lezcano
2015-06-30 8:25 ` Daniel Lezcano
2015-06-30 9:00 ` Viresh Kumar
2015-06-30 9:00 ` Viresh Kumar
2015-06-30 9:20 ` Daniel Lezcano
2015-06-30 9:20 ` Daniel Lezcano
2015-07-08 5:37 ` Vineet Gupta
2015-07-08 5:37 ` Vineet Gupta
2015-07-08 5:37 ` Vineet Gupta
2015-07-08 5:43 ` Viresh Kumar
2015-07-08 5:43 ` Viresh Kumar
2015-07-08 6:14 ` Vineet Gupta
2015-07-08 6:14 ` Vineet Gupta
2015-06-18 10:54 ` [PATCH 02/41] clocksource: cadence_ttc: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-25 23:15 ` Sören Brinkmann
2015-06-25 23:15 ` Sören Brinkmann
2015-06-30 8:28 ` Daniel Lezcano
2015-06-30 8:28 ` Daniel Lezcano
2015-06-18 10:54 ` [PATCH 03/41] clocksource: clps711x: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 04/41] clocksource: dummy_timer: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar [this message]
2015-06-18 10:54 ` [PATCH 05/41] clocksource: dw_apb: " Viresh Kumar
2015-06-18 10:54 ` [PATCH 06/41] clocksource: exynos_mct: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 16:38 ` Alexey Klimov
2015-06-18 16:38 ` Alexey Klimov
2015-06-19 2:14 ` Viresh Kumar
2015-06-19 2:14 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 07/41] clocksource: fsl_ftm: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 08/41] clocksource: i8253: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 09/41] clocksource: meson6: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-20 6:53 ` Carlo Caione
2015-06-20 6:53 ` Carlo Caione
2015-06-18 10:54 ` [PATCH 10/41] clocksource: metag_generic: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 11/41] clocksource: mips-gic: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 12/41] clocksource: moxart: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 13/41] clocksource: mtk: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 14/41] clocksource: mxs: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-07-17 5:28 ` Stefan Wahren
2015-07-17 5:28 ` Stefan Wahren
2015-06-18 10:54 ` [PATCH 15/41] clocksource: nomadik-mtu: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-07-14 11:11 ` Linus Walleij
2015-07-14 11:11 ` Linus Walleij
2015-06-18 10:54 ` [PATCH 16/41] clocksource: pxa: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-07-04 15:42 ` Robert Jarzmik
2015-07-04 15:42 ` Robert Jarzmik
2015-07-05 3:37 ` Viresh Kumar
2015-07-05 3:37 ` Viresh Kumar
2015-07-06 6:13 ` Robert Jarzmik
2015-07-06 6:13 ` Robert Jarzmik
2015-06-18 10:54 ` [PATCH 17/41] clocksource: qcom: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-19 19:10 ` Stephen Boyd
2015-06-19 19:10 ` Stephen Boyd
2015-06-18 10:54 ` [PATCH 18/41] clocksource: rockchip: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 19/41] clocksource: samsung_pwm: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 20/41] clocksource: sh_cmt: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 13:10 ` Laurent Pinchart
2015-06-18 13:10 ` Laurent Pinchart
2015-06-18 10:54 ` [PATCH 21/41] clocksource: sh_mtu2: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 13:10 ` Laurent Pinchart
2015-06-18 13:10 ` Laurent Pinchart
2015-06-18 10:54 ` [PATCH 22/41] clocksource: sh_tmu: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 13:10 ` Laurent Pinchart
2015-06-18 13:10 ` Laurent Pinchart
2015-06-18 10:54 ` [PATCH 23/41] clocksource: sun4i: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 12:01 ` Maxime Ripard
2015-06-18 12:01 ` Maxime Ripard
2015-06-18 12:23 ` Viresh Kumar
2015-06-18 12:23 ` Viresh Kumar
2015-06-19 10:30 ` Maxime Ripard
2015-06-19 10:30 ` Maxime Ripard
2015-06-18 10:54 ` [PATCH 24/41] clocksource: tcb_clksrc: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 25/41] clocksource: tegra20: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-07-02 19:41 ` Daniel Lezcano
2015-07-02 19:41 ` Daniel Lezcano
2015-07-03 8:54 ` Viresh Kumar
2015-07-03 8:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 26/41] clocksource: time-armada-370-xp: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 27/41] clocksource: efm32: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 28/41] clocksource: orion: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 29/41] clocksource: atlas7: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 30/41] clocksource: atmel: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 14:28 ` Alexandre Belloni
2015-06-18 14:28 ` Alexandre Belloni
2015-06-18 10:54 ` [PATCH 31/41] clocksource: atmel-st: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 14:40 ` Alexandre Belloni
2015-06-18 14:40 ` Alexandre Belloni
2015-06-19 1:49 ` Viresh Kumar
2015-06-19 1:49 ` Viresh Kumar
2015-06-19 11:48 ` Alexandre Belloni
2015-06-19 11:48 ` Alexandre Belloni
2015-06-19 11:52 ` Viresh Kumar
2015-06-19 11:52 ` Viresh Kumar
2015-06-19 12:06 ` Alexandre Belloni
2015-06-19 12:06 ` Alexandre Belloni
2015-06-18 10:54 ` [PATCH 32/41] clocksource: digicolor: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-23 10:17 ` Baruch Siach
2015-06-23 10:17 ` Baruch Siach
2015-06-23 10:21 ` Viresh Kumar
2015-06-23 10:21 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 33/41] clocksource: integrator: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-07-14 13:35 ` Linus Walleij
2015-07-14 13:35 ` Linus Walleij
2015-06-18 10:54 ` [PATCH 34/41] clocksource: keystone: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 35/41] clocksource: prima2: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 36/41] clocksource: stm32: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 11:09 ` Maxime Coquelin
2015-06-18 11:09 ` Maxime Coquelin
2015-06-18 11:32 ` Viresh Kumar
2015-06-18 11:32 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 37/41] clocksource: sun5i: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 38/41] clocksource: u300: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-07-14 13:36 ` Linus Walleij
2015-07-14 13:36 ` Linus Walleij
2015-06-18 10:54 ` [PATCH 39/41] clocksource: vf_pit: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-07-03 8:10 ` Stefan Agner
2015-07-03 8:10 ` Stefan Agner
2015-07-03 8:57 ` Viresh Kumar
2015-07-03 8:57 ` Viresh Kumar
2015-07-03 11:11 ` Stefan Agner
2015-07-03 11:11 ` Stefan Agner
2015-07-03 11:17 ` Viresh Kumar
2015-07-03 11:17 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 40/41] clocksource: vt8500: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-06-18 10:54 ` [PATCH 41/41] clocksource: zevio: " Viresh Kumar
2015-06-18 10:54 ` Viresh Kumar
2015-07-02 20:11 ` Daniel Lezcano
2015-07-02 20:11 ` Daniel Lezcano
2015-07-03 8:56 ` Viresh Kumar
2015-07-03 8:56 ` Viresh Kumar
2015-07-03 8:59 ` Daniel Lezcano
2015-07-03 8:59 ` Daniel Lezcano
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