From: Daniel Stone <daniel@fooishbar.org>
To: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: "DRI Development" <dri-devel@lists.freedesktop.org>,
"Tomeu Vizoso" <tomeu.vizoso@collabora.com>,
"Christian König" <christian.koenig@amd.com>,
"Intel Graphics Development" <intel-gfx@lists.freedesktop.org>,
"Steven Price" <steven.price@arm.com>,
"moderated list:DMA BUFFER SHARING FRAMEWORK"
<linaro-mm-sig@lists.linaro.org>,
"Alyssa Rosenzweig" <alyssa.rosenzweig@collabora.com>,
"Daniel Vetter" <daniel.vetter@intel.com>,
"open list:DMA BUFFER SHARING FRAMEWORK"
<linux-media@vger.kernel.org>
Subject: Re: [PATCH 04/11] drm/panfrost: Fix implicit sync
Date: Fri, 21 May 2021 13:22:40 +0100 [thread overview]
Message-ID: <CAPj87rMBVRamT+VAVUaUnq3C1KFVqzABi99RKs=1_vyb4YWDnQ@mail.gmail.com> (raw)
In-Reply-To: <20210521090959.1663703-4-daniel.vetter@ffwll.ch>
Hi,
On Fri, 21 May 2021 at 10:10, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Currently this has no practial relevance I think because there's not
> many who can pull off a setup with panfrost and another gpu in the
> same system. But the rules are that if you're setting an exclusive
> fence, indicating a gpu write access in the implicit fencing system,
> then you need to wait for all fences, not just the previous exclusive
> fence.
>
> panfrost against itself has no problem, because it always sets the
> exclusive fence (but that's probably something that will need to be
> fixed for vulkan and/or multi-engine gpus, or you'll suffer badly).
> Also no problem with that against display.
Yeah, the 'second-generation Valhall' GPUs coming later this year /
early next year are starting to get pretty weird. Firmware-mediated
job scheduling out of multiple queues, userspace having direct access
to the queues and can do inter-queue synchronisation (at least I think
so), etc. For bonus points, synchronisation is based on $addr = $val
to signal and $addr == $val to wait, with a separate fence primitive
as well.
Obviously Arm should be part of this conversation here, but I guess
we'll have to wait for a while yet to see how everything's shaken out
with this new gen, and hope that whatever's been designed upstream in
the meantime is actually vaguely compatible ...
Cheers,
Daniel
WARNING: multiple messages have this Message-ID (diff)
From: Daniel Stone <daniel@fooishbar.org>
To: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: "Tomeu Vizoso" <tomeu.vizoso@collabora.com>,
"Intel Graphics Development" <intel-gfx@lists.freedesktop.org>,
"DRI Development" <dri-devel@lists.freedesktop.org>,
"Steven Price" <steven.price@arm.com>,
"moderated list:DMA BUFFER SHARING FRAMEWORK"
<linaro-mm-sig@lists.linaro.org>,
"Alyssa Rosenzweig" <alyssa.rosenzweig@collabora.com>,
"Daniel Vetter" <daniel.vetter@intel.com>,
"Christian König" <christian.koenig@amd.com>,
"open list:DMA BUFFER SHARING FRAMEWORK"
<linux-media@vger.kernel.org>
Subject: Re: [Intel-gfx] [PATCH 04/11] drm/panfrost: Fix implicit sync
Date: Fri, 21 May 2021 13:22:40 +0100 [thread overview]
Message-ID: <CAPj87rMBVRamT+VAVUaUnq3C1KFVqzABi99RKs=1_vyb4YWDnQ@mail.gmail.com> (raw)
In-Reply-To: <20210521090959.1663703-4-daniel.vetter@ffwll.ch>
Hi,
On Fri, 21 May 2021 at 10:10, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Currently this has no practial relevance I think because there's not
> many who can pull off a setup with panfrost and another gpu in the
> same system. But the rules are that if you're setting an exclusive
> fence, indicating a gpu write access in the implicit fencing system,
> then you need to wait for all fences, not just the previous exclusive
> fence.
>
> panfrost against itself has no problem, because it always sets the
> exclusive fence (but that's probably something that will need to be
> fixed for vulkan and/or multi-engine gpus, or you'll suffer badly).
> Also no problem with that against display.
Yeah, the 'second-generation Valhall' GPUs coming later this year /
early next year are starting to get pretty weird. Firmware-mediated
job scheduling out of multiple queues, userspace having direct access
to the queues and can do inter-queue synchronisation (at least I think
so), etc. For bonus points, synchronisation is based on $addr = $val
to signal and $addr == $val to wait, with a separate fence primitive
as well.
Obviously Arm should be part of this conversation here, but I guess
we'll have to wait for a while yet to see how everything's shaken out
with this new gen, and hope that whatever's been designed upstream in
the meantime is actually vaguely compatible ...
Cheers,
Daniel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Daniel Stone <daniel@fooishbar.org>
To: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: "Tomeu Vizoso" <tomeu.vizoso@collabora.com>,
"Intel Graphics Development" <intel-gfx@lists.freedesktop.org>,
"DRI Development" <dri-devel@lists.freedesktop.org>,
"Steven Price" <steven.price@arm.com>,
"moderated list:DMA BUFFER SHARING FRAMEWORK"
<linaro-mm-sig@lists.linaro.org>,
"Alyssa Rosenzweig" <alyssa.rosenzweig@collabora.com>,
"Daniel Vetter" <daniel.vetter@intel.com>,
"Christian König" <christian.koenig@amd.com>,
"open list:DMA BUFFER SHARING FRAMEWORK"
<linux-media@vger.kernel.org>
Subject: Re: [PATCH 04/11] drm/panfrost: Fix implicit sync
Date: Fri, 21 May 2021 13:22:40 +0100 [thread overview]
Message-ID: <CAPj87rMBVRamT+VAVUaUnq3C1KFVqzABi99RKs=1_vyb4YWDnQ@mail.gmail.com> (raw)
In-Reply-To: <20210521090959.1663703-4-daniel.vetter@ffwll.ch>
Hi,
On Fri, 21 May 2021 at 10:10, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Currently this has no practial relevance I think because there's not
> many who can pull off a setup with panfrost and another gpu in the
> same system. But the rules are that if you're setting an exclusive
> fence, indicating a gpu write access in the implicit fencing system,
> then you need to wait for all fences, not just the previous exclusive
> fence.
>
> panfrost against itself has no problem, because it always sets the
> exclusive fence (but that's probably something that will need to be
> fixed for vulkan and/or multi-engine gpus, or you'll suffer badly).
> Also no problem with that against display.
Yeah, the 'second-generation Valhall' GPUs coming later this year /
early next year are starting to get pretty weird. Firmware-mediated
job scheduling out of multiple queues, userspace having direct access
to the queues and can do inter-queue synchronisation (at least I think
so), etc. For bonus points, synchronisation is based on $addr = $val
to signal and $addr == $val to wait, with a separate fence primitive
as well.
Obviously Arm should be part of this conversation here, but I guess
we'll have to wait for a while yet to see how everything's shaken out
with this new gen, and hope that whatever's been designed upstream in
the meantime is actually vaguely compatible ...
Cheers,
Daniel
next prev parent reply other threads:[~2021-05-21 12:22 UTC|newest]
Thread overview: 175+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-21 9:09 [Intel-gfx] [PATCH 01/11] drm/amdgpu: Comply with implicit fencing rules Daniel Vetter
2021-05-21 9:09 ` Daniel Vetter
2021-05-21 9:09 ` [Intel-gfx] [PATCH 02/11] drm/panfrost: Remove sched_lock Daniel Vetter
2021-05-21 9:09 ` Daniel Vetter
2021-05-21 9:32 ` Lucas Stach
2021-05-21 9:32 ` [Intel-gfx] " Lucas Stach
2021-05-21 14:49 ` Daniel Vetter
2021-05-21 14:49 ` Daniel Vetter
2021-05-21 9:09 ` [PATCH 03/11] drm/panfrost: Use xarray and helpers for depedency tracking Daniel Vetter
2021-05-21 9:09 ` Daniel Vetter
2021-05-21 9:09 ` [Intel-gfx] " Daniel Vetter
2021-06-02 14:06 ` Steven Price
2021-06-02 14:06 ` Steven Price
2021-06-02 14:06 ` Steven Price
2021-06-02 18:51 ` Daniel Vetter
2021-06-02 18:51 ` Daniel Vetter
2021-06-02 18:51 ` [Intel-gfx] " Daniel Vetter
2021-06-03 7:48 ` Steven Price
2021-06-03 7:48 ` [Intel-gfx] " Steven Price
2021-06-03 7:48 ` Steven Price
2021-05-21 9:09 ` [PATCH 04/11] drm/panfrost: Fix implicit sync Daniel Vetter
2021-05-21 9:09 ` Daniel Vetter
2021-05-21 9:09 ` [Intel-gfx] " Daniel Vetter
2021-05-21 12:22 ` Daniel Stone [this message]
2021-05-21 12:22 ` Daniel Stone
2021-05-21 12:22 ` [Intel-gfx] " Daniel Stone
2021-05-21 12:28 ` [Intel-gfx] [Linaro-mm-sig] " Christian König
2021-05-21 12:28 ` Christian König
2021-05-21 12:54 ` [Intel-gfx] " Daniel Stone
2021-05-21 12:54 ` Daniel Stone
2021-05-21 12:54 ` Daniel Stone
2021-05-21 13:09 ` Christian König
2021-05-21 13:09 ` Christian König
2021-05-21 13:09 ` [Intel-gfx] " Christian König
2021-05-21 13:23 ` Daniel Stone
2021-05-21 13:23 ` Daniel Stone
2021-05-21 13:23 ` Daniel Stone
2021-05-21 9:09 ` [Intel-gfx] [PATCH 05/11] drm/atomic-helper: make drm_gem_plane_helper_prepare_fb the default Daniel Vetter
2021-05-21 9:09 ` Daniel Vetter
2021-05-21 9:09 ` [Intel-gfx] [PATCH 06/11] drm/<driver>: drm_gem_plane_helper_prepare_fb is now " Daniel Vetter
2021-05-21 9:09 ` Daniel Vetter
2021-05-21 9:09 ` Daniel Vetter
2021-05-21 9:09 ` Daniel Vetter
2021-05-21 9:09 ` Daniel Vetter
2021-05-21 9:09 ` Daniel Vetter
2021-05-21 9:09 ` Daniel Vetter
2021-05-21 9:38 ` Lucas Stach
2021-05-21 9:38 ` Lucas Stach
2021-05-21 9:38 ` Lucas Stach
2021-05-21 9:38 ` Lucas Stach
2021-05-21 9:38 ` Lucas Stach
2021-05-21 9:38 ` Lucas Stach
2021-05-21 9:38 ` [Intel-gfx] " Lucas Stach
2021-05-21 12:20 ` Heiko Stübner
2021-05-21 12:20 ` Heiko Stübner
2021-05-21 12:20 ` [Intel-gfx] " Heiko Stübner
2021-05-21 12:20 ` Heiko Stübner
2021-05-21 12:20 ` Heiko Stübner
2021-05-21 12:20 ` Heiko Stübner
2021-05-21 12:20 ` Heiko Stübner
2021-05-21 12:22 ` Paul Cercueil
2021-05-21 12:22 ` [Intel-gfx] " Paul Cercueil
2021-05-21 12:22 ` Paul Cercueil
2021-05-21 12:22 ` Paul Cercueil
2021-05-21 12:22 ` Paul Cercueil
2021-05-21 12:22 ` Paul Cercueil
2021-05-21 12:22 ` Paul Cercueil
2021-05-21 15:53 ` Jernej Škrabec
2021-05-21 15:53 ` Jernej Škrabec
2021-05-21 15:53 ` [Intel-gfx] " Jernej Škrabec
2021-05-21 15:53 ` Jernej Škrabec
2021-05-21 15:53 ` Jernej Škrabec
2021-05-21 15:53 ` Jernej Škrabec
2021-05-21 15:53 ` Jernej Škrabec
2021-05-21 23:18 ` Chun-Kuang Hu
2021-05-21 23:18 ` Chun-Kuang Hu
2021-05-21 23:18 ` Chun-Kuang Hu
2021-05-21 23:18 ` Chun-Kuang Hu
2021-05-21 23:18 ` Chun-Kuang Hu
2021-05-21 23:18 ` [Intel-gfx] " Chun-Kuang Hu
2021-05-21 23:18 ` Chun-Kuang Hu
2021-05-23 12:17 ` Martin Blumenstingl
2021-05-23 12:17 ` [Intel-gfx] " Martin Blumenstingl
2021-05-23 12:17 ` Martin Blumenstingl
2021-05-23 12:17 ` Martin Blumenstingl
2021-05-23 12:17 ` Martin Blumenstingl
2021-05-23 12:17 ` Martin Blumenstingl
2021-05-23 12:17 ` Martin Blumenstingl
2021-05-24 7:54 ` [Intel-gfx] " Tomi Valkeinen
2021-05-24 7:54 ` Tomi Valkeinen
2021-05-24 7:54 ` Tomi Valkeinen
2021-05-24 7:54 ` Tomi Valkeinen
2021-05-24 7:54 ` Tomi Valkeinen
2021-05-24 7:54 ` Tomi Valkeinen
2021-05-24 7:54 ` Tomi Valkeinen
2021-05-28 9:55 ` [Intel-gfx] " Philippe CORNU
2021-05-28 9:55 ` Philippe CORNU
2021-05-28 9:55 ` Philippe CORNU
2021-05-28 9:55 ` Philippe CORNU
2021-05-28 9:55 ` Philippe CORNU
2021-05-28 9:55 ` Philippe CORNU
2021-05-28 9:55 ` Philippe CORNU
2021-05-21 9:09 ` [Intel-gfx] [PATCH 07/11] drm/armada: Remove prepare/cleanup_fb hooks Daniel Vetter
2021-05-21 9:09 ` Daniel Vetter
2021-05-21 9:09 ` [Intel-gfx] [PATCH 08/11] drm/vram-helpers: Create DRM_GEM_VRAM_PLANE_HELPER_FUNCS Daniel Vetter
2021-05-21 9:09 ` Daniel Vetter
2021-05-21 9:33 ` tiantao (H)
2021-05-21 9:33 ` [Intel-gfx] " tiantao (H)
2021-05-21 9:09 ` [Intel-gfx] [PATCH 09/11] drm/omap: Follow implicit fencing in prepare_fb Daniel Vetter
2021-05-21 9:09 ` Daniel Vetter
2021-05-24 7:53 ` [Intel-gfx] " Tomi Valkeinen
2021-05-24 7:53 ` Tomi Valkeinen
2021-05-21 9:09 ` [Intel-gfx] [PATCH 10/11] drm/simple-helper: drm_gem_simple_display_pipe_prepare_fb as default Daniel Vetter
2021-05-21 9:09 ` Daniel Vetter
2021-05-25 17:48 ` Noralf Trønnes
2021-05-25 17:48 ` [Intel-gfx] " Noralf Trønnes
2021-05-25 17:53 ` Daniel Vetter
2021-05-25 17:53 ` Daniel Vetter
2021-05-21 9:09 ` [Intel-gfx] [PATCH 11/11] drm/tiny: drm_gem_simple_display_pipe_prepare_fb is the default Daniel Vetter
2021-05-21 9:09 ` Daniel Vetter
2021-05-21 9:09 ` Daniel Vetter
2021-05-21 9:09 ` Daniel Vetter
2021-05-21 13:41 ` David Lechner
2021-05-21 13:41 ` David Lechner
2021-05-21 13:41 ` [Intel-gfx] " David Lechner
2021-05-21 13:41 ` David Lechner
2021-05-21 14:09 ` Noralf Trønnes
2021-05-21 14:09 ` [Intel-gfx] " Noralf Trønnes
2021-05-21 14:09 ` Noralf Trønnes
2021-05-21 14:09 ` Noralf Trønnes
2021-05-25 16:05 ` Daniel Vetter
2021-05-25 16:05 ` Daniel Vetter
2021-05-25 16:05 ` Daniel Vetter
2021-05-25 16:05 ` [Intel-gfx] " Daniel Vetter
2021-05-21 14:13 ` Oleksandr Andrushchenko
2021-05-21 14:13 ` [Intel-gfx] " Oleksandr Andrushchenko
2021-05-21 14:13 ` Oleksandr Andrushchenko
2021-05-21 14:13 ` Oleksandr Andrushchenko
2021-05-28 0:38 ` Linus Walleij
2021-05-28 0:38 ` Linus Walleij
2021-05-28 0:38 ` Linus Walleij
2021-05-28 0:38 ` [Intel-gfx] " Linus Walleij
2021-05-21 9:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/11] drm/amdgpu: Comply with implicit fencing rules Patchwork
2021-05-21 9:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-21 9:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-21 9:46 ` [Intel-gfx] [PATCH 01/11] " Bas Nieuwenhuizen
2021-05-21 9:46 ` Bas Nieuwenhuizen
2021-05-21 14:37 ` [Intel-gfx] " Daniel Vetter
2021-05-21 14:37 ` Daniel Vetter
2021-05-21 15:00 ` [Intel-gfx] " Bas Nieuwenhuizen
2021-05-21 15:00 ` Bas Nieuwenhuizen
2021-05-21 15:16 ` [Intel-gfx] " Daniel Vetter
2021-05-21 15:16 ` Daniel Vetter
2021-05-21 18:08 ` [Mesa-dev] " Christian König
2021-05-21 18:08 ` [Intel-gfx] " Christian König
2021-05-21 18:31 ` Daniel Vetter
2021-05-21 18:31 ` Daniel Vetter
2021-05-22 8:30 ` [Intel-gfx] " Christian König
2021-05-22 8:30 ` Christian König
2021-05-25 13:05 ` [Intel-gfx] " Daniel Vetter
2021-05-25 13:05 ` Daniel Vetter
2021-05-25 15:05 ` Christian König
2021-05-25 15:23 ` [Intel-gfx] " Daniel Vetter
2021-05-25 15:23 ` Daniel Vetter
2021-05-26 13:32 ` Christian König
2021-05-26 13:32 ` [Intel-gfx] " Christian König
2021-05-26 13:51 ` Daniel Vetter
2021-05-26 13:51 ` Daniel Vetter
2021-05-21 11:22 ` [Intel-gfx] " Christian König
2021-05-21 11:22 ` Christian König
2021-05-21 14:58 ` [Intel-gfx] [Mesa-dev] " Rob Clark
2021-05-21 14:58 ` Rob Clark
2021-05-21 14:58 ` [Intel-gfx] " Daniel Vetter
2021-05-21 14:58 ` Daniel Vetter
2021-05-23 5:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/11] " Patchwork
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