From: Peter Zijlstra <peterz@infradead.org>
To: Like Xu <like.xu@linux.intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Borislav Petkov <bp@alien8.de>,
Sean Christopherson <seanjc@google.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
weijiang.yang@intel.com, Kan Liang <kan.liang@linux.intel.com>,
ak@linux.intel.com, wei.w.wang@intel.com, eranian@google.com,
liuxiangdong5@huawei.com, linux-kernel@vger.kernel.org,
x86@kernel.org, kvm@vger.kernel.org,
Luwei Kang <luwei.kang@intel.com>
Subject: Re: [PATCH v6 06/16] KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for extended PEBS
Date: Mon, 17 May 2021 10:33:50 +0200 [thread overview]
Message-ID: <YKIqbph62oclxjnt@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20210511024214.280733-7-like.xu@linux.intel.com>
On Tue, May 11, 2021 at 10:42:04AM +0800, Like Xu wrote:
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 2f89fd599842..c791765f4761 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -3898,31 +3898,49 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
> struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
> struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
> u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
> + u64 pebs_mask = (x86_pmu.flags & PMU_FL_PEBS_ALL) ?
> + cpuc->pebs_enabled : (cpuc->pebs_enabled & PEBS_COUNTER_MASK);
> - if (x86_pmu.flags & PMU_FL_PEBS_ALL)
> - arr[0].guest &= ~cpuc->pebs_enabled;
> - else
> - arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
> - *nr = 1;
Instead of endlessly mucking about with branches, do we want something
like this instead?
---
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 2521d03de5e0..bcfba11196c8 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2819,10 +2819,7 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status)
* counters from the GLOBAL_STATUS mask and we always process PEBS
* events via drain_pebs().
*/
- if (x86_pmu.flags & PMU_FL_PEBS_ALL)
- status &= ~cpuc->pebs_enabled;
- else
- status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
+ status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
/*
* PEBS overflow sets bit 62 in the global status register
@@ -3862,10 +3859,7 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
arr[0].host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
arr[0].guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask;
- if (x86_pmu.flags & PMU_FL_PEBS_ALL)
- arr[0].guest &= ~cpuc->pebs_enabled;
- else
- arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
+ arr[0].guest &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
*nr = 1;
if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) {
@@ -5546,6 +5540,7 @@ __init int intel_pmu_init(void)
x86_pmu.events_mask_len = eax.split.mask_length;
x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
+ x86_pmu.pebs_capable = PEBS_COUNTER_MASK;
/*
* Quirk: v2 perfmon does not report fixed-purpose events, so
@@ -5730,6 +5725,7 @@ __init int intel_pmu_init(void)
x86_pmu.pebs_aliases = NULL;
x86_pmu.pebs_prec_dist = true;
x86_pmu.lbr_pt_coexist = true;
+ x86_pmu.pebs_capable = ~0ULL;
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
x86_pmu.flags |= PMU_FL_PEBS_ALL;
x86_pmu.get_event_constraints = glp_get_event_constraints;
@@ -6080,6 +6076,7 @@ __init int intel_pmu_init(void)
x86_pmu.pebs_aliases = NULL;
x86_pmu.pebs_prec_dist = true;
x86_pmu.pebs_block = true;
+ x86_pmu.pebs_capable = ~0ULL;
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
x86_pmu.flags |= PMU_FL_PEBS_ALL;
@@ -6123,6 +6120,7 @@ __init int intel_pmu_init(void)
x86_pmu.pebs_aliases = NULL;
x86_pmu.pebs_prec_dist = true;
x86_pmu.pebs_block = true;
+ x86_pmu.pebs_capable = ~0ULL;
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
x86_pmu.flags |= PMU_FL_PEBS_ALL;
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 27fa85e7d4fd..6f3cf81ccb1b 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -805,6 +805,7 @@ struct x86_pmu {
void (*pebs_aliases)(struct perf_event *event);
unsigned long large_pebs_flags;
u64 rtm_abort_event;
+ u64 pebs_capable;
/*
* Intel LBR
next prev parent reply other threads:[~2021-05-17 8:34 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-11 2:41 [PATCH v6 00/16] KVM: x86/pmu: Add *basic* support to enable guest PEBS via DS Like Xu
2021-05-11 2:41 ` [PATCH v6 01/16] perf/x86/intel: Add EPT-Friendly PEBS for Ice Lake Server Like Xu
2021-05-11 2:42 ` [PATCH v6 02/16] perf/x86/intel: Handle guest PEBS overflow PMI for KVM guest Like Xu
2021-05-17 8:16 ` Peter Zijlstra
2021-05-18 7:38 ` Xu, Like
2021-05-18 8:37 ` Peter Zijlstra
2021-05-11 2:42 ` [PATCH v6 03/16] perf/x86/core: Pass "struct kvm_pmu *" to determine the guest values Like Xu
2021-05-11 2:42 ` [PATCH v6 04/16] KVM: x86/pmu: Set MSR_IA32_MISC_ENABLE_EMON bit when vPMU is enabled Like Xu
2021-05-12 1:58 ` Venkatesh Srinivas
2021-05-12 5:00 ` Xu, Like
2021-05-12 15:18 ` Sean Christopherson
2021-05-13 2:50 ` Xu, Like
2021-05-17 18:43 ` Venkatesh Srinivas
2021-05-17 21:19 ` Sean Christopherson
2021-05-17 21:16 ` Sean Christopherson
2021-05-17 23:51 ` Sean Christopherson
2021-05-18 7:49 ` Xu, Like
2021-05-11 2:42 ` [PATCH v6 05/16] KVM: x86/pmu: Introduce the ctrl_mask value for fixed counter Like Xu
2021-05-17 8:18 ` Peter Zijlstra
2021-05-18 7:55 ` Xu, Like
2021-05-18 8:35 ` Peter Zijlstra
2021-05-11 2:42 ` [PATCH v6 06/16] KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for extended PEBS Like Xu
2021-05-17 8:32 ` Peter Zijlstra
2021-05-18 8:44 ` Xu, Like
2021-05-18 13:42 ` Peter Zijlstra
2021-05-17 8:33 ` Peter Zijlstra [this message]
2021-05-18 8:13 ` Xu, Like
2021-05-11 2:42 ` [PATCH v6 07/16] KVM: x86/pmu: Reprogram PEBS event to emulate guest PEBS counter Like Xu
2021-05-17 8:39 ` Peter Zijlstra
2021-05-17 14:44 ` Andi Kleen
2021-05-18 8:47 ` Peter Zijlstra
2021-05-18 13:15 ` Xu, Like
2021-05-18 15:58 ` Andi Kleen
2021-05-17 9:14 ` Peter Zijlstra
2021-05-18 13:28 ` Xu, Like
2021-05-18 13:36 ` Peter Zijlstra
2021-05-18 14:05 ` Xu, Like
2021-05-11 2:42 ` [PATCH v6 08/16] KVM: x86/pmu: Add IA32_DS_AREA MSR emulation to support guest DS Like Xu
2021-05-12 5:16 ` Xu, Like
2021-05-17 13:26 ` Peter Zijlstra
2021-05-17 14:50 ` Andi Kleen
2021-05-11 2:42 ` [PATCH v6 09/16] KVM: x86/pmu: Add PEBS_DATA_CFG MSR emulation to support adaptive PEBS Like Xu
2021-05-11 2:42 ` [PATCH v6 10/16] KVM: x86: Set PEBS_UNAVAIL in IA32_MISC_ENABLE when PEBS is enabled Like Xu
2021-05-11 2:42 ` [PATCH v6 11/16] KVM: x86/pmu: Adjust precise_ip to emulate Ice Lake guest PDIR counter Like Xu
2021-05-11 2:42 ` [PATCH v6 12/16] KVM: x86/pmu: Move pmc_speculative_in_use() to arch/x86/kvm/pmu.h Like Xu
2021-05-11 2:42 ` [PATCH v6 13/16] KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations Like Xu
2021-05-11 2:42 ` [PATCH v6 14/16] KVM: x86/pmu: Add kvm_pmu_cap to optimize perf_get_x86_pmu_capability Like Xu
2021-05-11 2:42 ` [PATCH v6 15/16] KVM: x86/cpuid: Refactor host/guest CPU model consistency check Like Xu
2021-05-11 2:42 ` [PATCH v6 16/16] KVM: x86/pmu: Expose CPUIDs feature bits PDCM, DS, DTES64 Like Xu
2021-05-15 10:30 ` [PATCH v6 00/16] KVM: x86/pmu: Add *basic* support to enable guest PEBS via DS Liuxiangdong
2021-05-17 6:38 ` Like Xu
2021-05-18 12:23 ` Liuxiangdong
2021-05-18 12:40 ` Xu, Like
2021-05-18 13:15 ` Liuxiangdong
2021-05-19 1:44 ` Liuxiangdong
2021-05-21 1:37 ` Like Xu
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