Re: [Intel-gfx] [PATCH 1/5] drm/i915/display: Limit disabling PSR around cdclk changes to ADL-P

From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
To: "Souza, Jose" <jose.souza@intel.com>,
	"Mun, Gwan-gyeong" <gwan-gyeong.mun@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915/display: Limit disabling PSR around cdclk changes to ADL-P
Date: Thu, 17 Jun 2021 21:26:33 +0000	[thread overview]
Message-ID: <c7b156b9157042bbba5ca3eaadebc9d0@intel.com> (raw)
In-Reply-To: <7bc8fce7e8ac4f444ad927db7c9e177322eac10d.camel@intel.com>

> -----Original Message-----
> From: Souza, Jose <jose.souza@intel.com>
> Sent: Thursday, June 17, 2021 2:18 PM
> To: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915/display: Limit disabling PSR
> around cdclk changes to ADL-P
> 
> On Thu, 2021-06-17 at 14:12 -0700, Anusha Srivatsa wrote:
> > From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> >
> > Only ADL-P platform requires a temporal disabling of PSR for changing
> > the CDCLK PLL frequency with crawling. Changing the CDCLK PLL
> > frequency on prior platforms of ADL-P or changing the CDCLK PLL
> > frequency without crawling on ADL-P don't need to disable of PSR.
> 
> This is only hiding a possible bug found in ICL under the IS_ALDERLAKE_P()
> check.
> There is no reason to not pause PSR in older platforms during cdclck changes.

According to 15729, pausing PSR during cdclk changes is not valid. 

Anusha 
> >
> > Bspec: 49207
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Fixes: 17c1a4b7ac6f ("drm/i915: Disable PSR around cdclk change")
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 22
> > ++++++++++++++++------
> >  1 file changed, 16 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 613ffcc68eba..6da426d26aac 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1962,10 +1962,18 @@ static void intel_set_cdclk(struct
> > drm_i915_private *dev_priv,
> >
> >  	intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
> >
> > -	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> > -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +	/*
> > +	 * Only ADL-P platform requires a temporal disabling of PSR for
> changing
> > +	 * the CDCLK PLL frequency with crawling.
> > +	 * Changing the CDCLK PLL frequency on prior platforms of ADL-P or
> changing
> > +	 * the CDCLK PLL frequency without crawling on ADL-P don't need to
> disable of PSR.
> > +	 */
> > +	if (IS_ALDERLAKE_P(dev_priv)) {
> > +		for_each_intel_encoder_with_psr(&dev_priv->drm,
> encoder) {
> > +			struct intel_dp *intel_dp =
> enc_to_intel_dp(encoder);
> >
> > -		intel_psr_pause(intel_dp);
> > +			intel_psr_pause(intel_dp);
> > +		}
> >  	}
> >
> >  	/*
> > @@ -1990,10 +1998,12 @@ static void intel_set_cdclk(struct
> drm_i915_private *dev_priv,
> >  	}
> >  	mutex_unlock(&dev_priv->gmbus_mutex);
> >
> > -	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> > -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +	if (IS_ALDERLAKE_P(dev_priv)) {
> > +		for_each_intel_encoder_with_psr(&dev_priv->drm,
> encoder) {
> > +			struct intel_dp *intel_dp =
> enc_to_intel_dp(encoder);
> >
> > -		intel_psr_resume(intel_dp);
> > +			intel_psr_resume(intel_dp);
> > +		}
> >  	}
> >
> >  	if (drm_WARN(&dev_priv->drm,

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