From: Dmitry Rokosov <ddrokosov@salutedevices.com> To: <neil.armstrong@linaro.org>, <jbrunet@baylibre.com>, <mturquette@baylibre.com>, <sboyd@kernel.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <khilman@baylibre.com>, <martin.blumenstingl@googlemail.com> Cc: <kernel@salutedevices.com>, <rockosov@gmail.com>, <linux-amlogic@lists.infradead.org>, <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, Dmitry Rokosov <ddrokosov@salutedevices.com> Subject: [PATCH v1 4/4] arm64: dts: amlogic: a1: setup CPU power management Date: Sat, 30 Mar 2024 00:04:42 +0300 [thread overview] Message-ID: <20240329210453.27530-5-ddrokosov@salutedevices.com> (raw) In-Reply-To: <20240329210453.27530-1-ddrokosov@salutedevices.com> The Amlogic A1 SoC family utilizes static operating points and a PWM-controlled core voltage regulator, which is specific to the board. As the main CPU clock input, the SoC uses CLKID_CPU_CLK from the CPU clock controller, which can be inherited from the system PLL (syspll) or a fixed CPU clock. Currently, the stable operating points at all frequencies are set to 800mV. This value is obtained from the vendor setup of several A1 boards. Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 44 +++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index 0de809f4d42c..c57c7c1cd5f8 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -33,6 +33,13 @@ cpu0: cpu@0 { reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&clkc_cpu CLKID_CPU_CLK>; + clock-names = "core_clk"; + operating-points-v2 = <&cpu_opp_table0>; + voltage-tolerance = <0>; + clock-latency = <50000>; + capacity-dmips-mhz = <400>; + dynamic-power-coefficient = <80>; #cooling-cells = <2>; }; @@ -42,6 +49,13 @@ cpu1: cpu@1 { reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&clkc_cpu CLKID_CPU_CLK>; + clock-names = "core_clk"; + operating-points-v2 = <&cpu_opp_table0>; + voltage-tolerance = <0>; + clock-latency = <50000>; + capacity-dmips-mhz = <400>; + dynamic-power-coefficient = <80>; #cooling-cells = <2>; }; @@ -52,6 +66,36 @@ l2: l2-cache0 { }; }; + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <128000000>; + opp-microvolt = <800000>; + }; + opp01 { + opp-hz = /bits/ 64 <256000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <512000000>; + opp-microvolt = <800000>; + }; + opp03 { + opp-hz = /bits/ 64 <768000000>; + opp-microvolt = <800000>; + }; + opp04 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <800000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <800000>; + }; + }; + efuse: efuse { compatible = "amlogic,meson-gxbb-efuse"; clocks = <&clkc_periphs CLKID_OTP>; -- 2.43.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Rokosov <ddrokosov@salutedevices.com> To: <neil.armstrong@linaro.org>, <jbrunet@baylibre.com>, <mturquette@baylibre.com>, <sboyd@kernel.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <khilman@baylibre.com>, <martin.blumenstingl@googlemail.com> Cc: <kernel@salutedevices.com>, <rockosov@gmail.com>, <linux-amlogic@lists.infradead.org>, <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, Dmitry Rokosov <ddrokosov@salutedevices.com> Subject: [PATCH v1 4/4] arm64: dts: amlogic: a1: setup CPU power management Date: Sat, 30 Mar 2024 00:04:42 +0300 [thread overview] Message-ID: <20240329210453.27530-5-ddrokosov@salutedevices.com> (raw) Message-ID: <20240329210442.jvq5lKVdGazqdPSzP2Tc2riNZM88GpPnpo9iaIQvyNs@z> (raw) In-Reply-To: <20240329210453.27530-1-ddrokosov@salutedevices.com> The Amlogic A1 SoC family utilizes static operating points and a PWM-controlled core voltage regulator, which is specific to the board. As the main CPU clock input, the SoC uses CLKID_CPU_CLK from the CPU clock controller, which can be inherited from the system PLL (syspll) or a fixed CPU clock. Currently, the stable operating points at all frequencies are set to 800mV. This value is obtained from the vendor setup of several A1 boards. Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 44 +++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index 0de809f4d42c..c57c7c1cd5f8 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -33,6 +33,13 @@ cpu0: cpu@0 { reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&clkc_cpu CLKID_CPU_CLK>; + clock-names = "core_clk"; + operating-points-v2 = <&cpu_opp_table0>; + voltage-tolerance = <0>; + clock-latency = <50000>; + capacity-dmips-mhz = <400>; + dynamic-power-coefficient = <80>; #cooling-cells = <2>; }; @@ -42,6 +49,13 @@ cpu1: cpu@1 { reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&clkc_cpu CLKID_CPU_CLK>; + clock-names = "core_clk"; + operating-points-v2 = <&cpu_opp_table0>; + voltage-tolerance = <0>; + clock-latency = <50000>; + capacity-dmips-mhz = <400>; + dynamic-power-coefficient = <80>; #cooling-cells = <2>; }; @@ -52,6 +66,36 @@ l2: l2-cache0 { }; }; + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <128000000>; + opp-microvolt = <800000>; + }; + opp01 { + opp-hz = /bits/ 64 <256000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <512000000>; + opp-microvolt = <800000>; + }; + opp03 { + opp-hz = /bits/ 64 <768000000>; + opp-microvolt = <800000>; + }; + opp04 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <800000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <800000>; + }; + }; + efuse: efuse { compatible = "amlogic,meson-gxbb-efuse"; clocks = <&clkc_periphs CLKID_OTP>; -- 2.43.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic
next prev parent reply other threads:[~2024-03-29 21:05 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <20240329210453.27530-1-ddrokosov@salutedevices.com> 2024-03-29 21:04 ` [PATCH v1 1/4] arm64: dts: amlogic: a1: add new syspll_in input for clkc_pll controller Dmitry Rokosov 2024-03-29 21:04 ` [PATCH v1 2/4] arm64: dts: amlogic: a1: declare cpu clock controller Dmitry Rokosov 2024-03-29 21:04 ` [PATCH v1 3/4] arm64: dts: amlogic: a1: add new input clock 'sys_pll_div16' to clkc_periphs Dmitry Rokosov 2024-03-29 21:04 ` Dmitry Rokosov [this message] 2024-03-29 21:04 ` [PATCH v1 4/4] arm64: dts: amlogic: a1: setup CPU power management Dmitry Rokosov
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