From: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
To: Abel Vesa <abelvesa@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>, Jacky Bai <ping.bai@nxp.com>,
Ye Li <ye.li@nxp.com>, Dong Aisheng <aisheng.dong@nxp.com>
Cc: linux-clk@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Abel Vesa <abel.vesa@linaro.org>,
Peng Fan <peng.fan@nxp.com>
Subject: [PATCH 10/18] clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D
Date: Sat, 04 May 2024 08:49:03 +0800 [thread overview]
Message-ID: <20240504-imx-clk-v1-10-f7915489d58d@nxp.com> (raw)
In-Reply-To: <20240504-imx-clk-v1-0-f7915489d58d@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
For i.MX7D DRAM related mux clock, the clock source change should ONLY
be done done in low level asm code without accessing DRAM, and then
calling clk API to sync the HW clock status with clk tree, it should never
touch real clock source switch via clk API, so CLK_SET_PARENT_GATE flag
should NOT be added, otherwise, DRAM's clock parent will be disabled when
DRAM is active, and system will hang.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-imx7d.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 2b77d1fc7bb9..1e1296e74835 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -498,9 +498,9 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
hws[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_hw_mux2_flags("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel), CLK_SET_PARENT_GATE);
hws[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_hw_mux2_flags("nand_usdhc_src", base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel), CLK_SET_PARENT_GATE);
hws[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_phym_src", base + 0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel), CLK_SET_PARENT_GATE);
- hws[IMX7D_DRAM_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel), CLK_SET_PARENT_GATE);
+ hws[IMX7D_DRAM_ROOT_SRC] = imx_clk_hw_mux2("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel));
hws[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_phym_alt_src", base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel), CLK_SET_PARENT_GATE);
- hws[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel), CLK_SET_PARENT_GATE);
+ hws[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_hw_mux2("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel));
hws[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_hw_mux2_flags("usb_hsic_src", base + 0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel), CLK_SET_PARENT_GATE);
hws[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel), CLK_SET_PARENT_GATE);
hws[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel), CLK_SET_PARENT_GATE);
--
2.37.1
next prev parent reply other threads:[~2024-05-04 0:42 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-04 0:48 [PATCH 00/18] clk: imx: misc update/fix Peng Fan (OSS)
2024-05-04 0:48 ` [PATCH 01/18] clk: imx: composite-8m: Enable gate clk with mcore_booted Peng Fan (OSS)
2024-05-04 0:48 ` [PATCH 02/18] clk: imx: composite-93: keep root clock on when mcore enabled Peng Fan (OSS)
2024-05-04 0:48 ` [PATCH 03/18] clk: imx: composite-7ulp: Check the PCC present bit Peng Fan (OSS)
2024-05-04 0:48 ` [PATCH 04/18] clk: imx: fracn-gppll: fix fractional part of PLL getting lost Peng Fan (OSS)
2024-05-04 0:48 ` [PATCH 05/18] clk: imx: pll14xx: Add constraint for fvco frequency Peng Fan (OSS)
2024-05-04 0:48 ` [PATCH 06/18] clk: imx: pll14xx: use rate_table for audio plls Peng Fan (OSS)
2024-05-16 12:18 ` Adam Ford
2024-05-04 0:49 ` [PATCH 07/18] clk: imx: pll14xx: potential integer overflow eliminated by casting to u64 Peng Fan (OSS)
2024-05-04 11:58 ` Francesco Dolcini
2024-05-04 13:13 ` Peng Fan
2024-05-04 0:49 ` [PATCH 08/18] clk: imx: imx8mp-audiomix: remove sdma root clock Peng Fan (OSS)
2024-05-04 11:59 ` Francesco Dolcini
2024-05-04 13:15 ` Peng Fan
2024-05-04 0:49 ` [PATCH 09/18] clk: imx: imx8mp: fix clock tree update of TF-A managed clocks Peng Fan (OSS)
2024-05-04 0:49 ` Peng Fan (OSS) [this message]
2024-05-04 12:01 ` [PATCH 10/18] clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D Francesco Dolcini
2024-05-04 13:15 ` Peng Fan
2024-05-04 0:49 ` [PATCH 11/18] clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src " Peng Fan (OSS)
2024-05-04 0:49 ` [PATCH 12/18] clk: imx: imx8mn: add sai7_ipg_clk clock settings Peng Fan (OSS)
2024-05-04 0:49 ` [PATCH 13/18] clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one Peng Fan (OSS)
2024-05-04 0:49 ` [PATCH 14/18] clk: imx: imx8qxp: Add LVDS bypass clocks Peng Fan (OSS)
2024-05-04 0:49 ` [PATCH 15/18] clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks Peng Fan (OSS)
2024-05-04 0:49 ` [PATCH 16/18] clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk Peng Fan (OSS)
2024-05-04 0:49 ` [PATCH 17/18] clk: imx: imx8qxp: Parent should be initialized earlier than the clock Peng Fan (OSS)
2024-05-04 0:49 ` [PATCH 18/18] clk: imx: fracn-gppll: update rate table Peng Fan (OSS)
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