From: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
To: Abel Vesa <abelvesa@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>, Jacky Bai <ping.bai@nxp.com>,
Ye Li <ye.li@nxp.com>, Dong Aisheng <aisheng.dong@nxp.com>
Cc: linux-clk@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Abel Vesa <abel.vesa@linaro.org>,
Peng Fan <peng.fan@nxp.com>,
Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>,
"Oliver F. Brown" <oliver.brown@oss.nxp.com>
Subject: [PATCH 14/18] clk: imx: imx8qxp: Add LVDS bypass clocks
Date: Sat, 04 May 2024 08:49:07 +0800 [thread overview]
Message-ID: <20240504-imx-clk-v1-14-f7915489d58d@nxp.com> (raw)
In-Reply-To: <20240504-imx-clk-v1-0-f7915489d58d@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
For iMX8QXP and iMX8QM, add bypass clocks and register some of the LVDS
clocks with imx_clk_scu2 as the parent needs to explicitly set.
In order to make sure MIPI DSI works well after suspend/resume, the LVDS
pixel and phy clocks must be initialized before the MIPI tx_esacpe
and rx_escape clocks. LVDS phy, LVDS pixel, tx_escape, and rx_esacpe are all
on the same MSLICE. They all share the same clock parent. So, setting the
parent source or rate affects all of these clocks. In the LVDS use case the
MIPI tx_escape and rx_escape are not saved and restored. So, LVDS works for
either clock initialization order. For MIPI case, LVDS must be initialized first.
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Oliver F. Brown <oliver.brown@oss.nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-imx8qxp.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index 7d8883916cac..a0654edaae83 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -71,7 +71,7 @@ static const char *const lvds0_sels[] = {
"clk_dummy",
"clk_dummy",
"clk_dummy",
- "mipi0_lvds_bypass_clk",
+ "lvds0_bypass_clk",
};
static const char *const lvds1_sels[] = {
@@ -79,7 +79,7 @@ static const char *const lvds1_sels[] = {
"clk_dummy",
"clk_dummy",
"clk_dummy",
- "mipi1_lvds_bypass_clk",
+ "lvds1_bypass_clk",
};
static const char * const mipi_sels[] = {
@@ -223,9 +223,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
/* MIPI-LVDS SS */
imx_clk_scu("mipi0_bypass_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("mipi0_pixel_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER);
- imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS);
- imx_clk_scu2("mipi0_lvds_pixel_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2);
- imx_clk_scu2("mipi0_lvds_phy_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3);
+ imx_clk_scu("lvds0_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS);
+ imx_clk_scu2("lvds0_pixel_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2);
+ imx_clk_scu2("lvds0_phy_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3);
imx_clk_scu2("mipi0_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_MST_BUS);
imx_clk_scu2("mipi0_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_SLV_BUS);
imx_clk_scu2("mipi0_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY);
@@ -235,10 +235,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
imx_clk_scu("mipi1_bypass_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("mipi1_pixel_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER);
- imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS);
- imx_clk_scu2("mipi1_lvds_pixel_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2);
- imx_clk_scu2("mipi1_lvds_phy_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3);
-
+ imx_clk_scu("lvds1_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS);
+ imx_clk_scu2("lvds1_pixel_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2);
+ imx_clk_scu2("lvds1_phy_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3);
imx_clk_scu2("mipi1_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_MST_BUS);
imx_clk_scu2("mipi1_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_SLV_BUS);
imx_clk_scu2("mipi1_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PHY);
--
2.37.1
next prev parent reply other threads:[~2024-05-04 0:42 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-04 0:48 [PATCH 00/18] clk: imx: misc update/fix Peng Fan (OSS)
2024-05-04 0:48 ` [PATCH 01/18] clk: imx: composite-8m: Enable gate clk with mcore_booted Peng Fan (OSS)
2024-05-04 0:48 ` [PATCH 02/18] clk: imx: composite-93: keep root clock on when mcore enabled Peng Fan (OSS)
2024-05-04 0:48 ` [PATCH 03/18] clk: imx: composite-7ulp: Check the PCC present bit Peng Fan (OSS)
2024-05-04 0:48 ` [PATCH 04/18] clk: imx: fracn-gppll: fix fractional part of PLL getting lost Peng Fan (OSS)
2024-05-04 0:48 ` [PATCH 05/18] clk: imx: pll14xx: Add constraint for fvco frequency Peng Fan (OSS)
2024-05-04 0:48 ` [PATCH 06/18] clk: imx: pll14xx: use rate_table for audio plls Peng Fan (OSS)
2024-05-16 12:18 ` Adam Ford
2024-05-04 0:49 ` [PATCH 07/18] clk: imx: pll14xx: potential integer overflow eliminated by casting to u64 Peng Fan (OSS)
2024-05-04 11:58 ` Francesco Dolcini
2024-05-04 13:13 ` Peng Fan
2024-05-04 0:49 ` [PATCH 08/18] clk: imx: imx8mp-audiomix: remove sdma root clock Peng Fan (OSS)
2024-05-04 11:59 ` Francesco Dolcini
2024-05-04 13:15 ` Peng Fan
2024-05-04 0:49 ` [PATCH 09/18] clk: imx: imx8mp: fix clock tree update of TF-A managed clocks Peng Fan (OSS)
2024-05-04 0:49 ` [PATCH 10/18] clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D Peng Fan (OSS)
2024-05-04 12:01 ` Francesco Dolcini
2024-05-04 13:15 ` Peng Fan
2024-05-04 0:49 ` [PATCH 11/18] clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src " Peng Fan (OSS)
2024-05-04 0:49 ` [PATCH 12/18] clk: imx: imx8mn: add sai7_ipg_clk clock settings Peng Fan (OSS)
2024-05-04 0:49 ` [PATCH 13/18] clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one Peng Fan (OSS)
2024-05-04 0:49 ` Peng Fan (OSS) [this message]
2024-05-04 0:49 ` [PATCH 15/18] clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks Peng Fan (OSS)
2024-05-04 0:49 ` [PATCH 16/18] clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk Peng Fan (OSS)
2024-05-04 0:49 ` [PATCH 17/18] clk: imx: imx8qxp: Parent should be initialized earlier than the clock Peng Fan (OSS)
2024-05-04 0:49 ` [PATCH 18/18] clk: imx: fracn-gppll: update rate table Peng Fan (OSS)
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