From: Manivannan Sadhasivam <mani@kernel.org>
To: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
Cc: agross@kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, quic_msarkar@quicinc.com,
quic_kraravin@quicinc.com,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Serge Semin" <fancer.lancer@gmail.com>,
"Yoshihiro Shimoda" <yoshihiro.shimoda.uh@renesas.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
linux-arm-msm@vger.kernel.org
Subject: Re: [PATCH v3 2/3] PCI: qcom: Add equalization settings for 16GT/s
Date: Mon, 22 Apr 2024 20:46:25 +0530 [thread overview]
Message-ID: <20240422151625.GG9775@thinkpad> (raw)
In-Reply-To: <20240419001013.28788-3-quic_schintav@quicinc.com>
On Thu, Apr 18, 2024 at 05:09:35PM -0700, Shashank Babu Chinta Venkata wrote:
PCI: qcom: Add PCIe link equalization settings for 16 GT/s
> GEN3_RELATED_OFFSET is being used to determine data rate of shadow
> registers. Select data rate as 16GT/s and set appropriate equilization
> settings to improve link stability for 16GT/s data rate.
>
How about:
'To improve the PCIe link stability while running at the rate of 16 GT/s, set
the appropriate link equalization settings for both RC and EP controllers.'
However, I don't understand the statement about 'GEN3_RELATED_OFFSET' and
'shadow registers'. Please reword it to make it understandable.
> Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
> ---
> drivers/pci/controller/dwc/pcie-designware.h | 12 ++++++++
> drivers/pci/controller/dwc/pcie-qcom-common.c | 30 +++++++++++++++++++
> drivers/pci/controller/dwc/pcie-qcom-common.h | 1 +
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 3 ++
> drivers/pci/controller/dwc/pcie-qcom.c | 3 ++
> 5 files changed, 49 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 26dae4837462..ad771bb52d29 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -122,6 +122,18 @@
> #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
> #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
>
> +#define GEN3_EQ_CONTROL_OFF 0x8a8
> +#define GEN3_EQ_CONTROL_OFF_FB_MODE(n) FIELD_PREP(GENMASK(3, 0), n)
> +#define GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE(n) FIELD_PREP(BIT(4), n)
> +#define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC(n) FIELD_PREP(GENMASK(23, 8), n)
> +#define GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL(n) FIELD_PREP(BIT(24), n)
> +
> +#define GEN3_EQ_FB_MODE_DIR_CHANGE_OFF 0x8ac
> +#define GEN3_EQ_FMDC_T_MIN_PHASE23(n) FIELD_PREP(GENMASK(4, 0), n)
> +#define GEN3_EQ_FMDC_N_EVALS(n) FIELD_PREP(GENMASK(9, 5), n)
> +#define GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA(n) FIELD_PREP(GENMASK(13, 10), n)
> +#define GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA(n) FIELD_PREP(GENMASK(17, 14), n)
> +
> #define PCIE_PORT_MULTI_LANE_CTRL 0x8C0
> #define PORT_MLTI_UPCFG_SUPPORT BIT(7)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c
> index dc2120ec5fef..a6f3eb4c3ee6 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-common.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c
> @@ -16,6 +16,36 @@
> #define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \
> Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]))
>
> +void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci)
> +{
> + u32 reg;
> +
> + /*
> + * GEN3_RELATED_OFF is repurposed to be used with GEN4(16GT/s) rate
> + * as well based on RATE_SHADOW_SEL_MASK settings on this register.
Same comment as above.
> + */
> + reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
> + reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
> + reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
> + reg |= (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT);
Use FIELD_PREP()
> + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg);
> +
> + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF);
> + reg = GEN3_EQ_FMDC_T_MIN_PHASE23(0) |
You are reading 'reg' above and then overwriting immediately.
> + GEN3_EQ_FMDC_N_EVALS(0xD) |
'0xd'
> + GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA(0x5) |
> + GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA(0x5);
> + dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg);
> +
> + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
> + reg = GEN3_EQ_CONTROL_OFF_FB_MODE(0) |
Same as above.
- Mani
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2024-04-22 15:16 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-19 0:09 [PATCH v3 0/3] Add 16GT/s equalization and margining settings Shashank Babu Chinta Venkata
2024-04-19 0:09 ` [PATCH v3 1/3] PCI: qcom: Refactor common code Shashank Babu Chinta Venkata
2024-04-22 14:58 ` Manivannan Sadhasivam
2024-04-19 0:09 ` [PATCH v3 2/3] PCI: qcom: Add equalization settings for 16GT/s Shashank Babu Chinta Venkata
2024-04-22 15:16 ` Manivannan Sadhasivam [this message]
2024-04-22 22:59 ` Konrad Dybcio
2024-04-19 0:09 ` [PATCH v3 3/3] PCI: qcom: Add rx margining " Shashank Babu Chinta Venkata
2024-04-22 15:20 ` Manivannan Sadhasivam
2024-04-22 22:58 ` Konrad Dybcio
2024-04-30 20:37 ` Shashank Babu Chinta Venkata
2024-05-01 23:13 ` Konrad Dybcio
2024-04-19 7:36 ` [PATCH v3 0/3] Add 16GT/s equalization and margining settings Niklas Cassel
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