From: guoren@kernel.org
To: guoren@kernel.org, palmer@dabbelt.com, arnd@arndb.de,
anup.patel@wdc.com, gregkh@linuxfoundation.org,
liush@allwinnertech.com, wefu@redhat.com, drew@beagleboard.org,
wangjunqiang@iscas.ac.cn, lazyparser@gmail.com
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-csky@vger.kernel.org, Guo Ren <guoren@linux.alibaba.com>
Subject: [PATCH 07/13] riscv: compat: Add elf.h implementation
Date: Wed, 22 Dec 2021 00:35:26 +0800 [thread overview]
Message-ID: <20211221163532.2636028-8-guoren@kernel.org> (raw)
In-Reply-To: <20211221163532.2636028-1-guoren@kernel.org>
From: Guo Ren <guoren@linux.alibaba.com>
Implement necessary type and macro for compat elf. See the code
comment for detail.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
---
arch/riscv/include/asm/elf.h | 42 +++++++++++++++++++++++++++++++++++-
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h
index f53c40026c7a..48c116f3c12d 100644
--- a/arch/riscv/include/asm/elf.h
+++ b/arch/riscv/include/asm/elf.h
@@ -8,6 +8,8 @@
#ifndef _ASM_RISCV_ELF_H
#define _ASM_RISCV_ELF_H
+#include <uapi/linux/elf.h>
+#include <linux/compat.h>
#include <uapi/asm/elf.h>
#include <asm/auxvec.h>
#include <asm/byteorder.h>
@@ -18,11 +20,13 @@
*/
#define ELF_ARCH EM_RISCV
+#ifndef ELF_CLASS
#ifdef CONFIG_64BIT
#define ELF_CLASS ELFCLASS64
#else
#define ELF_CLASS ELFCLASS32
#endif
+#endif
#define ELF_DATA ELFDATA2LSB
@@ -31,6 +35,8 @@
*/
#define elf_check_arch(x) ((x)->e_machine == EM_RISCV)
+#define compat_elf_check_arch(x) ((x)->e_machine == EM_RISCV)
+
#define CORE_DUMP_USE_REGSET
#define ELF_EXEC_PAGESIZE (PAGE_SIZE)
@@ -43,8 +49,14 @@
#define ELF_ET_DYN_BASE ((TASK_SIZE / 3) * 2)
#ifdef CONFIG_64BIT
+#ifdef CONFIG_COMPAT
+#define STACK_RND_MASK (test_thread_flag(TIF_32BIT) ? \
+ 0x7ff >> (PAGE_SHIFT - 12) : \
+ 0x3ffff >> (PAGE_SHIFT - 12))
+#else
#define STACK_RND_MASK (0x3ffff >> (PAGE_SHIFT - 12))
#endif
+#endif
/*
* This yields a mask that user programs can use to figure out what
* instruction set this CPU supports. This could be done in user space,
@@ -60,11 +72,19 @@ extern unsigned long elf_hwcap;
*/
#define ELF_PLATFORM (NULL)
+#define COMPAT_ELF_PLATFORM (NULL)
+
#ifdef CONFIG_MMU
#define ARCH_DLINFO \
do { \
+ /* \
+ * Note that we add ulong after elf_addr_t because \
+ * casting current->mm->context.vdso triggers a cast \
+ * warning of cast from pointer to integer for \
+ * COMPAT ELFCLASS32. \
+ */ \
NEW_AUX_ENT(AT_SYSINFO_EHDR, \
- (elf_addr_t)current->mm->context.vdso); \
+ (elf_addr_t)(ulong)current->mm->context.vdso); \
NEW_AUX_ENT(AT_L1I_CACHESIZE, \
get_cache_size(1, CACHE_TYPE_INST)); \
NEW_AUX_ENT(AT_L1I_CACHEGEOMETRY, \
@@ -90,4 +110,24 @@ do { \
*(struct user_regs_struct *)regs; \
} while (0);
+#ifdef CONFIG_COMPAT
+
+/*
+ * FIXME: not sure SET_PERSONALITY for compat process is right!
+ */
+#define SET_PERSONALITY(ex) \
+do { if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
+ set_thread_flag(TIF_32BIT); \
+ else \
+ clear_thread_flag(TIF_32BIT); \
+ set_personality(PER_LINUX | (current->personality & (~PER_MASK))); \
+} while (0)
+
+#define COMPAT_ELF_ET_DYN_BASE ((TASK_SIZE_32 / 3) * 2)
+
+/* rv32 registers */
+typedef compat_ulong_t compat_elf_greg_t;
+typedef compat_elf_greg_t compat_elf_gregset_t[ELF_NGREG];
+
+#endif /* CONFIG_COMPAT */
#endif /* _ASM_RISCV_ELF_H */
--
2.25.1
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next prev parent reply other threads:[~2021-12-21 16:36 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-21 16:35 [PATCH 00/13] riscv: compat: Add COMPAT mode support for rv64 guoren
2021-12-21 16:35 ` [PATCH 01/13] syscalls: compat: Fix the missing part for __SYSCALL_COMPAT guoren
2021-12-21 17:08 ` Arnd Bergmann
2021-12-22 11:16 ` Guo Ren
2021-12-22 11:24 ` Arnd Bergmann
2021-12-24 6:52 ` Christoph Hellwig
2021-12-21 16:35 ` [PATCH 02/13] riscv: Fixup difference with defconfig guoren
2021-12-21 17:09 ` Arnd Bergmann
2021-12-22 11:34 ` Guo Ren
2021-12-22 11:44 ` Arnd Bergmann
2021-12-22 13:06 ` Guo Ren
2021-12-22 13:30 ` Arnd Bergmann
2021-12-23 2:12 ` Guo Ren
2021-12-21 16:35 ` [PATCH 03/13] riscv: compat: Add basic compat date type implementation guoren
2021-12-21 17:12 ` Arnd Bergmann
2021-12-22 12:03 ` Guo Ren
2021-12-22 12:46 ` Arnd Bergmann
2021-12-26 15:33 ` Guo Ren
2021-12-24 6:53 ` Christoph Hellwig
2021-12-24 9:28 ` Guo Ren
2021-12-21 16:35 ` [PATCH 04/13] riscv: compat: Re-implement TASK_SIZE for COMPAT_32BIT guoren
2021-12-21 16:35 ` [PATCH 05/13] riscv: compat: syscall: Add compat_sys_call_table implementation guoren
2021-12-21 17:15 ` Arnd Bergmann
2021-12-22 12:43 ` Guo Ren
2021-12-22 13:21 ` Arnd Bergmann
2021-12-22 14:00 ` Arnd Bergmann
2021-12-24 9:42 ` Guo Ren
2021-12-21 16:35 ` [PATCH 06/13] riscv: compat: syscall: Add entry.S implementation guoren
2021-12-21 16:35 ` guoren [this message]
2021-12-21 16:35 ` [PATCH 08/13] riscv: compat: Add COMPAT Kbuild skeletal support guoren
2021-12-21 17:21 ` Arnd Bergmann
2021-12-22 12:06 ` Guo Ren
2021-12-24 6:54 ` Christoph Hellwig
2021-12-21 16:35 ` [PATCH 09/13] riscv: compat: init: Add hw-cap detect in setup_arch guoren
2021-12-21 16:35 ` [PATCH 10/13] riscv: compat: vdso: Add rv32 VDSO base code implementation guoren
2021-12-21 16:35 ` [PATCH 11/13] riscv: compat: vdso: Add setup additional pages implementation guoren
2021-12-21 16:35 ` [PATCH 12/13] riscv: compat: signal: Add rt_frame implementation guoren
2021-12-21 16:35 ` [PATCH 13/13] riscv: compat: ptrace: Add compat_arch_ptrace implement guoren
2021-12-21 17:38 ` [PATCH 00/13] riscv: compat: Add COMPAT mode support for rv64 Arnd Bergmann
2021-12-22 12:59 ` Guo Ren
2021-12-22 13:29 ` Arnd Bergmann
2021-12-26 8:22 ` Jisheng Zhang
2021-12-26 12:38 ` Guo Ren
2021-12-26 20:31 ` Arnd Bergmann
2021-12-27 1:16 ` Guo Ren
2021-12-27 2:29 ` Jessica Clarke
2021-12-28 10:45 ` Guo Ren
2021-12-22 12:00 ` Guo Ren
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