From: Charlie Jenkins <charlie@rivosinc.com>
To: "Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Palmer Dabbelt <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org,
Charlie Jenkins <charlie@rivosinc.com>
Subject: [PATCH 15/19] riscv: hwcap: Add v to hwcap if xtheadvector enabled
Date: Thu, 11 Apr 2024 21:11:21 -0700 [thread overview]
Message-ID: <20240411-dev-charlie-support_thead_vector_6_9-v1-15-4af9815ec746@rivosinc.com> (raw)
In-Reply-To: <20240411-dev-charlie-support_thead_vector_6_9-v1-0-4af9815ec746@rivosinc.com>
xtheadvector is not vector 1.0 compatible, but it can leverage all of
the same save/restore routines as vector plus
riscv_v_first_use_handler(). vector 1.0 and xtheadvector are mutually
exclusive so there is no risk of overlap.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
arch/riscv/kernel/cpufeature.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 41a4d2028428..59f628b1341c 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -647,9 +647,13 @@ static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap)
* Many vendors with T-Head CPU cores which implement the 0.7.1
* version of the vector specification put "v" into their DTs.
* CPU cores with the ratified spec will contain non-zero
- * marchid.
+ * marchid. Only allow "v" to be set if xtheadvector is present.
*/
- if (acpi_disabled && this_vendorid == THEAD_VENDOR_ID &&
+ if (__riscv_isa_vendor_extension_available(isavendorinfo->isa,
+ RISCV_ISA_VENDOR_EXT_XTHEADVECTOR)) {
+ this_hwcap |= isa2hwcap[RISCV_ISA_EXT_v];
+ set_bit(RISCV_ISA_EXT_v, isainfo->isa);
+ } else if (acpi_disabled && this_vendorid == THEAD_VENDOR_ID &&
this_archid == 0x0) {
this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_v];
clear_bit(RISCV_ISA_EXT_v, isainfo->isa);
@@ -776,6 +780,15 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap)
of_node_put(cpu_node);
+ /*
+ * Enable kernel vector routines if xtheadvector is present
+ */
+ if (__riscv_isa_vendor_extension_available(isavendorinfo->isa,
+ RISCV_ISA_VENDOR_EXT_XTHEADVECTOR)) {
+ this_hwcap |= isa2hwcap[RISCV_ISA_EXT_v];
+ set_bit(RISCV_ISA_EXT_v, isainfo->isa);
+ }
+
/*
* All "okay" harts should have same isa. Set HWCAP based on
* common capabilities of every "okay" hart, in case they don't.
--
2.44.0
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-04-12 4:15 UTC|newest]
Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-12 4:11 [PATCH 00/19] riscv: Support vendor extensions and xtheadvector Charlie Jenkins
2024-04-12 4:11 ` [PATCH 01/19] dt-bindings: riscv: Add vendorid and archid Charlie Jenkins
2024-04-12 9:57 ` Conor Dooley
2024-04-12 4:11 ` [PATCH 02/19] riscv: cpufeature: Fix thead vector hwcap removal Charlie Jenkins
2024-04-12 10:25 ` Conor Dooley
2024-04-12 17:04 ` Evan Green
2024-04-12 18:38 ` Conor Dooley
2024-04-12 18:46 ` Charlie Jenkins
2024-04-12 19:26 ` Conor Dooley
2024-04-12 20:34 ` Charlie Jenkins
2024-04-12 20:42 ` Conor Dooley
2024-04-12 17:12 ` Charlie Jenkins
2024-04-12 18:47 ` Conor Dooley
2024-04-12 20:48 ` Charlie Jenkins
2024-04-12 21:27 ` Conor Dooley
2024-04-12 21:31 ` Charlie Jenkins
2024-04-12 23:40 ` Conor Dooley
2024-04-16 3:34 ` Charlie Jenkins
2024-04-16 7:36 ` Conor Dooley
2024-04-17 4:25 ` Charlie Jenkins
2024-04-17 16:02 ` Evan Green
2024-04-17 22:02 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 03/19] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-04-12 10:27 ` Conor Dooley
2024-04-12 17:13 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 04/19] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-04-12 4:11 ` [PATCH 05/19] riscv: Fix extension subset checking Charlie Jenkins
2024-04-12 11:25 ` Conor Dooley
2024-04-12 4:11 ` [PATCH 06/19] riscv: Extend cpufeature.c to detect vendor extensions Charlie Jenkins
2024-04-12 12:30 ` Conor Dooley
2024-04-12 16:58 ` Charlie Jenkins
2024-04-12 18:59 ` Conor Dooley
2024-04-12 14:44 ` kernel test robot
2024-04-13 22:10 ` kernel test robot
2024-04-12 4:11 ` [PATCH 07/19] riscv: Optimize riscv_cpu_isa_extension_(un)likely() Charlie Jenkins
2024-04-12 10:40 ` Conor Dooley
2024-04-12 17:34 ` Charlie Jenkins
2024-04-12 20:33 ` Conor Dooley
2024-04-12 4:11 ` [PATCH 08/19] riscv: Introduce vendor variants of extension helpers Charlie Jenkins
2024-04-12 11:49 ` Conor Dooley
2024-04-12 17:43 ` Charlie Jenkins
2024-04-12 20:40 ` Conor Dooley
2024-04-12 21:03 ` Charlie Jenkins
2024-04-12 21:34 ` Conor Dooley
2024-04-12 21:56 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 09/19] riscv: uaccess: Add alternative for xtheadvector uaccess Charlie Jenkins
2024-04-12 4:11 ` [PATCH 10/19] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-04-12 11:27 ` Conor Dooley
2024-04-12 18:22 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 11/19] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT Charlie Jenkins
2024-04-12 4:11 ` [PATCH 12/19] riscv: Create xtheadvector file Charlie Jenkins
2024-04-12 11:30 ` Conor Dooley
2024-04-12 18:24 ` Charlie Jenkins
2024-04-12 19:00 ` Conor Dooley
2024-04-12 20:53 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 13/19] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-04-12 4:11 ` [PATCH 14/19] riscv: hwprobe: Disambiguate vector and xtheadvector in hwprobe Charlie Jenkins
2024-04-12 11:34 ` Conor Dooley
2024-04-12 17:04 ` Evan Green
2024-04-12 18:22 ` Charlie Jenkins
2024-04-12 22:08 ` Evan Green
2024-04-12 22:37 ` Charlie Jenkins
2024-04-12 4:11 ` Charlie Jenkins [this message]
2024-04-12 11:37 ` [PATCH 15/19] riscv: hwcap: Add v to hwcap if xtheadvector enabled Conor Dooley
2024-04-12 18:26 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 16/19] riscv: hwprobe: Add vendor extension probing Charlie Jenkins
2024-04-12 11:39 ` Conor Dooley
2024-04-12 17:05 ` Evan Green
2024-04-12 18:16 ` Charlie Jenkins
2024-04-12 19:07 ` Evan Green
2024-04-12 20:20 ` Charlie Jenkins
2024-04-12 21:43 ` Evan Green
2024-04-12 22:21 ` Charlie Jenkins
2024-04-12 22:50 ` Evan Green
2024-04-12 23:12 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 17/19] riscv: hwprobe: Document vendor extensions and xtheadvector extension Charlie Jenkins
2024-04-12 4:11 ` [PATCH 18/19] selftests: riscv: Fix vector tests Charlie Jenkins
2024-04-12 4:11 ` [PATCH 19/19] selftests: riscv: Support xtheadvector in " Charlie Jenkins
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