From: Charlie Jenkins <charlie@rivosinc.com>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: "Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
"Palmer Dabbelt" <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH 06/19] riscv: Extend cpufeature.c to detect vendor extensions
Date: Fri, 12 Apr 2024 09:58:04 -0700 [thread overview]
Message-ID: <ZhloHGxa5jRRR9xg@ghost> (raw)
In-Reply-To: <20240412-sprawl-product-1e1d02e25bca@wendy>
On Fri, Apr 12, 2024 at 01:30:08PM +0100, Conor Dooley wrote:
> On Thu, Apr 11, 2024 at 09:11:12PM -0700, Charlie Jenkins wrote:
> > static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct riscv_isainfo *isainfo,
>
> > - unsigned long *isa2hwcap, const char *isa)
> > + struct riscv_isainfo *isavendorinfo, unsigned long vendorid,
> > + unsigned long *isa2hwcap, const char *isa)
> > {
> > /*
> > * For all possible cpus, we have already validated in
> > @@ -349,8 +384,30 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc
> > const char *ext = isa++;
> > const char *ext_end = isa;
> > bool ext_long = false, ext_err = false;
> > + struct riscv_isainfo *selected_isainfo = isainfo;
> > + const struct riscv_isa_ext_data *selected_riscv_isa_ext = riscv_isa_ext;
> > + size_t selected_riscv_isa_ext_count = riscv_isa_ext_count;
> > + unsigned int id_offset = 0;
> >
> > switch (*ext) {
> > + case 'x':
> > + case 'X':
>
> One quick remark is that we should not go and support this stuff via
> riscv,isa in my opinion, only allowing it for the riscv,isa-extensions
> parsing. We don't have a way to define meanings for vendor extensions in
> this way. ACPI also uses this codepath and at the moment the kernel's
> docs say we're gonna follow isa string parsing rules in a specific version
> of the ISA manual. While that manual provides a format for the string and
> meanings for standard extensions, there's nothing in there that allows us
> to get consistent meanings for specific vendor extensions, so I think we
> should avoid intentionally supporting this here.
Getting a "consistent meaning" is managed by a vendor. If a vendor
supports a vendor extension and puts it in their DT/ACPI table it's up
to them to ensure that it works. How does riscv,isa-extensions allow for
a consistent meaning?
>
> I'd probably go as far as to actively skip vendor extensions in
> riscv_parse_isa_string() to avoid any potential issues.
>
> > + bool found;
> > +
> > + found = get_isa_vendor_ext(vendorid,
> > + &selected_riscv_isa_ext,
> > + &selected_riscv_isa_ext_count);
> > + selected_isainfo = isavendorinfo;
> > + id_offset = RISCV_ISA_VENDOR_EXT_BASE;
> > + if (!found) {
> > + pr_warn("No associated vendor extensions with vendor id: %lx\n",
> > + vendorid);
>
> This should not be a warning, anything we don't understand should be
> silently ignored to avoid spamming just because the kernel has not grown
> support for it yet.
Sounds good.
- Charlie
>
> Thanks,
> Conor.
>
> > + for (; *isa && *isa != '_'; ++isa)
> > + ;
> > + ext_err = true;
> > + break;
> > + }
> > + fallthrough;
> > case 's':
> > /*
> > * Workaround for invalid single-letter 's' & 'u' (QEMU).
> > @@ -366,8 +423,6 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc
> > }
> > fallthrough;
> > case 'S':
> > - case 'x':
> > - case 'X':
> > case 'z':
> > case 'Z':
> > /*
> > @@ -476,8 +531,10 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc
> > set_bit(nr, isainfo->isa);
> > }
> > } else {
> > - for (int i = 0; i < riscv_isa_ext_count; i++)
> > - match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo);
> > + for (int i = 0; i < selected_riscv_isa_ext_count; i++)
> > + match_isa_ext(&selected_riscv_isa_ext[i], ext,
> > + ext_end, selected_isainfo,
> > + id_offset);
> > }
> > }
> > }
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next prev parent reply other threads:[~2024-04-12 16:58 UTC|newest]
Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-12 4:11 [PATCH 00/19] riscv: Support vendor extensions and xtheadvector Charlie Jenkins
2024-04-12 4:11 ` [PATCH 01/19] dt-bindings: riscv: Add vendorid and archid Charlie Jenkins
2024-04-12 9:57 ` Conor Dooley
2024-04-12 4:11 ` [PATCH 02/19] riscv: cpufeature: Fix thead vector hwcap removal Charlie Jenkins
2024-04-12 10:25 ` Conor Dooley
2024-04-12 17:04 ` Evan Green
2024-04-12 18:38 ` Conor Dooley
2024-04-12 18:46 ` Charlie Jenkins
2024-04-12 19:26 ` Conor Dooley
2024-04-12 20:34 ` Charlie Jenkins
2024-04-12 20:42 ` Conor Dooley
2024-04-12 17:12 ` Charlie Jenkins
2024-04-12 18:47 ` Conor Dooley
2024-04-12 20:48 ` Charlie Jenkins
2024-04-12 21:27 ` Conor Dooley
2024-04-12 21:31 ` Charlie Jenkins
2024-04-12 23:40 ` Conor Dooley
2024-04-16 3:34 ` Charlie Jenkins
2024-04-16 7:36 ` Conor Dooley
2024-04-17 4:25 ` Charlie Jenkins
2024-04-17 16:02 ` Evan Green
2024-04-17 22:02 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 03/19] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-04-12 10:27 ` Conor Dooley
2024-04-12 17:13 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 04/19] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-04-12 4:11 ` [PATCH 05/19] riscv: Fix extension subset checking Charlie Jenkins
2024-04-12 11:25 ` Conor Dooley
2024-04-12 4:11 ` [PATCH 06/19] riscv: Extend cpufeature.c to detect vendor extensions Charlie Jenkins
2024-04-12 12:30 ` Conor Dooley
2024-04-12 16:58 ` Charlie Jenkins [this message]
2024-04-12 18:59 ` Conor Dooley
2024-04-12 14:44 ` kernel test robot
2024-04-13 22:10 ` kernel test robot
2024-04-12 4:11 ` [PATCH 07/19] riscv: Optimize riscv_cpu_isa_extension_(un)likely() Charlie Jenkins
2024-04-12 10:40 ` Conor Dooley
2024-04-12 17:34 ` Charlie Jenkins
2024-04-12 20:33 ` Conor Dooley
2024-04-12 4:11 ` [PATCH 08/19] riscv: Introduce vendor variants of extension helpers Charlie Jenkins
2024-04-12 11:49 ` Conor Dooley
2024-04-12 17:43 ` Charlie Jenkins
2024-04-12 20:40 ` Conor Dooley
2024-04-12 21:03 ` Charlie Jenkins
2024-04-12 21:34 ` Conor Dooley
2024-04-12 21:56 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 09/19] riscv: uaccess: Add alternative for xtheadvector uaccess Charlie Jenkins
2024-04-12 4:11 ` [PATCH 10/19] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-04-12 11:27 ` Conor Dooley
2024-04-12 18:22 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 11/19] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT Charlie Jenkins
2024-04-12 4:11 ` [PATCH 12/19] riscv: Create xtheadvector file Charlie Jenkins
2024-04-12 11:30 ` Conor Dooley
2024-04-12 18:24 ` Charlie Jenkins
2024-04-12 19:00 ` Conor Dooley
2024-04-12 20:53 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 13/19] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-04-12 4:11 ` [PATCH 14/19] riscv: hwprobe: Disambiguate vector and xtheadvector in hwprobe Charlie Jenkins
2024-04-12 11:34 ` Conor Dooley
2024-04-12 17:04 ` Evan Green
2024-04-12 18:22 ` Charlie Jenkins
2024-04-12 22:08 ` Evan Green
2024-04-12 22:37 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 15/19] riscv: hwcap: Add v to hwcap if xtheadvector enabled Charlie Jenkins
2024-04-12 11:37 ` Conor Dooley
2024-04-12 18:26 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 16/19] riscv: hwprobe: Add vendor extension probing Charlie Jenkins
2024-04-12 11:39 ` Conor Dooley
2024-04-12 17:05 ` Evan Green
2024-04-12 18:16 ` Charlie Jenkins
2024-04-12 19:07 ` Evan Green
2024-04-12 20:20 ` Charlie Jenkins
2024-04-12 21:43 ` Evan Green
2024-04-12 22:21 ` Charlie Jenkins
2024-04-12 22:50 ` Evan Green
2024-04-12 23:12 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 17/19] riscv: hwprobe: Document vendor extensions and xtheadvector extension Charlie Jenkins
2024-04-12 4:11 ` [PATCH 18/19] selftests: riscv: Fix vector tests Charlie Jenkins
2024-04-12 4:11 ` [PATCH 19/19] selftests: riscv: Support xtheadvector in " Charlie Jenkins
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