LKML Archive mirror
 help / color / mirror / Atom feed
From: Catalin Marinas <catalin.marinas@arm.com>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: Will Deacon <will.deacon@arm.com>,
	Christoffer Dall <christoffer.dall@linaro.org>,
	kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org
Subject: Re: [PATCH v3 23/23] arm64: Panic when VHE and non VHE CPUs coexist
Date: Mon, 8 Feb 2016 16:04:46 +0000	[thread overview]
Message-ID: <20160208160445.GS6076@e104818-lin.cambridge.arm.com> (raw)
In-Reply-To: <1454522416-6874-24-git-send-email-marc.zyngier@arm.com>

On Wed, Feb 03, 2016 at 06:00:16PM +0000, Marc Zyngier wrote:
> Having both VHE and non-VHE capable CPUs in the same system
> is likely to be a recipe for disaster.
> 
> If the boot CPU has VHE, but a secondary is not, we won't be
> able to downgrade and run the kernel at EL1. Add CPU hotplug
> to the mix, and this produces a terrifying mess.
> 
> Let's solve the problem once and for all. If you mix VHE and
> non-VHE CPUs in the same system, you deserve to loose, and this
> patch makes sure you don't get a chance.
> 
> This is implemented by storing the kernel execution level in
> a global variable. Secondaries will park themselves in a
> WFI loop if they observe a mismatch. Also, the primary CPU
> will detect that the secondary CPU has died on a mismatched
> execution level. Panic will follow.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
>  arch/arm64/include/asm/virt.h | 17 +++++++++++++++++
>  arch/arm64/kernel/head.S      | 20 ++++++++++++++++++++
>  arch/arm64/kernel/smp.c       |  3 +++
>  3 files changed, 40 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/virt.h b/arch/arm64/include/asm/virt.h
> index 9f22dd6..f81a345 100644
> --- a/arch/arm64/include/asm/virt.h
> +++ b/arch/arm64/include/asm/virt.h
> @@ -36,6 +36,11 @@
>   */
>  extern u32 __boot_cpu_mode[2];
>  
> +/*
> + * __run_cpu_mode records the mode the boot CPU uses for the kernel.
> + */
> +extern u32 __run_cpu_mode[2];
> +
>  void __hyp_set_vectors(phys_addr_t phys_vector_base);
>  phys_addr_t __hyp_get_vectors(void);
>  
> @@ -60,6 +65,18 @@ static inline bool is_kernel_in_hyp_mode(void)
>  	return el == CurrentEL_EL2;
>  }
>  
> +static inline bool is_kernel_mode_mismatched(void)
> +{
> +	/*
> +	 * A mismatched CPU will have written its own CurrentEL in
> +	 * __run_cpu_mode[1] (initially set to zero) after failing to
> +	 * match the value in __run_cpu_mode[0]. Thus, a non-zero
> +	 * value in __run_cpu_mode[1] is enough to detect the
> +	 * pathological case.
> +	 */
> +	return !!ACCESS_ONCE(__run_cpu_mode[1]);
> +}
> +
>  /* The section containing the hypervisor text */
>  extern char __hyp_text_start[];
>  extern char __hyp_text_end[];
> diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
> index 6f2f377..f9b6a5b 100644
> --- a/arch/arm64/kernel/head.S
> +++ b/arch/arm64/kernel/head.S
> @@ -578,7 +578,24 @@ ENTRY(set_cpu_boot_mode_flag)
>  1:	str	w20, [x1]			// This CPU has booted in EL1
>  	dmb	sy
>  	dc	ivac, x1			// Invalidate potentially stale cache line
> +	adr_l	x1, __run_cpu_mode
> +	ldr	w0, [x1]
> +	mrs	x20, CurrentEL
> +	cbz	x0, skip_el_check
> +	cmp	x0, x20
> +	bne	mismatched_el
>  	ret
> +skip_el_check:			// Only the first CPU gets to set the rule
> +	str	w20, [x1]
> +	dmb	sy
> +	dc	ivac, x1	// Invalidate potentially stale cache line
> +	ret
> +mismatched_el:
> +	str	w20, [x1, #4]
> +	dmb	sy
> +	dc	ivac, x1	// Invalidate potentially stale cache line
> +1:	wfi
> +	b	1b
>  ENDPROC(set_cpu_boot_mode_flag)

Do we need to wait for the D-cache maintenance completion before
entering WFI (like issuing a DSB)? Same for the skip_el_check path
before the RET.

Otherwise:

Acked-by: Catalin Marinas <catalin.marinas@arm.com>

  parent reply	other threads:[~2016-02-08 16:04 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-03 17:59 [PATCH v3 00/23] arm64: Virtualization Host Extension support Marc Zyngier
2016-02-03 17:59 ` [PATCH v3 01/23] arm/arm64: KVM: Add hook for C-based stage2 init Marc Zyngier
2016-02-03 17:59 ` [PATCH v3 02/23] arm64: KVM: Switch to " Marc Zyngier
2016-02-03 17:59 ` [PATCH v3 03/23] arm/arm64: Add new is_kernel_in_hyp_mode predicate Marc Zyngier
2016-02-08 14:41   ` Catalin Marinas
2016-02-03 17:59 ` [PATCH v3 04/23] arm64: Allow the arch timer to use the HYP timer Marc Zyngier
2016-02-03 17:59 ` [PATCH v3 05/23] arm64: Add ARM64_HAS_VIRT_HOST_EXTN feature Marc Zyngier
2016-02-08 14:42   ` Catalin Marinas
2016-02-03 17:59 ` [PATCH v3 06/23] arm64: KVM: Skip HYP setup when already running in HYP Marc Zyngier
2016-02-03 18:00 ` [PATCH v3 07/23] arm64: KVM: VHE: Patch out use of HVC Marc Zyngier
2016-02-03 18:00 ` [PATCH v3 08/23] arm64: KVM: VHE: Patch out kern_hyp_va Marc Zyngier
2016-02-03 18:00 ` [PATCH v3 09/23] arm64: KVM: VHE: Introduce unified system register accessors Marc Zyngier
2016-02-03 18:00 ` [PATCH v3 10/23] arm64: KVM: VHE: Differenciate host/guest sysreg save/restore Marc Zyngier
2016-02-03 18:00 ` [PATCH v3 11/23] arm64: KVM: VHE: Split save/restore of registers shared between guest and host Marc Zyngier
2016-02-04 19:15   ` Christoffer Dall
2016-02-03 18:00 ` [PATCH v3 12/23] arm64: KVM: VHE: Use unified system register accessors Marc Zyngier
2016-02-03 18:00 ` [PATCH v3 13/23] arm64: KVM: VHE: Enable minimal sysreg save/restore Marc Zyngier
2016-02-03 18:00 ` [PATCH v3 14/23] arm64: KVM: VHE: Make __fpsimd_enabled VHE aware Marc Zyngier
2016-02-03 18:00 ` [PATCH v3 15/23] arm64: KVM: VHE: Implement VHE activate/deactivate_traps Marc Zyngier
2016-02-03 18:00 ` [PATCH v3 16/23] arm64: KVM: VHE: Use unified sysreg accessors for timer Marc Zyngier
2016-02-03 18:00 ` [PATCH v3 17/23] arm64: KVM: VHE: Add fpsimd enabling on guest access Marc Zyngier
2016-02-03 18:00 ` [PATCH v3 18/23] arm64: KVM: VHE: Add alternative panic handling Marc Zyngier
2016-02-03 18:00 ` [PATCH v3 19/23] arm64: KVM: Move most of the fault decoding to C Marc Zyngier
2016-02-04 19:20   ` Christoffer Dall
2016-02-08 14:44   ` Catalin Marinas
2016-02-03 18:00 ` [PATCH v3 20/23] arm64: perf: Count EL2 events if the kernel is running in HYP Marc Zyngier
2016-02-04 19:23   ` Christoffer Dall
2016-02-05  9:02     ` Marc Zyngier
2016-02-08 14:48   ` Catalin Marinas
2016-02-03 18:00 ` [PATCH v3 21/23] arm64: hw_breakpoint: Allow EL2 breakpoints if " Marc Zyngier
2016-02-08 15:56   ` Catalin Marinas
2016-02-08 16:45     ` Marc Zyngier
2016-02-08 16:52       ` Catalin Marinas
2016-02-03 18:00 ` [PATCH v3 22/23] arm64: VHE: Add support for running Linux in EL2 mode Marc Zyngier
2016-02-04 19:25   ` Christoffer Dall
2016-02-08 15:58   ` Catalin Marinas
2016-02-03 18:00 ` [PATCH v3 23/23] arm64: Panic when VHE and non VHE CPUs coexist Marc Zyngier
2016-02-04 19:25   ` Christoffer Dall
2016-02-08 16:04   ` Catalin Marinas [this message]
2016-02-08 16:24     ` Mark Rutland
2016-02-09 12:02       ` Catalin Marinas
2016-02-04 19:26 ` [PATCH v3 00/23] arm64: Virtualization Host Extension support Christoffer Dall
2016-02-05  8:56   ` Marc Zyngier

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20160208160445.GS6076@e104818-lin.cambridge.arm.com \
    --to=catalin.marinas@arm.com \
    --cc=christoffer.dall@linaro.org \
    --cc=kvm@vger.kernel.org \
    --cc=kvmarm@lists.cs.columbia.edu \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=marc.zyngier@arm.com \
    --cc=will.deacon@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).