From: Vinod Koul <vinod.koul@intel.com>
To: Sinan Kaya <okaya@codeaurora.org>
Cc: dmaengine@vger.kernel.org, marc.zyngier@arm.com,
mark.rutland@arm.com, timur@codeaurora.org,
devicetree@vger.kernel.org, cov@codeaurora.org, jcm@redhat.com,
shankerd@codeaurora.org, vikrams@codeaurora.org,
eric.auger@linaro.org, agross@codeaurora.org, arnd@arndb.de,
linux-arm-msm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH V14 5/9] dma: qcom_hidma: implement lower level hardware interface
Date: Fri, 11 Mar 2016 07:36:50 +0530 [thread overview]
Message-ID: <20160311020650.GG11154@localhost> (raw)
In-Reply-To: <1454646882-24369-6-git-send-email-okaya@codeaurora.org>
On Thu, Feb 04, 2016 at 11:34:36PM -0500, Sinan Kaya wrote:
> +
> +#define EVRE_SIZE 16 /* each EVRE is 16 bytes */
> +
> +#define TRCA_CTRLSTS_OFFSET 0x000
> +#define TRCA_RING_LOW_OFFSET 0x008
> +#define TRCA_RING_HIGH_OFFSET 0x00C
> +#define TRCA_RING_LEN_OFFSET 0x010
> +#define TRCA_READ_PTR_OFFSET 0x018
> +#define TRCA_WRITE_PTR_OFFSET 0x020
> +#define TRCA_DOORBELL_OFFSET 0x400
> +
> +#define EVCA_CTRLSTS_OFFSET 0x000
> +#define EVCA_INTCTRL_OFFSET 0x004
> +#define EVCA_RING_LOW_OFFSET 0x008
> +#define EVCA_RING_HIGH_OFFSET 0x00C
> +#define EVCA_RING_LEN_OFFSET 0x010
> +#define EVCA_READ_PTR_OFFSET 0x018
> +#define EVCA_WRITE_PTR_OFFSET 0x020
> +#define EVCA_DOORBELL_OFFSET 0x400
> +
> +#define EVCA_IRQ_STAT_OFFSET 0x100
> +#define EVCA_IRQ_CLR_OFFSET 0x108
> +#define EVCA_IRQ_EN_OFFSET 0x110
> +
> +#define EVRE_CFG_IDX 0
> +#define EVRE_LEN_IDX 1
> +#define EVRE_DEST_LOW_IDX 2
> +#define EVRE_DEST_HI_IDX 3
> +
> +#define EVRE_ERRINFO_BIT_POS 24
> +#define EVRE_CODE_BIT_POS 28
> +
> +#define EVRE_ERRINFO_MASK GENMASK(3, 0)
> +#define EVRE_CODE_MASK GENMASK(3, 0)
These are rest here are not namespace properly...
> +static int hidma_ll_enable(struct hidma_lldev *lldev)
> +{
> + u32 val;
> + int ret;
> +
> + val = readl(lldev->evca + EVCA_CTRLSTS_OFFSET);
> + val &= ~(CH_CONTROL_MASK << 16);
> + val |= CH_ENABLE << 16;
> + writel(val, lldev->evca + EVCA_CTRLSTS_OFFSET);
> +
> + ret = readl_poll_timeout(lldev->evca + EVCA_CTRLSTS_OFFSET, val,
> + (HIDMA_CH_STATE(val) == CH_ENABLED) ||
> + (HIDMA_CH_STATE(val) == CH_RUNNING), 1000,
> + 10000);
> + if (ret) {
> + dev_err(lldev->dev, "event channel did not get enabled\n");
> + return ret;
> + }
> +
> + val = readl(lldev->trca + TRCA_CTRLSTS_OFFSET);
> + val &= ~(CH_CONTROL_MASK << 16);
> + val |= CH_ENABLE << 16;
> + writel(val, lldev->trca + TRCA_CTRLSTS_OFFSET);
> +
> + ret = readl_poll_timeout(lldev->trca + TRCA_CTRLSTS_OFFSET, val,
> + (HIDMA_CH_STATE(val) == CH_ENABLED) ||
> + (HIDMA_CH_STATE(val) == CH_RUNNING), 1000,
> + 10000);
first arg for readl_poll_timeout is accessor fn to do read, which doesnt
seem to be here... so what did i miss?
> +void hidma_ll_queue_request(struct hidma_lldev *lldev, u32 tre_ch)
> +{
> + struct hidma_tre *tre;
> + unsigned long flags;
> +
> + tre = &lldev->trepool[tre_ch];
> +
> + /* copy the TRE into its location in the TRE ring */
> + spin_lock_irqsave(&lldev->lock, flags);
> + tre->tre_index = lldev->tre_write_offset / TRE_SIZE;
> + lldev->pending_tre_list[tre->tre_index] = tre;
> + memcpy(lldev->tre_ring + lldev->tre_write_offset, &tre->tre_local[0],
> + TRE_SIZE);
> + lldev->tx_status_list[tre->idx].err_code = 0;
> + lldev->tx_status_list[tre->idx].err_info = 0;
> + tre->queued = 1;
> + lldev->pending_tre_count++;
> + lldev->tre_write_offset = (lldev->tre_write_offset + TRE_SIZE)
> + % lldev->tre_ring_size;
These and above one should be right justfied per coding style
--
~Vinod
next prev parent reply other threads:[~2016-03-11 2:03 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-05 4:34 [PATCH V14 0/9] dma: add Qualcomm Technologies HIDMA driver Sinan Kaya
2016-02-05 4:34 ` [PATCH V14 1/9] dma: qcom_bam_dma: move to qcom directory Sinan Kaya
2016-03-11 2:13 ` Vinod Koul
2016-02-05 4:34 ` [PATCH V14 2/9] dma: hidma: Add Device Tree binding Sinan Kaya
2016-03-11 2:16 ` Vinod Koul
2016-02-05 4:34 ` [PATCH V14 3/9] dma: add Qualcomm Technologies HIDMA management driver Sinan Kaya
2016-03-11 2:16 ` Vinod Koul
2016-02-05 4:34 ` [PATCH V14 4/9] dma: add Qualcomm Technologies HIDMA channel driver Sinan Kaya
2016-03-11 2:17 ` Vinod Koul
2016-02-05 4:34 ` [PATCH V14 5/9] dma: qcom_hidma: implement lower level hardware interface Sinan Kaya
2016-03-11 2:06 ` Vinod Koul [this message]
2016-03-11 3:08 ` Okaya
2016-03-11 16:02 ` Sinan Kaya
2016-03-11 16:32 ` Vinod Koul
2016-03-11 16:44 ` Sinan Kaya
2016-03-11 19:29 ` Sinan Kaya
2016-03-11 21:59 ` Sinan Kaya
2016-03-13 16:00 ` Vinod Koul
2016-03-14 13:53 ` Sinan Kaya
2016-03-13 15:59 ` Vinod Koul
2016-03-14 13:56 ` Sinan Kaya
2016-02-05 4:34 ` [PATCH V14 6/9] dma: qcom_hidma: add debugfs hooks Sinan Kaya
2016-02-05 4:34 ` [PATCH V14 7/9] dma: qcom_hidma: add support for object hierarchy Sinan Kaya
2016-02-05 4:34 ` [PATCH V14 8/9] vfio, platform: add support for ACPI while detecting the reset driver Sinan Kaya
2016-02-26 16:24 ` Sinan Kaya
2016-02-26 17:15 ` Eric Auger
2016-02-26 19:21 ` Sinan Kaya
2016-03-02 18:34 ` Sinan Kaya
2016-03-03 23:14 ` Eric Auger
2016-03-04 5:20 ` Sinan Kaya
2016-03-07 4:09 ` Eric Auger
2016-03-07 15:30 ` Sinan Kaya
2016-03-08 4:46 ` Eric Auger
2016-03-08 5:07 ` Sinan Kaya
2016-03-08 15:44 ` Sinan Kaya
2016-02-05 4:34 ` [PATCH V14 9/9] vfio, platform: add QTI HIDMA " Sinan Kaya
2016-02-26 17:52 ` Eric Auger
2016-02-26 19:05 ` Sinan Kaya
2016-02-08 10:14 ` [PATCH V14 0/9] dma: add Qualcomm Technologies HIDMA driver Christoffer Dall
2016-02-08 14:24 ` Sinan Kaya
2016-02-08 17:00 ` Christoffer Dall
2016-02-26 16:21 ` Sinan Kaya
2016-02-26 16:52 ` Timur Tabi
2016-03-02 18:40 ` Sinan Kaya
2016-03-03 3:44 ` Vinod Koul
2016-03-03 15:22 ` Sinan Kaya
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