From: Andrew Jones <ajones@ventanamicro.com>
To: Conor Dooley <conor@kernel.org>
Cc: Xu Lu <luxu.kernel@bytedance.com>,
paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, andy.chiu@sifive.com, guoren@kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
lihangjing@bytedance.com, dengliang.1214@bytedance.com,
xieyongji@bytedance.com, chaiwen.cc@bytedance.com
Subject: Re: [RFC 1/2] riscv: process: Introduce idle thread using Zawrs extension
Date: Thu, 18 Apr 2024 21:10:54 +0200 [thread overview]
Message-ID: <20240418-d9f305770dc71c2687a6e84b@orel> (raw)
In-Reply-To: <20240418-dove-deferral-2b01100e13ca@spud>
On Thu, Apr 18, 2024 at 04:05:55PM +0100, Conor Dooley wrote:
> + Drew,
>
> On Thu, Apr 18, 2024 at 07:49:41PM +0800, Xu Lu wrote:
> > The Zawrs extension introduces a new instruction WRS.NTO, which will
> > register a reservation set and causes the hart to temporarily stall
> > execution in a low-power state until a store occurs to the reservation
> > set or an interrupt is observed.
> >
> > This commit implements new version of idle thread for RISC-V via Zawrs
> > extension.
> >
> > Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
> > Reviewed-by: Hangjing Li <lihangjing@bytedance.com>
> > Reviewed-by: Liang Deng <dengliang.1214@bytedance.com>
> > Reviewed-by: Wen Chai <chaiwen.cc@bytedance.com>
> > ---
> > arch/riscv/Kconfig | 24 +++++++++++++++++
> > arch/riscv/include/asm/cpuidle.h | 11 +-------
> > arch/riscv/include/asm/hwcap.h | 1 +
> > arch/riscv/include/asm/processor.h | 17 +++++++++++++
> > arch/riscv/kernel/cpu.c | 5 ++++
> > arch/riscv/kernel/cpufeature.c | 1 +
> > arch/riscv/kernel/process.c | 41 +++++++++++++++++++++++++++++-
> > 7 files changed, 89 insertions(+), 11 deletions(-)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index be09c8836d56..a0d344e9803f 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -19,6 +19,7 @@ config RISCV
> > select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
> > select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
> > select ARCH_HAS_BINFMT_FLAT
> > + select ARCH_HAS_CPU_FINALIZE_INIT
> > select ARCH_HAS_CURRENT_STACK_POINTER
> > select ARCH_HAS_DEBUG_VIRTUAL if MMU
> > select ARCH_HAS_DEBUG_VM_PGTABLE
> > @@ -525,6 +526,20 @@ config RISCV_ISA_SVPBMT
> >
> > If you don't know what to do here, say Y.
> >
> > +config RISCV_ISA_ZAWRS
> > + bool "Zawrs extension support for wait-on-reservation-set instructions"
> > + depends on RISCV_ALTERNATIVE
> > + default y
> > + help
> > + Adds support to dynamically detect the presence of the Zawrs
> > + extension and enable its usage.
>
> Drew, could you, in your update, use the wording:
> Add support for enabling optimisations in the kernel when the
> Zawrs extension is detected at boot.
How about
The Zawrs extension defines a pair of instructions to be used in
polling loops which allow a hart to enter a low-power state or to
trap to the hypervisor while waiting on a store to a memory location.
Enable the use of these instructions when the Zawrs extension is
detected at boot.
Thanks,
drew
next prev parent reply other threads:[~2024-04-18 19:10 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-18 11:49 [RFC 0/2] riscv: Idle thread using Zawrs extension Xu Lu
2024-04-18 11:49 ` [RFC 1/2] riscv: process: Introduce idle " Xu Lu
2024-04-18 15:05 ` Conor Dooley
2024-04-18 16:14 ` [External] " Xu Lu
2024-04-22 8:21 ` Conor Dooley
2024-04-18 19:10 ` Andrew Jones [this message]
2024-04-18 22:00 ` Samuel Holland
2024-04-18 22:09 ` Conor Dooley
2024-04-18 11:49 ` [RFC 2/2] riscv: Use Zawrs to accelerate IPI to idle cpu Xu Lu
2024-04-18 12:26 ` [RFC 0/2] riscv: Idle thread using Zawrs extension Christoph Müllner
2024-04-18 12:44 ` [External] " Xu Lu
2024-04-18 12:56 ` Christoph Müllner
2024-04-18 13:09 ` Xu Lu
2024-04-18 14:08 ` Conor Dooley
2024-04-18 14:10 ` Andrew Jones
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