From: Irina Ryapolova <irina.ryapolova@syntacore.com>
To: <qemu-devel@nongnu.org>
Cc: <qemu-riscv@nongnu.org>, <palmer@dabbelt.com>,
<alistair.francis@wdc.com>, <bin.meng@windriver.com>,
<liwei1518@gmail.com>, <dbarboza@ventanamicro.com>,
<zhiwei_liu@linux.alibaba.com>,
Irina Ryapolova <irina.ryapolova@syntacore.com>
Subject: [PATCH 1/2] target/riscv/csr.c: Add functional of hvictl CSR
Date: Mon, 12 Feb 2024 20:13:19 +0300 [thread overview]
Message-ID: <20240212171320.47361-1-irina.ryapolova@syntacore.com> (raw)
CSR hvictl (Hypervisor Virtual Interrupt Control) provides further flexibility
for injecting interrupts into VS level in situations not fully supported by the
facilities described thus far, but only with more active involvement of the hypervisor.
(See riscv-interrupts-1.0: Interrupts at VS level)
Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com>
---
target/riscv/csr.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 674ea075a4..0c21145eaf 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3585,6 +3585,21 @@ static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val)
static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val)
{
env->hvictl = val & HVICTL_VALID_MASK;
+ if (env->hvictl & HVICTL_VTI)
+ {
+ uint32_t hviid = get_field(env->hvictl, HVICTL_IID);
+ uint32_t hviprio = get_field(env->hvictl, HVICTL_IPRIO);
+ /* the pair IID = 9, IPRIO = 0 generally to represent no interrupt in hvictl. */
+ if (!(hviid == IRQ_S_EXT && hviprio == 0)) {
+ uint64_t new_val = BIT(hviid) ;
+ if (new_val & S_MODE_INTERRUPTS) {
+ rmw_hvip64(env, csrno, NULL, new_val << 1, new_val << 1);
+ } else if (new_val & LOCAL_INTERRUPTS) {
+ rmw_hvip64(env, csrno, NULL, new_val, new_val);
+ }
+ }
+ }
+
return RISCV_EXCP_NONE;
}
--
2.25.1
next reply other threads:[~2024-02-12 17:14 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-12 17:13 Irina Ryapolova [this message]
2024-02-12 17:13 ` [PATCH 2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS Irina Ryapolova
-- strict thread matches above, loose matches on Subject: below --
2024-02-12 17:11 [PATCH 1/2] target/riscv/csr.c: Add functional of hvictl CSR Irina Ryapolova
2024-02-15 9:42 ` Alistair Francis
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