From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liwei1518@gmail.com,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
richard.henderson@linaro.org, max.chou@sifive.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v2 1/3] trans_rvv.c.inc: write CSRs must call mark_vs_dirty() too
Date: Fri, 16 Feb 2024 10:57:17 -0300 [thread overview]
Message-ID: <20240216135719.1034289-2-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20240216135719.1034289-1-dbarboza@ventanamicro.com>
In the Vector spec section 3.2 [1]:
"When mstatus.VS is set to Initial or Clean, executing any instruction
that changes vector state, including the vector CSRs, will change
mstatus.VS to Dirty."
ldst_us_trans(), ldst_stride_trans(), ldst_index_trans() and
ldst_whole_trans() will change vector state regardless of being a store
op or not. Stores will set env->vstart to zero after execution (see
vext_ldst_us() in vector_helper.c), and this is vector CSR state change.
[1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-start-index-csr-vstart
Fixes: 8e1ee1fb57 ("target/riscv: rvv-1.0: add translation-time vector context status")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 19 ++++---------------
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 9e101ab434..044c9c903e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -638,10 +638,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
fn(dest, mask, base, tcg_env, desc);
- if (!is_store) {
- mark_vs_dirty(s);
- }
-
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -799,10 +796,7 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
fn(dest, mask, base, stride, tcg_env, desc);
- if (!is_store) {
- mark_vs_dirty(s);
- }
-
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -906,10 +900,7 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
fn(dest, mask, base, index, tcg_env, desc);
- if (!is_store) {
- mark_vs_dirty(s);
- }
-
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -1104,9 +1095,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
fn(dest, base, tcg_env, desc);
- if (!is_store) {
- mark_vs_dirty(s);
- }
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
--
2.43.0
next prev parent reply other threads:[~2024-02-16 13:57 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-16 13:57 [PATCH v2 0/3] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
2024-02-16 13:57 ` Daniel Henrique Barboza [this message]
2024-02-16 19:06 ` [PATCH v2 1/3] trans_rvv.c.inc: write CSRs must call mark_vs_dirty() too Richard Henderson
2024-02-16 13:57 ` [PATCH v2 2/3] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls Daniel Henrique Barboza
2024-02-16 13:57 ` [PATCH v2 3/3] target/riscv/translate.c: set vstart_eq_zero in mark_vs_dirty() Daniel Henrique Barboza
2024-02-16 18:56 ` Richard Henderson
2024-02-16 22:40 ` Daniel Henrique Barboza
2024-02-16 23:41 ` Richard Henderson
2024-02-17 2:36 ` Daniel Henrique Barboza
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