From: Alvin Chang via <qemu-riscv@nongnu.org>
To: <qemu-riscv@nongnu.org>, <qemu-devel@nongnu.org>
Cc: <alistair.francis@wdc.com>, <bin.meng@windriver.com>,
<liwei1518@gmail.com>, <dbarboza@ventanamicro.com>,
<zhiwei_liu@linux.alibaba.com>,
Alvin Chang <alvinga@andestech.com>
Subject: [PATCH 1/4] target/riscv: Add functions for common matching conditions of trigger
Date: Mon, 19 Feb 2024 11:25:56 +0800 [thread overview]
Message-ID: <20240219032559.79665-2-alvinga@andestech.com> (raw)
In-Reply-To: <20240219032559.79665-1-alvinga@andestech.com>
According to RISC-V Debug specification, there are several common
matching conditions before firing a trigger, including the enabled
privilege levels of the trigger.
This commit adds trigger_common_match() to prepare the common matching
conditions for the type 2/3/6 triggers. For now, we just implement
trigger_priv_match() to check if the enabled privilege levels of the
trigger match CPU's current privilege level.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
---
target/riscv/debug.c | 70 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index e30d99cc2f..7932233073 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -241,6 +241,76 @@ static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index)
}
}
+/*
+ * Check the privilege level of specific trigger matches CPU's current privilege
+ * level.
+ */
+static bool trigger_priv_match(CPURISCVState *env, trigger_type_t type,
+ int trigger_index)
+{
+ target_ulong ctrl = env->tdata1[trigger_index];
+
+ switch (type) {
+ case TRIGGER_TYPE_AD_MATCH:
+ /* type 2 trigger cannot be fired in VU/VS mode */
+ if (env->virt_enabled) {
+ return false;
+ }
+ /* check U/S/M bit against current privilege level */
+ if ((ctrl >> 3) & BIT(env->priv)) {
+ return true;
+ }
+ break;
+ case TRIGGER_TYPE_AD_MATCH6:
+ if (env->virt_enabled) {
+ /* check VU/VS bit against current privilege level */
+ if ((ctrl >> 23) & BIT(env->priv)) {
+ return true;
+ }
+ } else {
+ /* check U/S/M bit against current privilege level */
+ if ((ctrl >> 3) & BIT(env->priv)) {
+ return true;
+ }
+ }
+ break;
+ case TRIGGER_TYPE_INST_CNT:
+ if (env->virt_enabled) {
+ /* check VU/VS bit against current privilege level */
+ if ((ctrl >> 25) & BIT(env->priv)) {
+ return true;
+ }
+ } else {
+ /* check U/S/M bit against current privilege level */
+ if ((ctrl >> 6) & BIT(env->priv)) {
+ return true;
+ }
+ }
+ break;
+ case TRIGGER_TYPE_INT:
+ case TRIGGER_TYPE_EXCP:
+ case TRIGGER_TYPE_EXT_SRC:
+ qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n", type);
+ break;
+ case TRIGGER_TYPE_NO_EXIST:
+ case TRIGGER_TYPE_UNAVAIL:
+ qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n",
+ type);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ return false;
+}
+
+/* Common matching conditions for all types of the triggers. */
+static bool trigger_common_match(CPURISCVState *env, trigger_type_t type,
+ int trigger_index)
+{
+ return trigger_priv_match(env, type, trigger_index);
+}
+
/* type 2 trigger */
static uint32_t type2_breakpoint_size(CPURISCVState *env, target_ulong ctrl)
--
2.34.1
next prev parent reply other threads:[~2024-02-19 3:26 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-19 3:25 [PATCH 0/4] RISC-V: Modularize common match conditions for trigger Alvin Chang via
2024-02-19 3:25 ` Alvin Chang via [this message]
2024-02-21 17:09 ` [PATCH 1/4] target/riscv: Add functions for common matching conditions of trigger Daniel Henrique Barboza
2024-02-19 3:25 ` [PATCH 2/4] target/riscv: Apply modularized matching conditions for breakpoint Alvin Chang via
2024-02-21 17:25 ` Daniel Henrique Barboza
2024-02-22 1:46 ` Alvin Che-Chia Chang(張哲嘉)
2024-02-22 12:37 ` Daniel Henrique Barboza
2024-02-19 3:25 ` [PATCH 3/4] target/riscv: Apply modularized matching conditions for watchpoint Alvin Chang via
2024-02-21 17:31 ` Daniel Henrique Barboza
2024-02-19 3:25 ` [PATCH 4/4] target/riscv: Apply modularized matching conditions for icount trigger Alvin Chang via
2024-02-21 18:05 ` Daniel Henrique Barboza
2024-02-22 2:05 ` Alvin Che-Chia Chang(張哲嘉)
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